9ebe9808dda4fcc96a7d9c403eb9d96e284285fa
3 * Copyright © 2010-2015 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
32 class fs_reg
: public backend_reg
{
34 DECLARE_RALLOC_CXX_OPERATORS(fs_reg
)
39 explicit fs_reg(float f
);
40 explicit fs_reg(int32_t i
);
41 explicit fs_reg(uint32_t u
);
42 explicit fs_reg(uint8_t vf
[4]);
43 explicit fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
);
44 fs_reg(struct brw_reg fixed_hw_reg
);
45 fs_reg(enum register_file file
, int reg
);
46 fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
);
47 fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
, uint8_t width
);
49 bool equals(const fs_reg
&r
) const;
50 bool is_contiguous() const;
52 /** Smear a channel of the reg to all channels. */
53 fs_reg
&set_smear(unsigned subreg
);
56 * Offset in bytes from the start of the register. Values up to a
57 * backend_reg::reg_offset unit are valid.
64 * The register width. This indicates how many hardware values are
65 * represented by each virtual value. Valid values are 1, 8, or 16.
66 * For immediate values, this is 1. Most of the rest of the time, it
67 * will be equal to the dispatch width.
72 * Returns the effective register width when used as a source in the
73 * given instruction. Registers such as uniforms and immediates
74 * effectively take on the width of the instruction in which they are
77 uint8_t effective_width
;
79 /** Register region horizontal stride */
86 assert(reg
.file
!= HW_REG
&& reg
.file
!= IMM
);
87 reg
.negate
= !reg
.negate
;
92 retype(fs_reg reg
, enum brw_reg_type type
)
94 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
99 byte_offset(fs_reg reg
, unsigned delta
)
106 reg
.reg_offset
+= delta
/ 32;
109 reg
.reg
+= delta
/ 32;
114 reg
.subreg_offset
+= delta
% 32;
119 horiz_offset(fs_reg reg
, unsigned delta
)
125 /* These only have a single component that is implicitly splatted. A
126 * horizontal offset should be a harmless no-op.
132 return byte_offset(reg
, delta
* reg
.stride
* type_sz(reg
.type
));
140 offset(fs_reg reg
, unsigned delta
)
142 assert(reg
.stride
> 0);
149 return byte_offset(reg
, delta
* reg
.width
* reg
.stride
* type_sz(reg
.type
));
151 reg
.reg_offset
+= delta
;
160 component(fs_reg reg
, unsigned idx
)
162 assert(reg
.subreg_offset
== 0);
163 assert(idx
< reg
.width
);
164 reg
.subreg_offset
= idx
* type_sz(reg
.type
);
170 is_uniform(const fs_reg
®
)
172 return (reg
.width
== 1 || reg
.stride
== 0 || reg
.is_null()) &&
173 (!reg
.reladdr
|| is_uniform(*reg
.reladdr
));
177 * Get either of the 8-component halves of a 16-component register.
179 * Note: this also works if \c reg represents a SIMD16 pair of registers.
182 half(fs_reg reg
, unsigned idx
)
194 assert(reg
.width
== 16);
196 return horiz_offset(reg
, 8 * idx
);
201 unreachable("Cannot take half of this register type");
206 static const fs_reg reg_undef
;
208 class fs_inst
: public backend_instruction
{
209 fs_inst
&operator=(const fs_inst
&);
211 void init(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
212 const fs_reg
*src
, unsigned sources
);
215 DECLARE_RALLOC_CXX_OPERATORS(fs_inst
)
218 fs_inst(enum opcode opcode
, uint8_t exec_size
);
219 fs_inst(enum opcode opcode
, const fs_reg
&dst
);
220 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
222 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
);
223 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
224 const fs_reg
&src0
, const fs_reg
&src1
);
225 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
227 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
228 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
);
229 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
230 const fs_reg
&src1
, const fs_reg
&src2
);
231 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg src
[],
233 fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
234 const fs_reg src
[], unsigned sources
);
235 fs_inst(const fs_inst
&that
);
238 void resize_sources(uint8_t num_sources
);
240 bool equals(fs_inst
*inst
) const;
241 bool overwrites_reg(const fs_reg
®
) const;
242 bool is_send_from_grf() const;
243 bool is_partial_write() const;
244 int regs_read(int arg
) const;
245 bool can_do_source_mods(const struct brw_device_info
*devinfo
);
246 bool has_side_effects() const;
248 bool reads_flag() const;
249 bool writes_flag() const;
254 uint8_t sources
; /**< Number of fs_reg sources. */
257 * Execution size of the instruction. This is used by the generator to
258 * generate the correct binary for the given fs_inst. Current valid
259 * values are 1, 8, 16.
264 bool force_uncompressed
:1;
265 bool force_sechalf
:1;
266 bool pi_noperspective
:1; /**< Pixel interpolator noperspective flag */