src/mesa/drivers/dri/i965/brw_ir_fs.h

   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright © 2010-2015 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef BRW_IR_FS_H
  26 #define BRW_IR_FS_H
  27
  28 #include "brw_shader.h"
  29
  30 class fs_inst;
  31
  32 class fs_reg : public backend_reg {
  33 public:
  34    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  35
  36    void init();
  37
  38    fs_reg();
  39    fs_reg(struct ::brw_reg reg);
  40    fs_reg(enum brw_reg_file file, int nr);
  41    fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
  42
  43    bool equals(const fs_reg &r) const;
  44    bool is_contiguous() const;
  45
  46    /**
  47     * Return the size in bytes of a single logical component of the
  48     * register assuming the given execution width.
  49     */
  50    unsigned component_size(unsigned width) const;
  51
  52    /** Smear a channel of the reg to all channels. */
  53    fs_reg &set_smear(unsigned subreg);
  54
  55    /**
  56     * Offset in bytes from the start of the register.  Values up to a
  57     * backend_reg::reg_offset unit are valid.
  58     */
  59    int subreg_offset;
  60
  61    /** Register region horizontal stride */
  62    uint8_t stride;
  63 };
  64
  65 static inline fs_reg
  66 negate(fs_reg reg)
  67 {
  68    assert(reg.file != IMM);
  69    reg.negate = !reg.negate;
  70    return reg;
  71 }
  72
  73 static inline fs_reg
  74 retype(fs_reg reg, enum brw_reg_type type)
  75 {
  76    reg.type = type;
  77    return reg;
  78 }
  79
  80 static inline fs_reg
  81 byte_offset(fs_reg reg, unsigned delta)
  82 {
  83    switch (reg.file) {
  84    case BAD_FILE:
  85       break;
  86    case VGRF:
  87    case ATTR:
  88    case UNIFORM: {
  89       const unsigned reg_size = (reg.file == UNIFORM ? 4 : REG_SIZE);
  90       const unsigned suboffset = reg.subreg_offset + delta;
  91       reg.reg_offset += suboffset / reg_size;
  92       reg.subreg_offset = suboffset % reg_size;
  93       break;
  94    }
  95    case MRF: {
  96       const unsigned suboffset = reg.subreg_offset + delta;
  97       reg.nr += suboffset / REG_SIZE;
  98       reg.subreg_offset = suboffset % REG_SIZE;
  99       break;
 100    }
 101    case ARF:
 102    case FIXED_GRF: {
 103       const unsigned suboffset = reg.subnr + delta;
 104       reg.nr += suboffset / REG_SIZE;
 105       reg.subnr = suboffset % REG_SIZE;
 106       break;
 107    }
 108    case IMM:
 109    default:
 110       assert(delta == 0);
 111    }
 112    return reg;
 113 }
 114
 115 static inline fs_reg
 116 horiz_offset(const fs_reg &reg, unsigned delta)
 117 {
 118    switch (reg.file) {
 119    case BAD_FILE:
 120    case UNIFORM:
 121    case IMM:
 122       /* These only have a single component that is implicitly splatted.  A
 123        * horizontal offset should be a harmless no-op.
 124        * XXX - Handle vector immediates correctly.
 125        */
 126       return reg;
 127    case VGRF:
 128    case MRF:
 129    case ATTR:
 130       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 131    case ARF:
 132    case FIXED_GRF:
 133       if (reg.is_null()) {
 134          return reg;
 135       } else {
 136          const unsigned stride = reg.hstride ? 1 << (reg.hstride - 1) : 0;
 137          return byte_offset(reg, delta * stride * type_sz(reg.type));
 138       }
 139    }
 140    unreachable("Invalid register file");
 141 }
 142
 143 static inline fs_reg
 144 offset(fs_reg reg, unsigned width, unsigned delta)
 145 {
 146    switch (reg.file) {
 147    case BAD_FILE:
 148       break;
 149    case ARF:
 150    case FIXED_GRF:
 151    case MRF:
 152    case VGRF:
 153    case ATTR:
 154    case UNIFORM:
 155       return byte_offset(reg, delta * reg.component_size(width));
 156    case IMM:
 157       assert(delta == 0);
 158    }
 159    return reg;
 160 }
 161
 162 /**
 163  * Get the scalar channel of \p reg given by \p idx and replicate it to all
 164  * channels of the result.
 165  */
 166 static inline fs_reg
 167 component(fs_reg reg, unsigned idx)
 168 {
 169    reg = horiz_offset(reg, idx);
 170    reg.stride = 0;
 171    return reg;
 172 }
 173
 174 /**
 175  * Return an integer identifying the discrete address space a register is
 176  * contained in.  A register is by definition fully contained in the single
 177  * reg_space it belongs to, so two registers with different reg_space ids are
 178  * guaranteed not to overlap.  Most register files are a single reg_space of
 179  * its own, only the VGRF file is composed of multiple discrete address
 180  * spaces, one for each VGRF allocation.
 181  */
 182 static inline uint32_t
 183 reg_space(const fs_reg &r)
 184 {
 185    return r.file << 16 | (r.file == VGRF ? r.nr : 0);
 186 }
 187
 188 /**
 189  * Return the base offset in bytes of a register relative to the start of its
 190  * reg_space().
 191  */
 192 static inline unsigned
 193 reg_offset(const fs_reg &r)
 194 {
 195    return ((r.file == VGRF || r.file == IMM ? 0 : r.nr) + r.reg_offset) *
 196           (r.file == UNIFORM ? 4 : REG_SIZE) + r.subreg_offset;
 197 }
 198
 199 /**
 200  * Return whether the register region starting at \p r and spanning \p dr
 201  * bytes could potentially overlap the register region starting at \p s and
 202  * spanning \p ds bytes.
 203  */
 204 static inline bool
 205 regions_overlap(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
 206 {
 207    if (r.file == MRF && (r.nr & BRW_MRF_COMPR4)) {
 208       fs_reg t = r;
 209       t.nr &= ~BRW_MRF_COMPR4;
 210       /* COMPR4 regions are translated by the hardware during decompression
 211        * into two separate half-regions 4 MRFs apart from each other.
 212        */
 213       return regions_overlap(t, dr / 2, s, ds) ||
 214              regions_overlap(byte_offset(t, 4 * REG_SIZE), dr / 2, s, ds);
 215
 216    } else if (s.file == MRF && (s.nr & BRW_MRF_COMPR4)) {
 217       return regions_overlap(s, ds, r, dr);
 218
 219    } else {
 220       return reg_space(r) == reg_space(s) &&
 221              !(reg_offset(r) + dr <= reg_offset(s) ||
 222                reg_offset(s) + ds <= reg_offset(r));
 223    }
 224 }
 225
 226 /**
 227  * Return whether the given register region is n-periodic, i.e. whether the
 228  * original region remains invariant after shifting it by \p n scalar
 229  * channels.
 230  */
 231 static inline bool
 232 is_periodic(const fs_reg &reg, unsigned n)
 233 {
 234    if (reg.file == BAD_FILE || reg.is_null()) {
 235       return true;
 236
 237    } else if (reg.file == IMM) {
 238       const unsigned period = (reg.type == BRW_REGISTER_TYPE_UV ||
 239                                reg.type == BRW_REGISTER_TYPE_V ? 8 :
 240                                reg.type == BRW_REGISTER_TYPE_VF ? 4 :
 241                                1);
 242       return n % period == 0;
 243
 244    } else if (reg.file == ARF || reg.file == FIXED_GRF) {
 245       const unsigned period = (reg.hstride == 0 && reg.vstride == 0 ? 1 :
 246                                reg.vstride == 0 ? 1 << reg.width :
 247                                ~0);
 248       return n % period == 0;
 249
 250    } else {
 251       return reg.stride == 0;
 252    }
 253 }
 254
 255 static inline bool
 256 is_uniform(const fs_reg &reg)
 257 {
 258    return is_periodic(reg, 1);
 259 }
 260
 261 /**
 262  * Get the specified 8-component quarter of a register.
 263  * XXX - Maybe come up with a less misleading name for this (e.g. quarter())?
 264  */
 265 static inline fs_reg
 266 half(const fs_reg &reg, unsigned idx)
 267 {
 268    assert(idx < 2);
 269    return horiz_offset(reg, 8 * idx);
 270 }
 271
 272 /**
 273  * Reinterpret each channel of register \p reg as a vector of values of the
 274  * given smaller type and take the i-th subcomponent from each.
 275  */
 276 static inline fs_reg
 277 subscript(fs_reg reg, brw_reg_type type, unsigned i)
 278 {
 279    assert((i + 1) * type_sz(type) <= type_sz(reg.type));
 280
 281    if (reg.file == ARF || reg.file == FIXED_GRF) {
 282       /* The stride is encoded inconsistently for fixed GRF and ARF registers
 283        * as the log2 of the actual vertical and horizontal strides.
 284        */
 285       const int delta = _mesa_logbase2(type_sz(reg.type)) -
 286                         _mesa_logbase2(type_sz(type));
 287       reg.hstride += (reg.hstride ? delta : 0);
 288       reg.vstride += (reg.vstride ? delta : 0);
 289
 290    } else if (reg.file == IMM) {
 291       assert(reg.type == type);
 292
 293    } else {
 294       reg.stride *= type_sz(reg.type) / type_sz(type);
 295    }
 296
 297    return byte_offset(retype(reg, type), i * type_sz(type));
 298 }
 299
 300 static const fs_reg reg_undef;
 301
 302 class fs_inst : public backend_instruction {
 303    fs_inst &operator=(const fs_inst &);
 304
 305    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 306              const fs_reg *src, unsigned sources);
 307
 308 public:
 309    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 310
 311    fs_inst();
 312    fs_inst(enum opcode opcode, uint8_t exec_size);
 313    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst);
 314    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 315            const fs_reg &src0);
 316    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 317            const fs_reg &src0, const fs_reg &src1);
 318    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 319            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 320    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 321            const fs_reg src[], unsigned sources);
 322    fs_inst(const fs_inst &that);
 323    ~fs_inst();
 324
 325    void resize_sources(uint8_t num_sources);
 326
 327    bool equals(fs_inst *inst) const;
 328    bool overwrites_reg(const fs_reg &reg) const;
 329    bool is_send_from_grf() const;
 330    bool is_partial_write() const;
 331    bool is_copy_payload(const brw::simple_allocator &grf_alloc) const;
 332    unsigned components_read(unsigned i) const;
 333    int regs_read(int arg) const;
 334    bool can_do_source_mods(const struct brw_device_info *devinfo);
 335    bool can_change_types() const;
 336    bool has_side_effects() const;
 337    bool has_source_and_destination_hazard() const;
 338
 339    /**
 340     * Return the subset of flag registers read by the instruction as a bitset
 341     * with byte granularity.
 342     */
 343    unsigned flags_read(const brw_device_info *devinfo) const;
 344
 345    /**
 346     * Return the subset of flag registers updated by the instruction (either
 347     * partially or fully) as a bitset with byte granularity.
 348     */
 349    unsigned flags_written() const;
 350
 351    fs_reg dst;
 352    fs_reg *src;
 353
 354    uint8_t sources; /**< Number of fs_reg sources. */
 355
 356    /**
 357     * Execution size of the instruction.  This is used by the generator to
 358     * generate the correct binary for the given fs_inst.  Current valid
 359     * values are 1, 8, 16.
 360     */
 361    uint8_t exec_size;
 362
 363    /**
 364     * Channel group from the hardware execution and predication mask that
 365     * should be applied to the instruction.  The subset of channel enable
 366     * signals (calculated from the EU control flow and predication state)
 367     * given by [group, group + exec_size) will be used to mask GRF writes and
 368     * any other side effects of the instruction.
 369     */
 370    uint8_t group;
 371
 372    bool eot:1;
 373    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 374 };
 375
 376 /**
 377  * Make the execution of \p inst dependent on the evaluation of a possibly
 378  * inverted predicate.
 379  */
 380 static inline fs_inst *
 381 set_predicate_inv(enum brw_predicate pred, bool inverse,
 382                   fs_inst *inst)
 383 {
 384    inst->predicate = pred;
 385    inst->predicate_inverse = inverse;
 386    return inst;
 387 }
 388
 389 /**
 390  * Make the execution of \p inst dependent on the evaluation of a predicate.
 391  */
 392 static inline fs_inst *
 393 set_predicate(enum brw_predicate pred, fs_inst *inst)
 394 {
 395    return set_predicate_inv(pred, false, inst);
 396 }
 397
 398 /**
 399  * Write the result of evaluating the condition given by \p mod to a flag
 400  * register.
 401  */
 402 static inline fs_inst *
 403 set_condmod(enum brw_conditional_mod mod, fs_inst *inst)
 404 {
 405    inst->conditional_mod = mod;
 406    return inst;
 407 }
 408
 409 /**
 410  * Clamp the result of \p inst to the saturation range of its destination
 411  * datatype.
 412  */
 413 static inline fs_inst *
 414 set_saturate(bool saturate, fs_inst *inst)
 415 {
 416    inst->saturate = saturate;
 417    return inst;
 418 }
 419
 420 #endif