src/mesa/drivers/dri/i965/brw_ir_fs.h

   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright © 2010-2015 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef BRW_IR_FS_H
  26 #define BRW_IR_FS_H
  27
  28 #include "brw_shader.h"
  29
  30 class fs_inst;
  31
  32 class fs_reg : public backend_reg {
  33 public:
  34    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  35
  36    void init();
  37
  38    fs_reg();
  39    fs_reg(struct ::brw_reg reg);
  40    fs_reg(enum brw_reg_file file, int nr);
  41    fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
  42
  43    bool equals(const fs_reg &r) const;
  44    bool is_contiguous() const;
  45
  46    /**
  47     * Return the size in bytes of a single logical component of the
  48     * register assuming the given execution width.
  49     */
  50    unsigned component_size(unsigned width) const;
  51
  52    /** Smear a channel of the reg to all channels. */
  53    fs_reg &set_smear(unsigned subreg);
  54
  55    /**
  56     * Offset in bytes from the start of the register.  Values up to a
  57     * backend_reg::reg_offset unit are valid.
  58     */
  59    int subreg_offset;
  60
  61    /** Register region horizontal stride */
  62    uint8_t stride;
  63 };
  64
  65 static inline fs_reg
  66 negate(fs_reg reg)
  67 {
  68    assert(reg.file != IMM);
  69    reg.negate = !reg.negate;
  70    return reg;
  71 }
  72
  73 static inline fs_reg
  74 retype(fs_reg reg, enum brw_reg_type type)
  75 {
  76    reg.type = type;
  77    return reg;
  78 }
  79
  80 static inline fs_reg
  81 byte_offset(fs_reg reg, unsigned delta)
  82 {
  83    switch (reg.file) {
  84    case BAD_FILE:
  85       break;
  86    case VGRF:
  87    case ATTR:
  88    case UNIFORM: {
  89       const unsigned reg_size = (reg.file == UNIFORM ? 4 : REG_SIZE);
  90       const unsigned suboffset = reg.subreg_offset + delta;
  91       reg.reg_offset += suboffset / reg_size;
  92       reg.subreg_offset = suboffset % reg_size;
  93       break;
  94    }
  95    case MRF: {
  96       const unsigned suboffset = reg.subreg_offset + delta;
  97       reg.nr += suboffset / REG_SIZE;
  98       reg.subreg_offset = suboffset % REG_SIZE;
  99       break;
 100    }
 101    case ARF:
 102    case FIXED_GRF: {
 103       const unsigned suboffset = reg.subnr + delta;
 104       reg.nr += suboffset / REG_SIZE;
 105       reg.subnr = suboffset % REG_SIZE;
 106       break;
 107    }
 108    case IMM:
 109    default:
 110       assert(delta == 0);
 111    }
 112    return reg;
 113 }
 114
 115 static inline fs_reg
 116 horiz_offset(fs_reg reg, unsigned delta)
 117 {
 118    switch (reg.file) {
 119    case BAD_FILE:
 120    case UNIFORM:
 121    case IMM:
 122       /* These only have a single component that is implicitly splatted.  A
 123        * horizontal offset should be a harmless no-op.
 124        */
 125       break;
 126    case VGRF:
 127    case MRF:
 128    case ATTR:
 129       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 130    case ARF:
 131    case FIXED_GRF:
 132       assert(delta == 0);
 133    }
 134    return reg;
 135 }
 136
 137 /**
 138  * Get the scalar channel of \p reg given by \p idx and replicate it to all
 139  * channels of the result.
 140  */
 141 static inline fs_reg
 142 component(fs_reg reg, unsigned idx)
 143 {
 144    reg = horiz_offset(reg, idx);
 145    reg.stride = 0;
 146    return reg;
 147 }
 148
 149 /**
 150  * Return whether the given register region is n-periodic, i.e. whether the
 151  * original region remains invariant after shifting it by \p n scalar
 152  * channels.
 153  */
 154 static inline bool
 155 is_periodic(const fs_reg &reg, unsigned n)
 156 {
 157    if (reg.file == BAD_FILE || reg.is_null()) {
 158       return true;
 159
 160    } else if (reg.file == IMM) {
 161       const unsigned period = (reg.type == BRW_REGISTER_TYPE_UV ||
 162                                reg.type == BRW_REGISTER_TYPE_V ? 8 :
 163                                reg.type == BRW_REGISTER_TYPE_VF ? 4 :
 164                                1);
 165       return n % period == 0;
 166
 167    } else if (reg.file == ARF || reg.file == FIXED_GRF) {
 168       const unsigned period = (reg.hstride == 0 && reg.vstride == 0 ? 1 :
 169                                reg.vstride == 0 ? 1 << reg.width :
 170                                ~0);
 171       return n % period == 0;
 172
 173    } else {
 174       return reg.stride == 0;
 175    }
 176 }
 177
 178 static inline bool
 179 is_uniform(const fs_reg &reg)
 180 {
 181    return is_periodic(reg, 1);
 182 }
 183
 184 /**
 185  * Get either of the 8-component halves of a 16-component register.
 186  *
 187  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 188  */
 189 static inline fs_reg
 190 half(fs_reg reg, unsigned idx)
 191 {
 192    assert(idx < 2);
 193
 194    switch (reg.file) {
 195    case BAD_FILE:
 196    case UNIFORM:
 197    case IMM:
 198       return reg;
 199
 200    case VGRF:
 201    case MRF:
 202       return horiz_offset(reg, 8 * idx);
 203
 204    case ARF:
 205    case FIXED_GRF:
 206    case ATTR:
 207       unreachable("Cannot take half of this register type");
 208    }
 209    return reg;
 210 }
 211
 212 /**
 213  * Reinterpret each channel of register \p reg as a vector of values of the
 214  * given smaller type and take the i-th subcomponent from each.
 215  */
 216 static inline fs_reg
 217 subscript(fs_reg reg, brw_reg_type type, unsigned i)
 218 {
 219    assert((i + 1) * type_sz(type) <= type_sz(reg.type));
 220
 221    if (reg.file == ARF || reg.file == FIXED_GRF) {
 222       /* The stride is encoded inconsistently for fixed GRF and ARF registers
 223        * as the log2 of the actual vertical and horizontal strides.
 224        */
 225       const int delta = _mesa_logbase2(type_sz(reg.type)) -
 226                         _mesa_logbase2(type_sz(type));
 227       reg.hstride += (reg.hstride ? delta : 0);
 228       reg.vstride += (reg.vstride ? delta : 0);
 229
 230    } else if (reg.file == IMM) {
 231       assert(reg.type == type);
 232
 233    } else {
 234       reg.stride *= type_sz(reg.type) / type_sz(type);
 235    }
 236
 237    return byte_offset(retype(reg, type), i * type_sz(type));
 238 }
 239
 240 static const fs_reg reg_undef;
 241
 242 class fs_inst : public backend_instruction {
 243    fs_inst &operator=(const fs_inst &);
 244
 245    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 246              const fs_reg *src, unsigned sources);
 247
 248 public:
 249    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 250
 251    fs_inst();
 252    fs_inst(enum opcode opcode, uint8_t exec_size);
 253    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst);
 254    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 255            const fs_reg &src0);
 256    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 257            const fs_reg &src0, const fs_reg &src1);
 258    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 259            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 260    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 261            const fs_reg src[], unsigned sources);
 262    fs_inst(const fs_inst &that);
 263    ~fs_inst();
 264
 265    void resize_sources(uint8_t num_sources);
 266
 267    bool equals(fs_inst *inst) const;
 268    bool overwrites_reg(const fs_reg &reg) const;
 269    bool is_send_from_grf() const;
 270    bool is_partial_write() const;
 271    bool is_copy_payload(const brw::simple_allocator &grf_alloc) const;
 272    unsigned components_read(unsigned i) const;
 273    int regs_read(int arg) const;
 274    bool can_do_source_mods(const struct brw_device_info *devinfo);
 275    bool can_change_types() const;
 276    bool has_side_effects() const;
 277    bool has_source_and_destination_hazard() const;
 278
 279    /**
 280     * Return the subset of flag registers read by the instruction as a bitset
 281     * with byte granularity.
 282     */
 283    unsigned flags_read(const brw_device_info *devinfo) const;
 284
 285    /**
 286     * Return the subset of flag registers updated by the instruction (either
 287     * partially or fully) as a bitset with byte granularity.
 288     */
 289    unsigned flags_written() const;
 290
 291    fs_reg dst;
 292    fs_reg *src;
 293
 294    uint8_t sources; /**< Number of fs_reg sources. */
 295
 296    /**
 297     * Execution size of the instruction.  This is used by the generator to
 298     * generate the correct binary for the given fs_inst.  Current valid
 299     * values are 1, 8, 16.
 300     */
 301    uint8_t exec_size;
 302
 303    /**
 304     * Channel group from the hardware execution and predication mask that
 305     * should be applied to the instruction.  The subset of channel enable
 306     * signals (calculated from the EU control flow and predication state)
 307     * given by [group, group + exec_size) will be used to mask GRF writes and
 308     * any other side effects of the instruction.
 309     */
 310    uint8_t group;
 311
 312    bool eot:1;
 313    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 314 };
 315
 316 /**
 317  * Make the execution of \p inst dependent on the evaluation of a possibly
 318  * inverted predicate.
 319  */
 320 static inline fs_inst *
 321 set_predicate_inv(enum brw_predicate pred, bool inverse,
 322                   fs_inst *inst)
 323 {
 324    inst->predicate = pred;
 325    inst->predicate_inverse = inverse;
 326    return inst;
 327 }
 328
 329 /**
 330  * Make the execution of \p inst dependent on the evaluation of a predicate.
 331  */
 332 static inline fs_inst *
 333 set_predicate(enum brw_predicate pred, fs_inst *inst)
 334 {
 335    return set_predicate_inv(pred, false, inst);
 336 }
 337
 338 /**
 339  * Write the result of evaluating the condition given by \p mod to a flag
 340  * register.
 341  */
 342 static inline fs_inst *
 343 set_condmod(enum brw_conditional_mod mod, fs_inst *inst)
 344 {
 345    inst->conditional_mod = mod;
 346    return inst;
 347 }
 348
 349 /**
 350  * Clamp the result of \p inst to the saturation range of its destination
 351  * datatype.
 352  */
 353 static inline fs_inst *
 354 set_saturate(bool saturate, fs_inst *inst)
 355 {
 356    inst->saturate = saturate;
 357    return inst;
 358 }
 359
 360 #endif