src/mesa/drivers/dri/i965/brw_ir_fs.h

   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright © 2010-2015 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef BRW_IR_FS_H
  26 #define BRW_IR_FS_H
  27
  28 #include "brw_shader.h"
  29
  30 class fs_inst;
  31
  32 class fs_reg : public backend_reg {
  33 public:
  34    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  35
  36    void init();
  37
  38    fs_reg();
  39    fs_reg(struct ::brw_reg reg);
  40    fs_reg(enum brw_reg_file file, int nr);
  41    fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
  42
  43    bool equals(const fs_reg &r) const;
  44    bool is_contiguous() const;
  45
  46    /**
  47     * Return the size in bytes of a single logical component of the
  48     * register assuming the given execution width.
  49     */
  50    unsigned component_size(unsigned width) const;
  51
  52    /** Smear a channel of the reg to all channels. */
  53    fs_reg &set_smear(unsigned subreg);
  54
  55    /**
  56     * Offset in bytes from the start of the register.  Values up to a
  57     * backend_reg::reg_offset unit are valid.
  58     */
  59    int subreg_offset;
  60
  61    fs_reg *reladdr;
  62
  63    /** Register region horizontal stride */
  64    uint8_t stride;
  65 };
  66
  67 static inline fs_reg
  68 negate(fs_reg reg)
  69 {
  70    assert(reg.file != IMM);
  71    reg.negate = !reg.negate;
  72    return reg;
  73 }
  74
  75 static inline fs_reg
  76 retype(fs_reg reg, enum brw_reg_type type)
  77 {
  78    reg.type = type;
  79    return reg;
  80 }
  81
  82 static inline fs_reg
  83 byte_offset(fs_reg reg, unsigned delta)
  84 {
  85    switch (reg.file) {
  86    case BAD_FILE:
  87       break;
  88    case VGRF:
  89    case ATTR:
  90       reg.reg_offset += delta / 32;
  91       break;
  92    case MRF:
  93       reg.nr += delta / 32;
  94       break;
  95    case ARF:
  96    case FIXED_GRF:
  97    case IMM:
  98    case UNIFORM:
  99       assert(delta == 0);
 100    }
 101    reg.subreg_offset += delta % 32;
 102    return reg;
 103 }
 104
 105 static inline fs_reg
 106 horiz_offset(fs_reg reg, unsigned delta)
 107 {
 108    switch (reg.file) {
 109    case BAD_FILE:
 110    case UNIFORM:
 111    case IMM:
 112       /* These only have a single component that is implicitly splatted.  A
 113        * horizontal offset should be a harmless no-op.
 114        */
 115       break;
 116    case VGRF:
 117    case MRF:
 118    case ATTR:
 119       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 120    case ARF:
 121    case FIXED_GRF:
 122       assert(delta == 0);
 123    }
 124    return reg;
 125 }
 126
 127 static inline fs_reg
 128 component(fs_reg reg, unsigned idx)
 129 {
 130    assert(reg.subreg_offset == 0);
 131    reg.subreg_offset = idx * type_sz(reg.type);
 132    reg.stride = 0;
 133    return reg;
 134 }
 135
 136 static inline bool
 137 is_uniform(const fs_reg &reg)
 138 {
 139    return (reg.stride == 0 || reg.is_null()) &&
 140           (!reg.reladdr || is_uniform(*reg.reladdr));
 141 }
 142
 143 /**
 144  * Get either of the 8-component halves of a 16-component register.
 145  *
 146  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 147  */
 148 static inline fs_reg
 149 half(fs_reg reg, unsigned idx)
 150 {
 151    assert(idx < 2);
 152
 153    switch (reg.file) {
 154    case BAD_FILE:
 155    case UNIFORM:
 156    case IMM:
 157       return reg;
 158
 159    case VGRF:
 160    case MRF:
 161       return horiz_offset(reg, 8 * idx);
 162
 163    case ARF:
 164    case FIXED_GRF:
 165    case ATTR:
 166       unreachable("Cannot take half of this register type");
 167    }
 168    return reg;
 169 }
 170
 171 static const fs_reg reg_undef;
 172
 173 class fs_inst : public backend_instruction {
 174    fs_inst &operator=(const fs_inst &);
 175
 176    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 177              const fs_reg *src, unsigned sources);
 178
 179 public:
 180    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 181
 182    fs_inst();
 183    fs_inst(enum opcode opcode, uint8_t exec_size);
 184    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst);
 185    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 186            const fs_reg &src0);
 187    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 188            const fs_reg &src0, const fs_reg &src1);
 189    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 190            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 191    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 192            const fs_reg src[], unsigned sources);
 193    fs_inst(const fs_inst &that);
 194    ~fs_inst();
 195
 196    void resize_sources(uint8_t num_sources);
 197
 198    bool equals(fs_inst *inst) const;
 199    bool overwrites_reg(const fs_reg &reg) const;
 200    bool is_send_from_grf() const;
 201    bool is_partial_write() const;
 202    bool is_copy_payload(const brw::simple_allocator &grf_alloc) const;
 203    unsigned components_read(unsigned i) const;
 204    int regs_read(int arg) const;
 205    bool can_do_source_mods(const struct brw_device_info *devinfo);
 206    bool can_change_types() const;
 207    bool has_side_effects() const;
 208    bool has_source_and_destination_hazard() const;
 209
 210    bool reads_flag() const;
 211    bool writes_flag() const;
 212
 213    fs_reg dst;
 214    fs_reg *src;
 215
 216    uint8_t sources; /**< Number of fs_reg sources. */
 217
 218    /**
 219     * Execution size of the instruction.  This is used by the generator to
 220     * generate the correct binary for the given fs_inst.  Current valid
 221     * values are 1, 8, 16.
 222     */
 223    uint8_t exec_size;
 224
 225    bool eot:1;
 226    bool force_sechalf:1;
 227    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 228 };
 229
 230 /**
 231  * Set second-half quarter control on \p inst.
 232  */
 233 static inline fs_inst *
 234 set_sechalf(fs_inst *inst)
 235 {
 236    inst->force_sechalf = true;
 237    return inst;
 238 }
 239
 240 /**
 241  * Make the execution of \p inst dependent on the evaluation of a possibly
 242  * inverted predicate.
 243  */
 244 static inline fs_inst *
 245 set_predicate_inv(enum brw_predicate pred, bool inverse,
 246                   fs_inst *inst)
 247 {
 248    inst->predicate = pred;
 249    inst->predicate_inverse = inverse;
 250    return inst;
 251 }
 252
 253 /**
 254  * Make the execution of \p inst dependent on the evaluation of a predicate.
 255  */
 256 static inline fs_inst *
 257 set_predicate(enum brw_predicate pred, fs_inst *inst)
 258 {
 259    return set_predicate_inv(pred, false, inst);
 260 }
 261
 262 /**
 263  * Write the result of evaluating the condition given by \p mod to a flag
 264  * register.
 265  */
 266 static inline fs_inst *
 267 set_condmod(enum brw_conditional_mod mod, fs_inst *inst)
 268 {
 269    inst->conditional_mod = mod;
 270    return inst;
 271 }
 272
 273 /**
 274  * Clamp the result of \p inst to the saturation range of its destination
 275  * datatype.
 276  */
 277 static inline fs_inst *
 278 set_saturate(bool saturate, fs_inst *inst)
 279 {
 280    inst->saturate = saturate;
 281    return inst;
 282 }
 283
 284 #endif