src/mesa/drivers/dri/i965/brw_ir_fs.h

   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright © 2010-2015 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef BRW_IR_FS_H
  26 #define BRW_IR_FS_H
  27
  28 #include "brw_shader.h"
  29
  30 class fs_inst;
  31
  32 class fs_reg : public backend_reg {
  33 public:
  34    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  35
  36    void init();
  37
  38    fs_reg();
  39    explicit fs_reg(float f);
  40    explicit fs_reg(int32_t i);
  41    explicit fs_reg(uint32_t u);
  42    explicit fs_reg(uint8_t vf[4]);
  43    explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
  44    fs_reg(struct brw_reg fixed_hw_reg);
  45    fs_reg(enum register_file file, int reg);
  46    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  47    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  48
  49    bool equals(const fs_reg &r) const;
  50    bool is_contiguous() const;
  51
  52    /** Smear a channel of the reg to all channels. */
  53    fs_reg &set_smear(unsigned subreg);
  54
  55    /**
  56     * Offset in bytes from the start of the register.  Values up to a
  57     * backend_reg::reg_offset unit are valid.
  58     */
  59    int subreg_offset;
  60
  61    fs_reg *reladdr;
  62
  63    /**
  64     * The register width.  This indicates how many hardware values are
  65     * represented by each virtual value.  Valid values are 1, 8, or 16.
  66     * For immediate values, this is 1.  Most of the rest of the time, it
  67     * will be equal to the dispatch width.
  68     */
  69    uint8_t width;
  70
  71    /** Register region horizontal stride */
  72    uint8_t stride;
  73 };
  74
  75 static inline fs_reg
  76 negate(fs_reg reg)
  77 {
  78    assert(reg.file != HW_REG && reg.file != IMM);
  79    reg.negate = !reg.negate;
  80    return reg;
  81 }
  82
  83 static inline fs_reg
  84 retype(fs_reg reg, enum brw_reg_type type)
  85 {
  86    reg.fixed_hw_reg.type = reg.type = type;
  87    return reg;
  88 }
  89
  90 static inline fs_reg
  91 byte_offset(fs_reg reg, unsigned delta)
  92 {
  93    switch (reg.file) {
  94    case BAD_FILE:
  95       break;
  96    case GRF:
  97    case ATTR:
  98       reg.reg_offset += delta / 32;
  99       break;
 100    case MRF:
 101       reg.reg += delta / 32;
 102       break;
 103    default:
 104       assert(delta == 0);
 105    }
 106    reg.subreg_offset += delta % 32;
 107    return reg;
 108 }
 109
 110 static inline fs_reg
 111 horiz_offset(fs_reg reg, unsigned delta)
 112 {
 113    switch (reg.file) {
 114    case BAD_FILE:
 115    case UNIFORM:
 116    case IMM:
 117       /* These only have a single component that is implicitly splatted.  A
 118        * horizontal offset should be a harmless no-op.
 119        */
 120       break;
 121    case GRF:
 122    case MRF:
 123    case ATTR:
 124       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 125    default:
 126       assert(delta == 0);
 127    }
 128    return reg;
 129 }
 130
 131 static inline fs_reg
 132 component(fs_reg reg, unsigned idx)
 133 {
 134    assert(reg.subreg_offset == 0);
 135    assert(idx < reg.width);
 136    reg.subreg_offset = idx * type_sz(reg.type);
 137    reg.width = 1;
 138    reg.stride = 0;
 139    return reg;
 140 }
 141
 142 static inline bool
 143 is_uniform(const fs_reg &reg)
 144 {
 145    return (reg.width == 1 || reg.stride == 0 || reg.is_null()) &&
 146           (!reg.reladdr || is_uniform(*reg.reladdr));
 147 }
 148
 149 /**
 150  * Get either of the 8-component halves of a 16-component register.
 151  *
 152  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 153  */
 154 static inline fs_reg
 155 half(fs_reg reg, unsigned idx)
 156 {
 157    assert(idx < 2);
 158
 159    switch (reg.file) {
 160    case BAD_FILE:
 161    case UNIFORM:
 162    case IMM:
 163       return reg;
 164
 165    case GRF:
 166    case MRF:
 167       assert(reg.width == 16);
 168       reg.width = 8;
 169       return horiz_offset(reg, 8 * idx);
 170
 171    case ATTR:
 172    case HW_REG:
 173    default:
 174       unreachable("Cannot take half of this register type");
 175    }
 176    return reg;
 177 }
 178
 179 static const fs_reg reg_undef;
 180
 181 class fs_inst : public backend_instruction {
 182    fs_inst &operator=(const fs_inst &);
 183
 184    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 185              const fs_reg *src, unsigned sources);
 186
 187 public:
 188    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 189
 190    fs_inst();
 191    fs_inst(enum opcode opcode, uint8_t exec_size);
 192    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst);
 193    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 194            const fs_reg &src0);
 195    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 196            const fs_reg &src0, const fs_reg &src1);
 197    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 198            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 199    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 200            const fs_reg src[], unsigned sources);
 201    fs_inst(const fs_inst &that);
 202    ~fs_inst();
 203
 204    void resize_sources(uint8_t num_sources);
 205
 206    bool equals(fs_inst *inst) const;
 207    bool overwrites_reg(const fs_reg &reg) const;
 208    bool is_send_from_grf() const;
 209    bool is_partial_write() const;
 210    bool is_copy_payload(const brw::simple_allocator &grf_alloc) const;
 211    int regs_read(int arg) const;
 212    bool can_do_source_mods(const struct brw_device_info *devinfo);
 213    bool has_side_effects() const;
 214
 215    bool reads_flag() const;
 216    bool writes_flag() const;
 217
 218    fs_reg dst;
 219    fs_reg *src;
 220
 221    uint8_t sources; /**< Number of fs_reg sources. */
 222
 223    /**
 224     * Execution size of the instruction.  This is used by the generator to
 225     * generate the correct binary for the given fs_inst.  Current valid
 226     * values are 1, 8, 16.
 227     */
 228    uint8_t exec_size;
 229
 230    bool eot:1;
 231    bool force_sechalf:1;
 232    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 233 };
 234
 235 /**
 236  * Set second-half quarter control on \p inst.
 237  */
 238 static inline fs_inst *
 239 set_sechalf(fs_inst *inst)
 240 {
 241    inst->force_sechalf = true;
 242    return inst;
 243 }
 244
 245 /**
 246  * Make the execution of \p inst dependent on the evaluation of a possibly
 247  * inverted predicate.
 248  */
 249 static inline fs_inst *
 250 set_predicate_inv(enum brw_predicate pred, bool inverse,
 251                   fs_inst *inst)
 252 {
 253    inst->predicate = pred;
 254    inst->predicate_inverse = inverse;
 255    return inst;
 256 }
 257
 258 /**
 259  * Make the execution of \p inst dependent on the evaluation of a predicate.
 260  */
 261 static inline fs_inst *
 262 set_predicate(enum brw_predicate pred, fs_inst *inst)
 263 {
 264    return set_predicate_inv(pred, false, inst);
 265 }
 266
 267 /**
 268  * Write the result of evaluating the condition given by \p mod to a flag
 269  * register.
 270  */
 271 static inline fs_inst *
 272 set_condmod(enum brw_conditional_mod mod, fs_inst *inst)
 273 {
 274    inst->conditional_mod = mod;
 275    return inst;
 276 }
 277
 278 /**
 279  * Clamp the result of \p inst to the saturation range of its destination
 280  * datatype.
 281  */
 282 static inline fs_inst *
 283 set_saturate(bool saturate, fs_inst *inst)
 284 {
 285    inst->saturate = saturate;
 286    return inst;
 287 }
 288
 289 #endif