src/mesa/drivers/dri/i965/brw_ir_fs.h

   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright © 2010-2015 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef BRW_IR_FS_H
  26 #define BRW_IR_FS_H
  27
  28 #include "brw_shader.h"
  29
  30 class fs_inst;
  31
  32 class fs_reg : public backend_reg {
  33 public:
  34    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  35
  36    void init();
  37
  38    fs_reg();
  39    fs_reg(struct ::brw_reg reg);
  40    fs_reg(enum brw_reg_file file, int nr);
  41    fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
  42
  43    bool equals(const fs_reg &r) const;
  44    bool is_contiguous() const;
  45
  46    /**
  47     * Return the size in bytes of a single logical component of the
  48     * register assuming the given execution width.
  49     */
  50    unsigned component_size(unsigned width) const;
  51
  52    /** Smear a channel of the reg to all channels. */
  53    fs_reg &set_smear(unsigned subreg);
  54
  55    /** Register region horizontal stride */
  56    uint8_t stride;
  57 };
  58
  59 static inline fs_reg
  60 negate(fs_reg reg)
  61 {
  62    assert(reg.file != IMM);
  63    reg.negate = !reg.negate;
  64    return reg;
  65 }
  66
  67 static inline fs_reg
  68 retype(fs_reg reg, enum brw_reg_type type)
  69 {
  70    reg.type = type;
  71    return reg;
  72 }
  73
  74 static inline fs_reg
  75 byte_offset(fs_reg reg, unsigned delta)
  76 {
  77    switch (reg.file) {
  78    case BAD_FILE:
  79       break;
  80    case VGRF:
  81    case ATTR:
  82    case UNIFORM: {
  83       const unsigned reg_size = (reg.file == UNIFORM ? 4 : REG_SIZE);
  84       const unsigned suboffset = reg.offset % reg_size + delta;
  85       reg.offset += ROUND_DOWN_TO(suboffset, reg_size);
  86       reg.offset = ROUND_DOWN_TO(reg.offset, reg_size) + suboffset % reg_size;
  87       break;
  88    }
  89    case MRF: {
  90       const unsigned suboffset = reg.offset % REG_SIZE + delta;
  91       reg.nr += suboffset / REG_SIZE;
  92       reg.offset = ROUND_DOWN_TO(reg.offset, REG_SIZE) + suboffset % REG_SIZE;
  93       break;
  94    }
  95    case ARF:
  96    case FIXED_GRF: {
  97       const unsigned suboffset = reg.subnr + delta;
  98       reg.nr += suboffset / REG_SIZE;
  99       reg.subnr = suboffset % REG_SIZE;
 100       break;
 101    }
 102    case IMM:
 103    default:
 104       assert(delta == 0);
 105    }
 106    return reg;
 107 }
 108
 109 static inline fs_reg
 110 horiz_offset(const fs_reg &reg, unsigned delta)
 111 {
 112    switch (reg.file) {
 113    case BAD_FILE:
 114    case UNIFORM:
 115    case IMM:
 116       /* These only have a single component that is implicitly splatted.  A
 117        * horizontal offset should be a harmless no-op.
 118        * XXX - Handle vector immediates correctly.
 119        */
 120       return reg;
 121    case VGRF:
 122    case MRF:
 123    case ATTR:
 124       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 125    case ARF:
 126    case FIXED_GRF:
 127       if (reg.is_null()) {
 128          return reg;
 129       } else {
 130          const unsigned stride = reg.hstride ? 1 << (reg.hstride - 1) : 0;
 131          return byte_offset(reg, delta * stride * type_sz(reg.type));
 132       }
 133    }
 134    unreachable("Invalid register file");
 135 }
 136
 137 static inline fs_reg
 138 offset(fs_reg reg, unsigned width, unsigned delta)
 139 {
 140    switch (reg.file) {
 141    case BAD_FILE:
 142       break;
 143    case ARF:
 144    case FIXED_GRF:
 145    case MRF:
 146    case VGRF:
 147    case ATTR:
 148    case UNIFORM:
 149       return byte_offset(reg, delta * reg.component_size(width));
 150    case IMM:
 151       assert(delta == 0);
 152    }
 153    return reg;
 154 }
 155
 156 /**
 157  * Get the scalar channel of \p reg given by \p idx and replicate it to all
 158  * channels of the result.
 159  */
 160 static inline fs_reg
 161 component(fs_reg reg, unsigned idx)
 162 {
 163    reg = horiz_offset(reg, idx);
 164    reg.stride = 0;
 165    return reg;
 166 }
 167
 168 /**
 169  * Return an integer identifying the discrete address space a register is
 170  * contained in.  A register is by definition fully contained in the single
 171  * reg_space it belongs to, so two registers with different reg_space ids are
 172  * guaranteed not to overlap.  Most register files are a single reg_space of
 173  * its own, only the VGRF file is composed of multiple discrete address
 174  * spaces, one for each VGRF allocation.
 175  */
 176 static inline uint32_t
 177 reg_space(const fs_reg &r)
 178 {
 179    return r.file << 16 | (r.file == VGRF ? r.nr : 0);
 180 }
 181
 182 /**
 183  * Return the base offset in bytes of a register relative to the start of its
 184  * reg_space().
 185  */
 186 static inline unsigned
 187 reg_offset(const fs_reg &r)
 188 {
 189    return (r.file == VGRF || r.file == IMM ? 0 : r.nr) *
 190           (r.file == UNIFORM ? 4 : REG_SIZE) + r.offset;
 191 }
 192
 193 /**
 194  * Return whether the register region starting at \p r and spanning \p dr
 195  * bytes could potentially overlap the register region starting at \p s and
 196  * spanning \p ds bytes.
 197  */
 198 static inline bool
 199 regions_overlap(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
 200 {
 201    if (r.file == MRF && (r.nr & BRW_MRF_COMPR4)) {
 202       fs_reg t = r;
 203       t.nr &= ~BRW_MRF_COMPR4;
 204       /* COMPR4 regions are translated by the hardware during decompression
 205        * into two separate half-regions 4 MRFs apart from each other.
 206        */
 207       return regions_overlap(t, dr / 2, s, ds) ||
 208              regions_overlap(byte_offset(t, 4 * REG_SIZE), dr / 2, s, ds);
 209
 210    } else if (s.file == MRF && (s.nr & BRW_MRF_COMPR4)) {
 211       return regions_overlap(s, ds, r, dr);
 212
 213    } else {
 214       return reg_space(r) == reg_space(s) &&
 215              !(reg_offset(r) + dr <= reg_offset(s) ||
 216                reg_offset(s) + ds <= reg_offset(r));
 217    }
 218 }
 219
 220 /**
 221  * Return whether the given register region is n-periodic, i.e. whether the
 222  * original region remains invariant after shifting it by \p n scalar
 223  * channels.
 224  */
 225 static inline bool
 226 is_periodic(const fs_reg &reg, unsigned n)
 227 {
 228    if (reg.file == BAD_FILE || reg.is_null()) {
 229       return true;
 230
 231    } else if (reg.file == IMM) {
 232       const unsigned period = (reg.type == BRW_REGISTER_TYPE_UV ||
 233                                reg.type == BRW_REGISTER_TYPE_V ? 8 :
 234                                reg.type == BRW_REGISTER_TYPE_VF ? 4 :
 235                                1);
 236       return n % period == 0;
 237
 238    } else if (reg.file == ARF || reg.file == FIXED_GRF) {
 239       const unsigned period = (reg.hstride == 0 && reg.vstride == 0 ? 1 :
 240                                reg.vstride == 0 ? 1 << reg.width :
 241                                ~0);
 242       return n % period == 0;
 243
 244    } else {
 245       return reg.stride == 0;
 246    }
 247 }
 248
 249 static inline bool
 250 is_uniform(const fs_reg &reg)
 251 {
 252    return is_periodic(reg, 1);
 253 }
 254
 255 /**
 256  * Get the specified 8-component quarter of a register.
 257  * XXX - Maybe come up with a less misleading name for this (e.g. quarter())?
 258  */
 259 static inline fs_reg
 260 half(const fs_reg &reg, unsigned idx)
 261 {
 262    assert(idx < 2);
 263    return horiz_offset(reg, 8 * idx);
 264 }
 265
 266 /**
 267  * Reinterpret each channel of register \p reg as a vector of values of the
 268  * given smaller type and take the i-th subcomponent from each.
 269  */
 270 static inline fs_reg
 271 subscript(fs_reg reg, brw_reg_type type, unsigned i)
 272 {
 273    assert((i + 1) * type_sz(type) <= type_sz(reg.type));
 274
 275    if (reg.file == ARF || reg.file == FIXED_GRF) {
 276       /* The stride is encoded inconsistently for fixed GRF and ARF registers
 277        * as the log2 of the actual vertical and horizontal strides.
 278        */
 279       const int delta = _mesa_logbase2(type_sz(reg.type)) -
 280                         _mesa_logbase2(type_sz(type));
 281       reg.hstride += (reg.hstride ? delta : 0);
 282       reg.vstride += (reg.vstride ? delta : 0);
 283
 284    } else if (reg.file == IMM) {
 285       assert(reg.type == type);
 286
 287    } else {
 288       reg.stride *= type_sz(reg.type) / type_sz(type);
 289    }
 290
 291    return byte_offset(retype(reg, type), i * type_sz(type));
 292 }
 293
 294 static const fs_reg reg_undef;
 295
 296 class fs_inst : public backend_instruction {
 297    fs_inst &operator=(const fs_inst &);
 298
 299    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 300              const fs_reg *src, unsigned sources);
 301
 302 public:
 303    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 304
 305    fs_inst();
 306    fs_inst(enum opcode opcode, uint8_t exec_size);
 307    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst);
 308    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 309            const fs_reg &src0);
 310    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 311            const fs_reg &src0, const fs_reg &src1);
 312    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 313            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 314    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 315            const fs_reg src[], unsigned sources);
 316    fs_inst(const fs_inst &that);
 317    ~fs_inst();
 318
 319    void resize_sources(uint8_t num_sources);
 320
 321    bool equals(fs_inst *inst) const;
 322    bool overwrites_reg(const fs_reg &reg) const;
 323    bool is_send_from_grf() const;
 324    bool is_partial_write() const;
 325    bool is_copy_payload(const brw::simple_allocator &grf_alloc) const;
 326    unsigned components_read(unsigned i) const;
 327    int size_read(int arg) const;
 328    bool can_do_source_mods(const struct gen_device_info *devinfo);
 329    bool can_change_types() const;
 330    bool has_side_effects() const;
 331    bool has_source_and_destination_hazard() const;
 332
 333    /**
 334     * Return the subset of flag registers read by the instruction as a bitset
 335     * with byte granularity.
 336     */
 337    unsigned flags_read(const gen_device_info *devinfo) const;
 338
 339    /**
 340     * Return the subset of flag registers updated by the instruction (either
 341     * partially or fully) as a bitset with byte granularity.
 342     */
 343    unsigned flags_written() const;
 344
 345    fs_reg dst;
 346    fs_reg *src;
 347
 348    uint8_t sources; /**< Number of fs_reg sources. */
 349
 350    /**
 351     * Execution size of the instruction.  This is used by the generator to
 352     * generate the correct binary for the given fs_inst.  Current valid
 353     * values are 1, 8, 16.
 354     */
 355    uint8_t exec_size;
 356
 357    /**
 358     * Channel group from the hardware execution and predication mask that
 359     * should be applied to the instruction.  The subset of channel enable
 360     * signals (calculated from the EU control flow and predication state)
 361     * given by [group, group + exec_size) will be used to mask GRF writes and
 362     * any other side effects of the instruction.
 363     */
 364    uint8_t group;
 365
 366    bool eot:1;
 367    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 368 };
 369
 370 /**
 371  * Make the execution of \p inst dependent on the evaluation of a possibly
 372  * inverted predicate.
 373  */
 374 static inline fs_inst *
 375 set_predicate_inv(enum brw_predicate pred, bool inverse,
 376                   fs_inst *inst)
 377 {
 378    inst->predicate = pred;
 379    inst->predicate_inverse = inverse;
 380    return inst;
 381 }
 382
 383 /**
 384  * Make the execution of \p inst dependent on the evaluation of a predicate.
 385  */
 386 static inline fs_inst *
 387 set_predicate(enum brw_predicate pred, fs_inst *inst)
 388 {
 389    return set_predicate_inv(pred, false, inst);
 390 }
 391
 392 /**
 393  * Write the result of evaluating the condition given by \p mod to a flag
 394  * register.
 395  */
 396 static inline fs_inst *
 397 set_condmod(enum brw_conditional_mod mod, fs_inst *inst)
 398 {
 399    inst->conditional_mod = mod;
 400    return inst;
 401 }
 402
 403 /**
 404  * Clamp the result of \p inst to the saturation range of its destination
 405  * datatype.
 406  */
 407 static inline fs_inst *
 408 set_saturate(bool saturate, fs_inst *inst)
 409 {
 410    inst->saturate = saturate;
 411    return inst;
 412 }
 413
 414 /**
 415  * Return the number of dataflow registers written by the instruction (either
 416  * fully or partially) counted from 'floor(reg_offset(inst->dst) /
 417  * register_size)'.  The somewhat arbitrary register size unit is 4B for the
 418  * UNIFORM and IMM files and 32B for all other files.
 419  */
 420 inline unsigned
 421 regs_written(const fs_inst *inst)
 422 {
 423    /* XXX - Take into account register-misaligned offsets correctly. */
 424    assert(inst->dst.file != UNIFORM && inst->dst.file != IMM);
 425    return DIV_ROUND_UP(inst->size_written, REG_SIZE);
 426 }
 427
 428 /**
 429  * Return the number of dataflow registers read by the instruction (either
 430  * fully or partially) counted from 'floor(reg_offset(inst->src[i]) /
 431  * register_size)'.  The somewhat arbitrary register size unit is 4B for the
 432  * UNIFORM and IMM files and 32B for all other files.
 433  */
 434 inline unsigned
 435 regs_read(const fs_inst *inst, unsigned i)
 436 {
 437    /* XXX - Take into account register-misaligned offsets correctly. */
 438    const unsigned reg_size =
 439       inst->src[i].file == UNIFORM || inst->src[i].file == IMM ? 4 : REG_SIZE;
 440    return DIV_ROUND_UP(inst->size_read(i), reg_size);
 441 }
 442
 443 #endif