src/mesa/drivers/dri/i965/brw_ir_vec4.h

   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright © 2011-2015 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef BRW_IR_VEC4_H
  26 #define BRW_IR_VEC4_H
  27
  28 #include "brw_shader.h"
  29 #include "brw_context.h"
  30
  31 namespace brw {
  32
  33 class dst_reg;
  34
  35 class src_reg : public backend_reg
  36 {
  37 public:
  38    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
  39
  40    void init();
  41
  42    src_reg(enum brw_reg_file file, int nr, const glsl_type *type);
  43    src_reg();
  44    src_reg(struct ::brw_reg reg);
  45
  46    bool equals(const src_reg &r) const;
  47
  48    src_reg(class vec4_visitor *v, const struct glsl_type *type);
  49    src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
  50
  51    explicit src_reg(const dst_reg &reg);
  52
  53    src_reg *reladdr;
  54 };
  55
  56 static inline src_reg
  57 retype(src_reg reg, enum brw_reg_type type)
  58 {
  59    reg.type = type;
  60    return reg;
  61 }
  62
  63 static inline src_reg
  64 offset(src_reg reg, unsigned delta)
  65 {
  66    assert(delta == 0 ||
  67           (reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM));
  68    reg.reg_offset += delta;
  69    return reg;
  70 }
  71
  72 /**
  73  * Reswizzle a given source register.
  74  * \sa brw_swizzle().
  75  */
  76 static inline src_reg
  77 swizzle(src_reg reg, unsigned swizzle)
  78 {
  79    reg.swizzle = brw_compose_swizzle(swizzle, reg.swizzle);
  80    return reg;
  81 }
  82
  83 static inline src_reg
  84 negate(src_reg reg)
  85 {
  86    assert(reg.file != IMM);
  87    reg.negate = !reg.negate;
  88    return reg;
  89 }
  90
  91 static inline bool
  92 is_uniform(const src_reg &reg)
  93 {
  94    return (reg.file == IMM || reg.file == UNIFORM || reg.is_null()) &&
  95           (!reg.reladdr || is_uniform(*reg.reladdr));
  96 }
  97
  98 class dst_reg : public backend_reg
  99 {
 100 public:
 101    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 102
 103    void init();
 104
 105    dst_reg();
 106    dst_reg(enum brw_reg_file file, int nr);
 107    dst_reg(enum brw_reg_file file, int nr, const glsl_type *type,
 108            unsigned writemask);
 109    dst_reg(enum brw_reg_file file, int nr, brw_reg_type type,
 110            unsigned writemask);
 111    dst_reg(struct ::brw_reg reg);
 112    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 113
 114    explicit dst_reg(const src_reg &reg);
 115
 116    bool equals(const dst_reg &r) const;
 117
 118    src_reg *reladdr;
 119 };
 120
 121 static inline dst_reg
 122 retype(dst_reg reg, enum brw_reg_type type)
 123 {
 124    reg.type = type;
 125    return reg;
 126 }
 127
 128 static inline dst_reg
 129 offset(dst_reg reg, unsigned delta)
 130 {
 131    assert(delta == 0 ||
 132           (reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM));
 133    reg.reg_offset += delta;
 134    return reg;
 135 }
 136
 137 static inline dst_reg
 138 writemask(dst_reg reg, unsigned mask)
 139 {
 140    assert(reg.file != IMM);
 141    assert((reg.writemask & mask) != 0);
 142    reg.writemask &= mask;
 143    return reg;
 144 }
 145
 146 class vec4_instruction : public backend_instruction {
 147 public:
 148    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 149
 150    vec4_instruction(enum opcode opcode,
 151                     const dst_reg &dst = dst_reg(),
 152                     const src_reg &src0 = src_reg(),
 153                     const src_reg &src1 = src_reg(),
 154                     const src_reg &src2 = src_reg());
 155
 156    dst_reg dst;
 157    src_reg src[3];
 158
 159    enum brw_urb_write_flags urb_write_flags;
 160
 161    unsigned sol_binding; /**< gen6: SOL binding table index */
 162    bool sol_final_write; /**< gen6: send commit message */
 163    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 164
 165    bool is_send_from_grf();
 166    unsigned regs_read(unsigned arg) const;
 167    bool can_reswizzle(const struct brw_device_info *devinfo, int dst_writemask,
 168                       int swizzle, int swizzle_mask);
 169    void reswizzle(int dst_writemask, int swizzle);
 170    bool can_do_source_mods(const struct brw_device_info *devinfo);
 171    bool can_change_types() const;
 172    bool has_source_and_destination_hazard() const;
 173
 174    bool reads_flag()
 175    {
 176       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 177    }
 178
 179    bool reads_flag(unsigned c)
 180    {
 181       if (opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2)
 182          return true;
 183
 184       switch (predicate) {
 185       case BRW_PREDICATE_NONE:
 186          return false;
 187       case BRW_PREDICATE_ALIGN16_REPLICATE_X:
 188          return c == 0;
 189       case BRW_PREDICATE_ALIGN16_REPLICATE_Y:
 190          return c == 1;
 191       case BRW_PREDICATE_ALIGN16_REPLICATE_Z:
 192          return c == 2;
 193       case BRW_PREDICATE_ALIGN16_REPLICATE_W:
 194          return c == 3;
 195       default:
 196          return true;
 197       }
 198    }
 199
 200    bool writes_flag()
 201    {
 202       return (conditional_mod && (opcode != BRW_OPCODE_SEL &&
 203                                   opcode != BRW_OPCODE_IF &&
 204                                   opcode != BRW_OPCODE_WHILE));
 205    }
 206 };
 207
 208 /**
 209  * Make the execution of \p inst dependent on the evaluation of a possibly
 210  * inverted predicate.
 211  */
 212 inline vec4_instruction *
 213 set_predicate_inv(enum brw_predicate pred, bool inverse,
 214                   vec4_instruction *inst)
 215 {
 216    inst->predicate = pred;
 217    inst->predicate_inverse = inverse;
 218    return inst;
 219 }
 220
 221 /**
 222  * Make the execution of \p inst dependent on the evaluation of a predicate.
 223  */
 224 inline vec4_instruction *
 225 set_predicate(enum brw_predicate pred, vec4_instruction *inst)
 226 {
 227    return set_predicate_inv(pred, false, inst);
 228 }
 229
 230 /**
 231  * Write the result of evaluating the condition given by \p mod to a flag
 232  * register.
 233  */
 234 inline vec4_instruction *
 235 set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst)
 236 {
 237    inst->conditional_mod = mod;
 238    return inst;
 239 }
 240
 241 /**
 242  * Clamp the result of \p inst to the saturation range of its destination
 243  * datatype.
 244  */
 245 inline vec4_instruction *
 246 set_saturate(bool saturate, vec4_instruction *inst)
 247 {
 248    inst->saturate = saturate;
 249    return inst;
 250 }
 251
 252 } /* namespace brw */
 253
 254 #endif