src/mesa/drivers/dri/i965/brw_ir_vec4.h

   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright © 2011-2015 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef BRW_IR_VEC4_H
  26 #define BRW_IR_VEC4_H
  27
  28 #include "brw_shader.h"
  29 #include "brw_context.h"
  30
  31 namespace brw {
  32
  33 class dst_reg;
  34
  35 class src_reg : public backend_reg
  36 {
  37 public:
  38    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
  39
  40    void init();
  41
  42    src_reg(enum brw_reg_file file, int nr, const glsl_type *type);
  43    src_reg();
  44    src_reg(struct ::brw_reg reg);
  45
  46    bool equals(const src_reg &r) const;
  47
  48    src_reg(class vec4_visitor *v, const struct glsl_type *type);
  49    src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
  50
  51    explicit src_reg(const dst_reg &reg);
  52
  53    src_reg *reladdr;
  54 };
  55
  56 static inline src_reg
  57 retype(src_reg reg, enum brw_reg_type type)
  58 {
  59    reg.type = type;
  60    return reg;
  61 }
  62
  63 static inline src_reg
  64 offset(src_reg reg, unsigned delta)
  65 {
  66    assert(delta == 0 ||
  67           (reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM));
  68    reg.reg_offset += delta;
  69    return reg;
  70 }
  71
  72 /**
  73  * Reswizzle a given source register.
  74  * \sa brw_swizzle().
  75  */
  76 static inline src_reg
  77 swizzle(src_reg reg, unsigned swizzle)
  78 {
  79    if (reg.file == IMM)
  80       reg.ud = brw_swizzle_immediate(reg.type, reg.ud, swizzle);
  81    else
  82       reg.swizzle = brw_compose_swizzle(swizzle, reg.swizzle);
  83
  84    return reg;
  85 }
  86
  87 static inline src_reg
  88 negate(src_reg reg)
  89 {
  90    assert(reg.file != IMM);
  91    reg.negate = !reg.negate;
  92    return reg;
  93 }
  94
  95 static inline bool
  96 is_uniform(const src_reg &reg)
  97 {
  98    return (reg.file == IMM || reg.file == UNIFORM || reg.is_null()) &&
  99           (!reg.reladdr || is_uniform(*reg.reladdr));
 100 }
 101
 102 class dst_reg : public backend_reg
 103 {
 104 public:
 105    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 106
 107    void init();
 108
 109    dst_reg();
 110    dst_reg(enum brw_reg_file file, int nr);
 111    dst_reg(enum brw_reg_file file, int nr, const glsl_type *type,
 112            unsigned writemask);
 113    dst_reg(enum brw_reg_file file, int nr, brw_reg_type type,
 114            unsigned writemask);
 115    dst_reg(struct ::brw_reg reg);
 116    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 117
 118    explicit dst_reg(const src_reg &reg);
 119
 120    bool equals(const dst_reg &r) const;
 121
 122    src_reg *reladdr;
 123 };
 124
 125 static inline dst_reg
 126 retype(dst_reg reg, enum brw_reg_type type)
 127 {
 128    reg.type = type;
 129    return reg;
 130 }
 131
 132 static inline dst_reg
 133 offset(dst_reg reg, unsigned delta)
 134 {
 135    assert(delta == 0 ||
 136           (reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM));
 137    reg.reg_offset += delta;
 138    return reg;
 139 }
 140
 141 static inline dst_reg
 142 writemask(dst_reg reg, unsigned mask)
 143 {
 144    assert(reg.file != IMM);
 145    assert((reg.writemask & mask) != 0);
 146    reg.writemask &= mask;
 147    return reg;
 148 }
 149
 150 class vec4_instruction : public backend_instruction {
 151 public:
 152    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 153
 154    vec4_instruction(enum opcode opcode,
 155                     const dst_reg &dst = dst_reg(),
 156                     const src_reg &src0 = src_reg(),
 157                     const src_reg &src1 = src_reg(),
 158                     const src_reg &src2 = src_reg());
 159
 160    dst_reg dst;
 161    src_reg src[3];
 162
 163    enum brw_urb_write_flags urb_write_flags;
 164
 165    unsigned sol_binding; /**< gen6: SOL binding table index */
 166    bool sol_final_write; /**< gen6: send commit message */
 167    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 168
 169    bool is_send_from_grf();
 170    unsigned regs_read(unsigned arg) const;
 171    bool can_reswizzle(const struct brw_device_info *devinfo, int dst_writemask,
 172                       int swizzle, int swizzle_mask);
 173    void reswizzle(int dst_writemask, int swizzle);
 174    bool can_do_source_mods(const struct brw_device_info *devinfo);
 175    bool can_do_writemask(const struct brw_device_info *devinfo);
 176    bool can_change_types() const;
 177    bool has_source_and_destination_hazard() const;
 178
 179    bool reads_flag()
 180    {
 181       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 182    }
 183
 184    bool reads_flag(unsigned c)
 185    {
 186       if (opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2)
 187          return true;
 188
 189       switch (predicate) {
 190       case BRW_PREDICATE_NONE:
 191          return false;
 192       case BRW_PREDICATE_ALIGN16_REPLICATE_X:
 193          return c == 0;
 194       case BRW_PREDICATE_ALIGN16_REPLICATE_Y:
 195          return c == 1;
 196       case BRW_PREDICATE_ALIGN16_REPLICATE_Z:
 197          return c == 2;
 198       case BRW_PREDICATE_ALIGN16_REPLICATE_W:
 199          return c == 3;
 200       default:
 201          return true;
 202       }
 203    }
 204
 205    bool writes_flag()
 206    {
 207       return (conditional_mod && (opcode != BRW_OPCODE_SEL &&
 208                                   opcode != BRW_OPCODE_IF &&
 209                                   opcode != BRW_OPCODE_WHILE));
 210    }
 211 };
 212
 213 /**
 214  * Make the execution of \p inst dependent on the evaluation of a possibly
 215  * inverted predicate.
 216  */
 217 inline vec4_instruction *
 218 set_predicate_inv(enum brw_predicate pred, bool inverse,
 219                   vec4_instruction *inst)
 220 {
 221    inst->predicate = pred;
 222    inst->predicate_inverse = inverse;
 223    return inst;
 224 }
 225
 226 /**
 227  * Make the execution of \p inst dependent on the evaluation of a predicate.
 228  */
 229 inline vec4_instruction *
 230 set_predicate(enum brw_predicate pred, vec4_instruction *inst)
 231 {
 232    return set_predicate_inv(pred, false, inst);
 233 }
 234
 235 /**
 236  * Write the result of evaluating the condition given by \p mod to a flag
 237  * register.
 238  */
 239 inline vec4_instruction *
 240 set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst)
 241 {
 242    inst->conditional_mod = mod;
 243    return inst;
 244 }
 245
 246 /**
 247  * Clamp the result of \p inst to the saturation range of its destination
 248  * datatype.
 249  */
 250 inline vec4_instruction *
 251 set_saturate(bool saturate, vec4_instruction *inst)
 252 {
 253    inst->saturate = saturate;
 254    return inst;
 255 }
 256
 257 } /* namespace brw */
 258
 259 #endif