src/mesa/drivers/dri/i965/brw_ir_vec4.h

   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright © 2011-2015 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef BRW_IR_VEC4_H
  26 #define BRW_IR_VEC4_H
  27
  28 #include "brw_shader.h"
  29 #include "brw_context.h"
  30
  31 namespace brw {
  32
  33 class dst_reg;
  34
  35 unsigned
  36 swizzle_for_size(int size);
  37
  38 class src_reg : public backend_reg
  39 {
  40 public:
  41    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
  42
  43    void init();
  44
  45    src_reg(register_file file, int reg, const glsl_type *type);
  46    src_reg();
  47    src_reg(float f);
  48    src_reg(uint32_t u);
  49    src_reg(int32_t i);
  50    src_reg(uint8_t vf[4]);
  51    src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
  52    src_reg(struct brw_reg reg);
  53
  54    bool equals(const src_reg &r) const;
  55
  56    src_reg(class vec4_visitor *v, const struct glsl_type *type);
  57    src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
  58
  59    explicit src_reg(dst_reg reg);
  60
  61    GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
  62
  63    src_reg *reladdr;
  64 };
  65
  66 static inline src_reg
  67 retype(src_reg reg, enum brw_reg_type type)
  68 {
  69    reg.fixed_hw_reg.type = reg.type = type;
  70    return reg;
  71 }
  72
  73 static inline src_reg
  74 offset(src_reg reg, unsigned delta)
  75 {
  76    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
  77    reg.reg_offset += delta;
  78    return reg;
  79 }
  80
  81 /**
  82  * Reswizzle a given source register.
  83  * \sa brw_swizzle().
  84  */
  85 static inline src_reg
  86 swizzle(src_reg reg, unsigned swizzle)
  87 {
  88    assert(reg.file != HW_REG);
  89    reg.swizzle = BRW_SWIZZLE4(
  90       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)),
  91       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)),
  92       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)),
  93       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3)));
  94    return reg;
  95 }
  96
  97 static inline src_reg
  98 negate(src_reg reg)
  99 {
 100    assert(reg.file != HW_REG && reg.file != IMM);
 101    reg.negate = !reg.negate;
 102    return reg;
 103 }
 104
 105 class dst_reg : public backend_reg
 106 {
 107 public:
 108    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 109
 110    void init();
 111
 112    dst_reg();
 113    dst_reg(register_file file, int reg);
 114    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 115    dst_reg(struct brw_reg reg);
 116    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 117
 118    explicit dst_reg(src_reg reg);
 119
 120    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 121
 122    src_reg *reladdr;
 123 };
 124
 125 static inline dst_reg
 126 retype(dst_reg reg, enum brw_reg_type type)
 127 {
 128    reg.fixed_hw_reg.type = reg.type = type;
 129    return reg;
 130 }
 131
 132 static inline dst_reg
 133 offset(dst_reg reg, unsigned delta)
 134 {
 135    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 136    reg.reg_offset += delta;
 137    return reg;
 138 }
 139
 140 static inline dst_reg
 141 writemask(dst_reg reg, unsigned mask)
 142 {
 143    assert(reg.file != HW_REG && reg.file != IMM);
 144    assert((reg.writemask & mask) != 0);
 145    reg.writemask &= mask;
 146    return reg;
 147 }
 148
 149 class vec4_instruction : public backend_instruction {
 150 public:
 151    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 152
 153    vec4_instruction(enum opcode opcode,
 154                     const dst_reg &dst = dst_reg(),
 155                     const src_reg &src0 = src_reg(),
 156                     const src_reg &src1 = src_reg(),
 157                     const src_reg &src2 = src_reg());
 158
 159    struct brw_reg get_dst(void);
 160    struct brw_reg get_src(const struct brw_vue_prog_data *prog_data, int i);
 161
 162    dst_reg dst;
 163    src_reg src[3];
 164
 165    enum brw_urb_write_flags urb_write_flags;
 166
 167    unsigned sol_binding; /**< gen6: SOL binding table index */
 168    bool sol_final_write; /**< gen6: send commit message */
 169    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 170
 171    bool is_send_from_grf();
 172    bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
 173    void reswizzle(int dst_writemask, int swizzle);
 174    bool can_do_source_mods(struct brw_context *brw);
 175
 176    bool reads_flag()
 177    {
 178       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 179    }
 180
 181    bool writes_flag()
 182    {
 183       return (conditional_mod && (opcode != BRW_OPCODE_SEL &&
 184                                   opcode != BRW_OPCODE_IF &&
 185                                   opcode != BRW_OPCODE_WHILE));
 186    }
 187 };
 188
 189 } /* namespace brw */
 190
 191 #endif