src/mesa/drivers/dri/i965/brw_link.cpp

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_shader.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_program.h"
  29 #include "compiler/glsl/ir_optimization.h"
  30 #include "program/program.h"
  31 #include "main/shaderapi.h"
  32 #include "main/uniforms.h"
  33
  34 /**
  35  * Performs a compile of the shader stages even when we don't know
  36  * what non-orthogonal state will be set, in the hope that it reflects
  37  * the eventual NOS used, and thus allows us to produce link failures.
  38  */
  39 static bool
  40 brw_shader_precompile(struct gl_context *ctx,
  41                       struct gl_shader_program *sh_prog)
  42 {
  43    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  44    struct gl_shader *tcs = sh_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL];
  45    struct gl_shader *tes = sh_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
  46    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  47    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  48    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
  49
  50    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  51       return false;
  52
  53    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  54       return false;
  55
  56    if (tes && !brw_tes_precompile(ctx, sh_prog, tes->Program))
  57       return false;
  58
  59    if (tcs && !brw_tcs_precompile(ctx, sh_prog, tcs->Program))
  60       return false;
  61
  62    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  63       return false;
  64
  65    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
  66       return false;
  67
  68    return true;
  69 }
  70
  71 static void
  72 brw_lower_packing_builtins(struct brw_context *brw,
  73                            gl_shader_stage shader_type,
  74                            exec_list *ir)
  75 {
  76    const struct brw_compiler *compiler = brw->intelScreen->compiler;
  77
  78    int ops = LOWER_PACK_SNORM_2x16
  79            | LOWER_UNPACK_SNORM_2x16
  80            | LOWER_PACK_UNORM_2x16
  81            | LOWER_UNPACK_UNORM_2x16;
  82
  83    if (compiler->scalar_stage[shader_type]) {
  84       ops |= LOWER_UNPACK_UNORM_4x8
  85            | LOWER_UNPACK_SNORM_4x8
  86            | LOWER_PACK_UNORM_4x8
  87            | LOWER_PACK_SNORM_4x8;
  88    }
  89
  90    if (brw->gen >= 7) {
  91       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
  92        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
  93        * lowering is needed. For SOA code, the Half2x16 ops must be
  94        * scalarized.
  95        */
  96       if (compiler->scalar_stage[shader_type]) {
  97          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
  98              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
  99       }
 100    } else {
 101       ops |= LOWER_PACK_HALF_2x16
 102           |  LOWER_UNPACK_HALF_2x16;
 103    }
 104
 105    lower_packing_builtins(ir, ops);
 106 }
 107
 108 static void
 109 process_glsl_ir(gl_shader_stage stage,
 110                 struct brw_context *brw,
 111                 struct gl_shader_program *shader_prog,
 112                 struct gl_shader *shader)
 113 {
 114    struct gl_context *ctx = &brw->ctx;
 115    const struct brw_compiler *compiler = brw->intelScreen->compiler;
 116    const struct gl_shader_compiler_options *options =
 117       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 118
 119    /* Temporary memory context for any new IR. */
 120    void *mem_ctx = ralloc_context(NULL);
 121
 122    ralloc_adopt(mem_ctx, shader->ir);
 123
 124    /* lower_packing_builtins() inserts arithmetic instructions, so it
 125     * must precede lower_instructions().
 126     */
 127    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 128    do_mat_op_to_vec(shader->ir);
 129    lower_instructions(shader->ir,
 130                       MOD_TO_FLOOR |
 131                       DIV_TO_MUL_RCP |
 132                       SUB_TO_ADD_NEG |
 133                       EXP_TO_EXP2 |
 134                       LOG_TO_LOG2 |
 135                       LDEXP_TO_ARITH |
 136                       CARRY_TO_ARITH |
 137                       BORROW_TO_ARITH);
 138
 139    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 140     * if-statements need to be flattened.
 141     */
 142    if (brw->gen < 6)
 143       lower_if_to_cond_assign(shader->ir, 16);
 144
 145    do_lower_texture_projection(shader->ir);
 146    brw_lower_texture_gradients(brw, shader->ir);
 147    do_vec_index_to_cond_assign(shader->ir);
 148    lower_vector_insert(shader->ir, true);
 149    lower_offset_arrays(shader->ir);
 150    brw_do_lower_unnormalized_offset(shader->ir);
 151    lower_noise(shader->ir);
 152    lower_quadop_vector(shader->ir, false);
 153
 154    bool lowered_variable_indexing =
 155       lower_variable_index_to_cond_assign((gl_shader_stage)stage,
 156                                           shader->ir,
 157                                           options->EmitNoIndirectInput,
 158                                           options->EmitNoIndirectOutput,
 159                                           options->EmitNoIndirectTemp,
 160                                           options->EmitNoIndirectUniform);
 161
 162    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 163       perf_debug("Unsupported form of variable indexing in %s; falling "
 164                  "back to very inefficient code generation\n",
 165                  _mesa_shader_stage_to_abbrev(shader->Stage));
 166    }
 167
 168    bool progress;
 169    do {
 170       progress = false;
 171
 172       if (compiler->scalar_stage[shader->Stage]) {
 173          brw_do_channel_expressions(shader->ir);
 174          brw_do_vector_splitting(shader->ir);
 175       }
 176
 177       progress = do_lower_jumps(shader->ir, true, true,
 178                                 true, /* main return */
 179                                 false, /* continue */
 180                                 false /* loops */
 181                                 ) || progress;
 182
 183       progress = do_common_optimization(shader->ir, true, true,
 184                                         options, ctx->Const.NativeIntegers) || progress;
 185    } while (progress);
 186
 187    validate_ir_tree(shader->ir);
 188
 189    /* Now that we've finished altering the linked IR, reparent any live IR back
 190     * to the permanent memory context, and free the temporary one (discarding any
 191     * junk we optimized away).
 192     */
 193    reparent_ir(shader->ir, shader->ir);
 194    ralloc_free(mem_ctx);
 195
 196    if (ctx->_Shader->Flags & GLSL_DUMP) {
 197       fprintf(stderr, "\n");
 198       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 199               _mesa_shader_stage_to_string(shader->Stage),
 200               shader_prog->Name);
 201       _mesa_print_ir(stderr, shader->ir, NULL);
 202       fprintf(stderr, "\n");
 203    }
 204 }
 205
 206 extern "C" GLboolean
 207 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 208 {
 209    struct brw_context *brw = brw_context(ctx);
 210    const struct brw_compiler *compiler = brw->intelScreen->compiler;
 211    unsigned int stage;
 212
 213    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 214       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 215       if (!shader)
 216          continue;
 217
 218       struct gl_program *prog =
 219          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 220                                 shader->Name);
 221       if (!prog)
 222         return false;
 223       prog->Parameters = _mesa_new_parameter_list();
 224
 225       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 226
 227       process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
 228
 229       /* Make a pass over the IR to add state references for any built-in
 230        * uniforms that are used.  This has to be done now (during linking).
 231        * Code generation doesn't happen until the first time this shader is
 232        * used for rendering.  Waiting until then to generate the parameters is
 233        * too late.  At that point, the values for the built-in uniforms won't
 234        * get sent to the shader.
 235        */
 236       foreach_in_list(ir_instruction, node, shader->ir) {
 237          ir_variable *var = node->as_variable();
 238
 239          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 240              || (strncmp(var->name, "gl_", 3) != 0))
 241             continue;
 242
 243          const ir_state_slot *const slots = var->get_state_slots();
 244          assert(slots != NULL);
 245
 246          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 247             _mesa_add_state_reference(prog->Parameters,
 248                                       (gl_state_index *) slots[i].tokens);
 249          }
 250       }
 251
 252       do_set_program_inouts(shader->ir, prog, shader->Stage);
 253
 254       prog->SamplersUsed = shader->active_samplers;
 255       prog->ShadowSamplers = shader->shadow_samplers;
 256       _mesa_update_shader_textures_used(shProg, prog);
 257
 258       _mesa_reference_program(ctx, &shader->Program, prog);
 259
 260       brw_add_texrect_params(prog);
 261
 262       prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
 263                                  compiler->scalar_stage[stage]);
 264
 265       _mesa_reference_program(ctx, &prog, NULL);
 266    }
 267
 268    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 269       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 270          const struct gl_shader *sh = shProg->Shaders[i];
 271          if (!sh)
 272             continue;
 273
 274          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 275                  _mesa_shader_stage_to_string(sh->Stage),
 276                  i, shProg->Name);
 277          fprintf(stderr, "%s", sh->Source);
 278          fprintf(stderr, "\n");
 279       }
 280    }
 281
 282    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 283       return false;
 284
 285    return true;
 286 }