i965: Update TexturesUsed after linking the shaders
[mesa.git] / src / mesa / drivers / dri / i965 / brw_link.cpp
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "compiler/brw_nir.h"
26 #include "brw_program.h"
27 #include "compiler/glsl/gl_nir.h"
28 #include "compiler/glsl/gl_nir_linker.h"
29 #include "compiler/glsl/ir.h"
30 #include "compiler/glsl/ir_optimization.h"
31 #include "compiler/glsl/program.h"
32 #include "compiler/nir/nir_serialize.h"
33 #include "program/program.h"
34 #include "main/glspirv.h"
35 #include "main/mtypes.h"
36 #include "main/shaderapi.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39
40 /**
41 * Performs a compile of the shader stages even when we don't know
42 * what non-orthogonal state will be set, in the hope that it reflects
43 * the eventual NOS used, and thus allows us to produce link failures.
44 */
45 static bool
46 brw_shader_precompile(struct gl_context *ctx,
47 struct gl_shader_program *sh_prog)
48 {
49 struct gl_linked_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
50 struct gl_linked_shader *tcs = sh_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL];
51 struct gl_linked_shader *tes = sh_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
52 struct gl_linked_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
53 struct gl_linked_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
54 struct gl_linked_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
55
56 if (fs && !brw_fs_precompile(ctx, fs->Program))
57 return false;
58
59 if (gs && !brw_gs_precompile(ctx, gs->Program))
60 return false;
61
62 if (tes && !brw_tes_precompile(ctx, sh_prog, tes->Program))
63 return false;
64
65 if (tcs && !brw_tcs_precompile(ctx, sh_prog, tcs->Program))
66 return false;
67
68 if (vs && !brw_vs_precompile(ctx, vs->Program))
69 return false;
70
71 if (cs && !brw_cs_precompile(ctx, cs->Program))
72 return false;
73
74 return true;
75 }
76
77 static void
78 brw_lower_packing_builtins(struct brw_context *brw,
79 exec_list *ir)
80 {
81 const struct gen_device_info *devinfo = &brw->screen->devinfo;
82
83 /* Gens < 7 don't have instructions to convert to or from half-precision,
84 * and Gens < 6 don't expose that functionality.
85 */
86 if (devinfo->gen != 6)
87 return;
88
89 lower_packing_builtins(ir, LOWER_PACK_HALF_2x16 | LOWER_UNPACK_HALF_2x16);
90 }
91
92 static void
93 process_glsl_ir(struct brw_context *brw,
94 struct gl_shader_program *shader_prog,
95 struct gl_linked_shader *shader)
96 {
97 const struct gen_device_info *devinfo = &brw->screen->devinfo;
98 struct gl_context *ctx = &brw->ctx;
99
100 /* Temporary memory context for any new IR. */
101 void *mem_ctx = ralloc_context(NULL);
102
103 ralloc_adopt(mem_ctx, shader->ir);
104
105 lower_blend_equation_advanced(
106 shader, ctx->Extensions.KHR_blend_equation_advanced_coherent);
107
108 /* lower_packing_builtins() inserts arithmetic instructions, so it
109 * must precede lower_instructions().
110 */
111 brw_lower_packing_builtins(brw, shader->ir);
112 do_mat_op_to_vec(shader->ir);
113
114 unsigned instructions_to_lower = (DIV_TO_MUL_RCP |
115 SUB_TO_ADD_NEG |
116 EXP_TO_EXP2 |
117 LOG_TO_LOG2 |
118 DFREXP_DLDEXP_TO_ARITH);
119 if (devinfo->gen < 7) {
120 instructions_to_lower |= BIT_COUNT_TO_MATH |
121 EXTRACT_TO_SHIFTS |
122 INSERT_TO_SHIFTS |
123 REVERSE_TO_SHIFTS;
124 }
125
126 lower_instructions(shader->ir, instructions_to_lower);
127
128 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
129 * if-statements need to be flattened.
130 */
131 if (devinfo->gen < 6)
132 lower_if_to_cond_assign(shader->Stage, shader->ir, 16);
133
134 do_lower_texture_projection(shader->ir);
135 do_vec_index_to_cond_assign(shader->ir);
136 lower_vector_insert(shader->ir, true);
137 lower_offset_arrays(shader->ir);
138 lower_noise(shader->ir);
139 lower_quadop_vector(shader->ir, false);
140
141 validate_ir_tree(shader->ir);
142
143 /* Now that we've finished altering the linked IR, reparent any live IR back
144 * to the permanent memory context, and free the temporary one (discarding any
145 * junk we optimized away).
146 */
147 reparent_ir(shader->ir, shader->ir);
148 ralloc_free(mem_ctx);
149
150 if (ctx->_Shader->Flags & GLSL_DUMP) {
151 fprintf(stderr, "\n");
152 if (shader->ir) {
153 fprintf(stderr, "GLSL IR for linked %s program %d:\n",
154 _mesa_shader_stage_to_string(shader->Stage),
155 shader_prog->Name);
156 _mesa_print_ir(stderr, shader->ir, NULL);
157 } else {
158 fprintf(stderr, "No GLSL IR for linked %s program %d (shader may be "
159 "from cache)\n", _mesa_shader_stage_to_string(shader->Stage),
160 shader_prog->Name);
161 }
162 fprintf(stderr, "\n");
163 }
164 }
165
166 static void
167 unify_interfaces(struct shader_info **infos)
168 {
169 struct shader_info *prev_info = NULL;
170
171 for (unsigned i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
172 if (!infos[i])
173 continue;
174
175 if (prev_info) {
176 prev_info->outputs_written |= infos[i]->inputs_read &
177 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
178 infos[i]->inputs_read |= prev_info->outputs_written &
179 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
180
181 prev_info->patch_outputs_written |= infos[i]->patch_inputs_read;
182 infos[i]->patch_inputs_read |= prev_info->patch_outputs_written;
183 }
184 prev_info = infos[i];
185 }
186 }
187
188 static void
189 update_xfb_info(struct gl_transform_feedback_info *xfb_info,
190 struct shader_info *info)
191 {
192 if (!xfb_info)
193 return;
194
195 for (unsigned i = 0; i < xfb_info->NumOutputs; i++) {
196 struct gl_transform_feedback_output *output = &xfb_info->Outputs[i];
197
198 /* The VUE header contains three scalar fields packed together:
199 * - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
200 * - gl_Layer is stored in VARYING_SLOT_PSIZ.y
201 * - gl_ViewportIndex is stored in VARYING_SLOT_PSIZ.z
202 */
203 switch (output->OutputRegister) {
204 case VARYING_SLOT_LAYER:
205 assert(output->NumComponents == 1);
206 output->OutputRegister = VARYING_SLOT_PSIZ;
207 output->ComponentOffset = 1;
208 break;
209 case VARYING_SLOT_VIEWPORT:
210 assert(output->NumComponents == 1);
211 output->OutputRegister = VARYING_SLOT_PSIZ;
212 output->ComponentOffset = 2;
213 break;
214 case VARYING_SLOT_PSIZ:
215 assert(output->NumComponents == 1);
216 output->ComponentOffset = 3;
217 break;
218 }
219
220 info->outputs_written |= 1ull << output->OutputRegister;
221 }
222 }
223
224 extern "C" GLboolean
225 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
226 {
227 struct brw_context *brw = brw_context(ctx);
228 const struct brw_compiler *compiler = brw->screen->compiler;
229 unsigned int stage;
230 struct shader_info *infos[MESA_SHADER_STAGES] = { 0, };
231
232 if (shProg->data->LinkStatus == LINKING_SKIPPED)
233 return GL_TRUE;
234
235 for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
236 struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
237 if (!shader)
238 continue;
239
240 struct gl_program *prog = shader->Program;
241 prog->Parameters = _mesa_new_parameter_list();
242
243 if (!shader->spirv_data)
244 process_glsl_ir(brw, shProg, shader);
245
246 _mesa_copy_linked_program_data(shProg, shader);
247
248 prog->ShadowSamplers = shader->shadow_samplers;
249
250 bool debug_enabled =
251 (INTEL_DEBUG & intel_debug_flag_for_shader_stage(shader->Stage));
252
253 if (debug_enabled && shader->ir) {
254 fprintf(stderr, "GLSL IR for native %s shader %d:\n",
255 _mesa_shader_stage_to_string(shader->Stage), shProg->Name);
256 _mesa_print_ir(stderr, shader->ir, NULL);
257 fprintf(stderr, "\n\n");
258 }
259
260 prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
261 compiler->scalar_stage[stage]);
262 }
263
264 /* Determine first and last stage. */
265 unsigned first = MESA_SHADER_STAGES;
266 unsigned last = 0;
267 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
268 if (!shProg->_LinkedShaders[i])
269 continue;
270 if (first == MESA_SHADER_STAGES)
271 first = i;
272 last = i;
273 }
274
275 /* Linking the stages in the opposite order (from fragment to vertex)
276 * ensures that inter-shader outputs written to in an earlier stage
277 * are eliminated if they are (transitively) not used in a later
278 * stage.
279 *
280 * TODO: Look into Shadow of Mordor regressions on HSW and enable this for
281 * all platforms. See: https://bugs.freedesktop.org/show_bug.cgi?id=103537
282 */
283 if (first != last && brw->screen->devinfo.gen >= 8) {
284 int next = last;
285 for (int i = next - 1; i >= 0; i--) {
286 if (shProg->_LinkedShaders[i] == NULL)
287 continue;
288
289 brw_nir_link_shaders(compiler,
290 &shProg->_LinkedShaders[i]->Program->nir,
291 &shProg->_LinkedShaders[next]->Program->nir);
292 next = i;
293 }
294 }
295
296 for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
297 struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
298 if (!shader)
299 continue;
300
301 struct gl_program *prog = shader->Program;
302
303 _mesa_update_shader_textures_used(shProg, prog);
304
305 brw_shader_gather_info(prog->nir, prog);
306
307 NIR_PASS_V(prog->nir, gl_nir_lower_samplers, shProg);
308 NIR_PASS_V(prog->nir, gl_nir_lower_atomics, shProg, false);
309 NIR_PASS_V(prog->nir, nir_lower_atomics_to_ssbo,
310 prog->nir->info.num_abos);
311
312 infos[stage] = &prog->nir->info;
313
314 update_xfb_info(prog->sh.LinkedTransformFeedback, infos[stage]);
315
316 /* Make a pass over the IR to add state references for any built-in
317 * uniforms that are used. This has to be done now (during linking).
318 * Code generation doesn't happen until the first time this shader is
319 * used for rendering. Waiting until then to generate the parameters is
320 * too late. At that point, the values for the built-in uniforms won't
321 * get sent to the shader.
322 */
323 nir_foreach_variable(var, &prog->nir->uniforms) {
324 if (strncmp(var->name, "gl_", 3) == 0) {
325 const nir_state_slot *const slots = var->state_slots;
326 assert(var->state_slots != NULL);
327
328 for (unsigned int i = 0; i < var->num_state_slots; i++) {
329 _mesa_add_state_reference(prog->Parameters, slots[i].tokens);
330 }
331 }
332 }
333 }
334
335 /* The linker tries to dead code eliminate unused varying components,
336 * and make sure interfaces match. But it isn't able to do so in all
337 * cases. So, explicitly make the interfaces match by OR'ing together
338 * the inputs_read/outputs_written bitfields of adjacent stages.
339 */
340 if (!shProg->SeparateShader)
341 unify_interfaces(infos);
342
343 if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
344 for (unsigned i = 0; i < shProg->NumShaders; i++) {
345 const struct gl_shader *sh = shProg->Shaders[i];
346 if (!sh)
347 continue;
348
349 fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
350 _mesa_shader_stage_to_string(sh->Stage),
351 i, shProg->Name);
352 fprintf(stderr, "%s", sh->Source);
353 fprintf(stderr, "\n");
354 }
355 }
356
357 if (brw->ctx.Cache) {
358 for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
359 struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
360 if (!shader)
361 continue;
362
363 struct gl_program *prog = shader->Program;
364 brw_program_serialize_nir(ctx, prog);
365 }
366 }
367
368 if (brw->precompile && !brw_shader_precompile(ctx, shProg))
369 return false;
370
371 /* SPIR-V programs build its resource list from linked NIR shaders. */
372 if (!shProg->data->spirv)
373 build_program_resource_list(ctx, shProg);
374 else
375 nir_build_program_resource_list(ctx, shProg);
376
377 for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
378 struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
379 if (!shader)
380 continue;
381
382 /* The GLSL IR won't be needed anymore. */
383 ralloc_free(shader->ir);
384 shader->ir = NULL;
385 }
386
387 return true;
388 }