2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
37 #include "intel_regions.h"
39 #include "brw_context.h"
40 #include "brw_state.h"
41 #include "brw_defines.h"
43 #include "main/fbobject.h"
44 #include "main/glformats.h"
46 /* Constant single cliprect for framebuffer object or DRI2 drawing */
47 static void upload_drawing_rect(struct brw_context
*brw
)
49 struct gl_context
*ctx
= &brw
->ctx
;
52 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
53 OUT_BATCH(0); /* xmin, ymin */
54 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
55 ((ctx
->DrawBuffer
->Height
- 1) << 16));
60 const struct brw_tracked_state brw_drawing_rect
= {
63 .brw
= BRW_NEW_CONTEXT
,
66 .emit
= upload_drawing_rect
70 * Upload the binding table pointers, which point each stage's array of surface
73 * The binding table pointers are relative to the surface state base address,
74 * which points at the batchbuffer containing the streamed batch state.
76 static void upload_binding_table_pointers(struct brw_context
*brw
)
79 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 | (6 - 2));
80 OUT_BATCH(brw
->vs
.base
.bind_bo_offset
);
81 OUT_BATCH(0); /* gs */
82 OUT_BATCH(0); /* clip */
83 OUT_BATCH(0); /* sf */
84 OUT_BATCH(brw
->wm
.bind_bo_offset
);
88 const struct brw_tracked_state brw_binding_table_pointers
= {
91 .brw
= (BRW_NEW_BATCH
|
92 BRW_NEW_STATE_BASE_ADDRESS
|
93 BRW_NEW_VS_BINDING_TABLE
|
94 BRW_NEW_GS_BINDING_TABLE
|
95 BRW_NEW_PS_BINDING_TABLE
),
98 .emit
= upload_binding_table_pointers
,
102 * Upload the binding table pointers, which point each stage's array of surface
105 * The binding table pointers are relative to the surface state base address,
106 * which points at the batchbuffer containing the streamed batch state.
108 static void upload_gen6_binding_table_pointers(struct brw_context
*brw
)
111 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
112 GEN6_BINDING_TABLE_MODIFY_VS
|
113 GEN6_BINDING_TABLE_MODIFY_GS
|
114 GEN6_BINDING_TABLE_MODIFY_PS
|
116 OUT_BATCH(brw
->vs
.base
.bind_bo_offset
); /* vs */
117 OUT_BATCH(brw
->ff_gs
.bind_bo_offset
); /* gs */
118 OUT_BATCH(brw
->wm
.bind_bo_offset
); /* wm/ps */
122 const struct brw_tracked_state gen6_binding_table_pointers
= {
125 .brw
= (BRW_NEW_BATCH
|
126 BRW_NEW_STATE_BASE_ADDRESS
|
127 BRW_NEW_VS_BINDING_TABLE
|
128 BRW_NEW_GS_BINDING_TABLE
|
129 BRW_NEW_PS_BINDING_TABLE
),
132 .emit
= upload_gen6_binding_table_pointers
,
136 * Upload pointers to the per-stage state.
138 * The state pointers in this packet are all relative to the general state
139 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
141 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
144 /* Need to flush before changing clip max threads for errata. */
151 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
152 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
153 brw
->vs
.base
.state_offset
);
154 if (brw
->ff_gs
.prog_active
)
155 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
156 brw
->ff_gs
.state_offset
| 1);
159 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
160 brw
->clip
.state_offset
| 1);
161 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
162 brw
->sf
.state_offset
);
163 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
164 brw
->wm
.state_offset
);
165 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
166 brw
->cc
.state_offset
);
169 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
172 static void upload_psp_urb_cbs(struct brw_context
*brw
)
174 upload_pipelined_state_pointers(brw
);
175 brw_upload_urb_fence(brw
);
176 brw_upload_cs_urb_state(brw
);
179 const struct brw_tracked_state brw_psp_urb_cbs
= {
182 .brw
= (BRW_NEW_URB_FENCE
|
184 BRW_NEW_STATE_BASE_ADDRESS
),
185 .cache
= (CACHE_NEW_VS_UNIT
|
186 CACHE_NEW_FF_GS_UNIT
|
187 CACHE_NEW_FF_GS_PROG
|
188 CACHE_NEW_CLIP_UNIT
|
193 .emit
= upload_psp_urb_cbs
,
197 brw_depthbuffer_format(struct brw_context
*brw
)
199 struct gl_context
*ctx
= &brw
->ctx
;
200 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
201 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
202 struct intel_renderbuffer
*srb
;
205 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
206 !srb
->mt
->stencil_mt
&&
207 (intel_rb_format(srb
) == MESA_FORMAT_S8_Z24
||
208 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_X24S8
)) {
213 return BRW_DEPTHFORMAT_D32_FLOAT
;
215 switch (drb
->mt
->format
) {
216 case MESA_FORMAT_Z16
:
217 return BRW_DEPTHFORMAT_D16_UNORM
;
218 case MESA_FORMAT_Z32_FLOAT
:
219 return BRW_DEPTHFORMAT_D32_FLOAT
;
220 case MESA_FORMAT_X8_Z24
:
222 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
224 /* Use D24_UNORM_S8, not D24_UNORM_X8.
226 * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
227 * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
228 * 3DSTATE_DEPTH_BUFFER.Surface_Format).
230 * However, on Gen5, D24_UNORM_X8 may be used only if separate
231 * stencil is enabled, and we never enable it. From the Ironlake PRM,
232 * same section as above, Bit 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Buffer_Enable:
233 * If this field is disabled, the Surface Format of the depth
234 * buffer cannot be D24_UNORM_X8_UINT.
236 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
238 case MESA_FORMAT_S8_Z24
:
239 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
240 case MESA_FORMAT_Z32_FLOAT_X24S8
:
241 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT
;
243 _mesa_problem(ctx
, "Unexpected depth format %s\n",
244 _mesa_get_format_name(intel_rb_format(drb
)));
245 return BRW_DEPTHFORMAT_D16_UNORM
;
250 * Returns the mask of how many bits of x and y must be handled through the
251 * depthbuffer's draw offset x and y fields.
253 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
254 * between the depth, hiz, and stencil buffers. Because it can be hard to get
255 * all 3 to agree on this value, we want to do as much drawing offset
256 * adjustment as possible by moving the base offset of the 3 buffers, which is
257 * restricted to tile boundaries.
259 * For each buffer, the remainder must be applied through the x/y draw offset.
260 * This returns the worst-case mask of the low bits that have to go into the
261 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
262 * mask, then we're in trouble.
265 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
266 uint32_t depth_level
,
267 uint32_t depth_layer
,
268 struct intel_mipmap_tree
*stencil_mt
,
269 uint32_t *out_tile_mask_x
,
270 uint32_t *out_tile_mask_y
)
272 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
275 intel_region_get_tile_masks(depth_mt
->region
,
276 &tile_mask_x
, &tile_mask_y
, false);
278 if (intel_miptree_slice_has_hiz(depth_mt
, depth_level
, depth_layer
)) {
279 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
280 intel_region_get_tile_masks(depth_mt
->hiz_mt
->region
,
281 &hiz_tile_mask_x
, &hiz_tile_mask_y
, false);
283 /* Each HiZ row represents 2 rows of pixels */
284 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
286 tile_mask_x
|= hiz_tile_mask_x
;
287 tile_mask_y
|= hiz_tile_mask_y
;
292 if (stencil_mt
->stencil_mt
)
293 stencil_mt
= stencil_mt
->stencil_mt
;
295 if (stencil_mt
->format
== MESA_FORMAT_S8
) {
296 /* Separate stencil buffer uses 64x64 tiles. */
300 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
301 intel_region_get_tile_masks(stencil_mt
->region
,
302 &stencil_tile_mask_x
,
303 &stencil_tile_mask_y
, false);
305 tile_mask_x
|= stencil_tile_mask_x
;
306 tile_mask_y
|= stencil_tile_mask_y
;
310 *out_tile_mask_x
= tile_mask_x
;
311 *out_tile_mask_y
= tile_mask_y
;
314 static struct intel_mipmap_tree
*
315 get_stencil_miptree(struct intel_renderbuffer
*irb
)
319 if (irb
->mt
->stencil_mt
)
320 return irb
->mt
->stencil_mt
;
325 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
326 GLbitfield clear_mask
)
328 struct gl_context
*ctx
= &brw
->ctx
;
329 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
330 bool rebase_depth
= false;
331 bool rebase_stencil
= false;
332 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
333 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
334 struct intel_mipmap_tree
*depth_mt
= NULL
;
335 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
336 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
337 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
338 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
339 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
342 depth_mt
= depth_irb
->mt
;
344 /* Initialize brw->depthstencil to 'nop' workaround state.
346 brw
->depthstencil
.tile_x
= 0;
347 brw
->depthstencil
.tile_y
= 0;
348 brw
->depthstencil
.depth_offset
= 0;
349 brw
->depthstencil
.stencil_offset
= 0;
350 brw
->depthstencil
.hiz_offset
= 0;
351 brw
->depthstencil
.depth_mt
= NULL
;
352 brw
->depthstencil
.stencil_mt
= NULL
;
354 brw
->depthstencil
.depth_mt
= depth_mt
;
356 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
358 /* Gen7+ doesn't require the workarounds, since we always program the
359 * surface state at the start of the whole surface.
364 /* Check if depth buffer is in depth/stencil format. If so, then it's only
365 * safe to invalidate it if we're also clearing stencil, and both depth_irb
366 * and stencil_irb point to the same miptree.
368 * Note: it's not sufficient to check for the case where
369 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
370 * because this fails to catch depth/stencil buffers on hardware that uses
371 * separate stencil. To catch that case, we check whether
372 * depth_mt->stencil_mt is non-NULL.
374 if (depth_irb
&& invalidate_depth
&&
375 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
376 depth_mt
->stencil_mt
)) {
377 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
378 && depth_irb
->mt
== stencil_irb
->mt
;
381 uint32_t tile_mask_x
, tile_mask_y
;
382 brw_get_depthstencil_tile_masks(depth_mt
,
383 depth_mt
? depth_irb
->mt_level
: 0,
384 depth_mt
? depth_irb
->mt_layer
: 0,
386 &tile_mask_x
, &tile_mask_y
);
389 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
390 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
392 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
393 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
394 * Coordinate Offset X/Y":
396 * "The 3 LSBs of both offsets must be zero to ensure correct
399 if (tile_x
& 7 || tile_y
& 7)
402 /* We didn't even have intra-tile offsets before g45. */
403 if (brw
->gen
== 4 && !brw
->is_g4x
) {
404 if (tile_x
|| tile_y
)
409 perf_debug("HW workaround: blitting depth level %d to a temporary "
410 "to fix alignment (depth tile offset %d,%d)\n",
411 depth_irb
->mt_level
, tile_x
, tile_y
);
412 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
413 /* In the case of stencil_irb being the same packed depth/stencil
414 * texture but not the same rb, make it point at our rebased mt, too.
417 stencil_irb
!= depth_irb
&&
418 stencil_irb
->mt
== depth_mt
) {
419 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
420 intel_renderbuffer_set_draw_offset(stencil_irb
);
423 stencil_mt
= get_stencil_miptree(stencil_irb
);
425 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
426 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
430 stencil_mt
= get_stencil_miptree(stencil_irb
);
431 intel_miptree_get_image_offset(stencil_mt
,
432 stencil_irb
->mt_level
,
433 stencil_irb
->mt_layer
,
434 &stencil_draw_x
, &stencil_draw_y
);
435 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
436 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
438 /* If stencil doesn't match depth, then we'll need to rebase stencil
439 * as well. (if we hadn't decided to rebase stencil before, the
440 * post-stencil depth test will also rebase depth to try to match it
443 if (tile_x
!= stencil_tile_x
||
444 tile_y
!= stencil_tile_y
) {
445 rebase_stencil
= true;
450 /* If we have (just) stencil, check it for ignored low bits as well */
452 intel_miptree_get_image_offset(stencil_mt
,
453 stencil_irb
->mt_level
,
454 stencil_irb
->mt_layer
,
455 &stencil_draw_x
, &stencil_draw_y
);
456 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
457 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
459 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
460 rebase_stencil
= true;
462 if (brw
->gen
== 4 && !brw
->is_g4x
) {
463 if (stencil_tile_x
|| stencil_tile_y
)
464 rebase_stencil
= true;
468 if (rebase_stencil
) {
469 perf_debug("HW workaround: blitting stencil level %d to a temporary "
470 "to fix alignment (stencil tile offset %d,%d)\n",
471 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
473 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
474 stencil_mt
= get_stencil_miptree(stencil_irb
);
476 intel_miptree_get_image_offset(stencil_mt
,
477 stencil_irb
->mt_level
,
478 stencil_irb
->mt_layer
,
479 &stencil_draw_x
, &stencil_draw_y
);
480 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
481 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
483 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
484 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
485 intel_renderbuffer_set_draw_offset(depth_irb
);
486 } else if (depth_irb
&& !rebase_depth
) {
487 if (tile_x
!= stencil_tile_x
||
488 tile_y
!= stencil_tile_y
) {
489 perf_debug("HW workaround: blitting depth level %d to a temporary "
490 "to match stencil level %d alignment (depth tile offset "
491 "%d,%d, stencil offset %d,%d)\n",
493 stencil_irb
->mt_level
,
495 stencil_tile_x
, stencil_tile_y
);
497 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
499 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
500 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
502 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
503 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
504 intel_renderbuffer_set_draw_offset(stencil_irb
);
507 WARN_ONCE(stencil_tile_x
!= tile_x
||
508 stencil_tile_y
!= tile_y
,
509 "Rebased stencil tile offset (%d,%d) doesn't match depth "
510 "tile offset (%d,%d).\n",
511 stencil_tile_x
, stencil_tile_y
,
518 tile_x
= stencil_tile_x
;
519 tile_y
= stencil_tile_y
;
522 /* While we just tried to get everything aligned, we may have failed to do
523 * so in the case of rendering to array or 3D textures, where nonzero faces
524 * will still have an offset post-rebase. At least give an informative
527 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
528 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
529 "Truncating offset, bad rendering may occur.\n");
533 /* Now, after rebasing, save off the new dephtstencil state so the hardware
534 * packets can just dereference that without re-calculating tile offsets.
536 brw
->depthstencil
.tile_x
= tile_x
;
537 brw
->depthstencil
.tile_y
= tile_y
;
539 depth_mt
= depth_irb
->mt
;
540 brw
->depthstencil
.depth_mt
= depth_mt
;
541 brw
->depthstencil
.depth_offset
=
542 intel_region_get_aligned_offset(depth_mt
->region
,
543 depth_irb
->draw_x
& ~tile_mask_x
,
544 depth_irb
->draw_y
& ~tile_mask_y
,
546 if (intel_renderbuffer_has_hiz(depth_irb
)) {
547 brw
->depthstencil
.hiz_offset
=
548 intel_region_get_aligned_offset(depth_mt
->region
,
549 depth_irb
->draw_x
& ~tile_mask_x
,
550 (depth_irb
->draw_y
& ~tile_mask_y
) /
556 stencil_mt
= get_stencil_miptree(stencil_irb
);
558 brw
->depthstencil
.stencil_mt
= stencil_mt
;
559 if (stencil_mt
->format
== MESA_FORMAT_S8
) {
560 /* Note: we can't compute the stencil offset using
561 * intel_region_get_aligned_offset(), because stencil_region claims
562 * that the region is untiled even though it's W tiled.
564 brw
->depthstencil
.stencil_offset
=
565 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->region
->pitch
+
566 (stencil_draw_x
& ~tile_mask_x
) * 64;
572 brw_emit_depthbuffer(struct brw_context
*brw
)
574 struct gl_context
*ctx
= &brw
->ctx
;
575 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
577 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
578 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
579 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
580 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
581 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
582 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
583 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
584 bool separate_stencil
= false;
585 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
586 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
587 uint32_t depth_offset
= 0;
588 uint32_t width
= 1, height
= 1;
591 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S8
;
593 /* Gen7 supports only separate stencil */
594 assert(separate_stencil
|| brw
->gen
< 7);
597 /* If there's a packed depth/stencil bound to stencil only, we need to
598 * emit the packed depth/stencil buffer packet.
600 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
601 depth_irb
= stencil_irb
;
602 depth_mt
= stencil_mt
;
605 if (depth_irb
&& depth_mt
) {
606 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
607 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
608 * depthstencil format.
610 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
611 * set to the same value. Gens after 7 implicitly always set
612 * Separate_Stencil_Enable; software cannot disable it.
614 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
615 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
618 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
619 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
621 assert(brw
->gen
< 6 || depth_mt
->region
->tiling
== I915_TILING_Y
);
622 assert(!hiz
|| depth_mt
->region
->tiling
== I915_TILING_Y
);
624 depthbuffer_format
= brw_depthbuffer_format(brw
);
625 depth_surface_type
= BRW_SURFACE_2D
;
626 depth_offset
= brw
->depthstencil
.depth_offset
;
627 width
= depth_irb
->Base
.Base
.Width
;
628 height
= depth_irb
->Base
.Base
.Height
;
629 } else if (separate_stencil
) {
631 * There exists a separate stencil buffer but no depth buffer.
633 * The stencil buffer inherits most of its fields from
634 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
637 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
638 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
639 * [DevGT+]: This field must be set to TRUE.
641 assert(brw
->has_separate_stencil
);
643 depth_surface_type
= BRW_SURFACE_2D
;
644 width
= stencil_irb
->Base
.Base
.Width
;
645 height
= stencil_irb
->Base
.Base
.Height
;
648 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
649 depthbuffer_format
, depth_surface_type
,
650 stencil_mt
, hiz
, separate_stencil
,
651 width
, height
, tile_x
, tile_y
);
655 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
656 struct intel_mipmap_tree
*depth_mt
,
657 uint32_t depth_offset
, uint32_t depthbuffer_format
,
658 uint32_t depth_surface_type
,
659 struct intel_mipmap_tree
*stencil_mt
,
660 bool hiz
, bool separate_stencil
,
661 uint32_t width
, uint32_t height
,
662 uint32_t tile_x
, uint32_t tile_y
)
664 /* Enable the hiz bit if we're doing separate stencil, because it and the
665 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
666 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
667 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
668 * Enable must also be enabled.
670 * [DevGT]: This field must be set to the same value (enabled or
671 * disabled) as Hierarchical Depth Buffer Enable
673 bool enable_hiz_ss
= hiz
|| separate_stencil
;
676 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
677 * non-pipelined state that will need the PIPE_CONTROL workaround.
680 intel_emit_post_sync_nonzero_flush(brw
);
681 intel_emit_depth_stall_flushes(brw
);
687 else if (brw
->is_g4x
|| brw
->gen
== 5)
693 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
694 OUT_BATCH((depth_mt
? depth_mt
->region
->pitch
- 1 : 0) |
695 (depthbuffer_format
<< 18) |
696 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
697 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
698 (BRW_TILEWALK_YMAJOR
<< 26) |
699 ((depth_mt
? depth_mt
->region
->tiling
!= I915_TILING_NONE
: 1)
701 (depth_surface_type
<< 29));
704 OUT_RELOC(depth_mt
->region
->bo
,
705 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
711 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
712 ((height
+ tile_y
- 1) << 19));
715 if (brw
->is_g4x
|| brw
->gen
>= 5)
716 OUT_BATCH(tile_x
| (tile_y
<< 16));
718 assert(tile_x
== 0 && tile_y
== 0);
725 if (hiz
|| separate_stencil
) {
727 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
728 * stencil enable' and 'hiz enable' bits were set. Therefore we must
729 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
730 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
731 * failure to do so causes hangs on gen5 and a stall on gen6.
734 /* Emit hiz buffer. */
736 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_mt
;
738 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
739 OUT_BATCH(hiz_mt
->region
->pitch
- 1);
740 OUT_RELOC(hiz_mt
->region
->bo
,
741 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
742 brw
->depthstencil
.hiz_offset
);
746 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
752 /* Emit stencil buffer. */
753 if (separate_stencil
) {
754 struct intel_region
*region
= stencil_mt
->region
;
757 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
758 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
759 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
760 * The pitch must be set to 2x the value computed based on width, as
761 * the stencil buffer is stored with two rows interleaved.
763 OUT_BATCH(2 * region
->pitch
- 1);
764 OUT_RELOC(region
->bo
,
765 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
766 brw
->depthstencil
.stencil_offset
);
770 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
778 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
779 * params must be emitted.
781 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
782 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
783 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
785 if (brw
->gen
>= 6 || hiz
) {
787 intel_emit_post_sync_nonzero_flush(brw
);
790 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
791 GEN5_DEPTH_CLEAR_VALID
|
793 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
798 const struct brw_tracked_state brw_depthbuffer
= {
800 .mesa
= _NEW_BUFFERS
,
801 .brw
= BRW_NEW_BATCH
,
804 .emit
= brw_emit_depthbuffer
,
809 /***********************************************************************
810 * Polygon stipple packet
813 static void upload_polygon_stipple(struct brw_context
*brw
)
815 struct gl_context
*ctx
= &brw
->ctx
;
819 if (!ctx
->Polygon
.StippleFlag
)
823 intel_emit_post_sync_nonzero_flush(brw
);
826 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
828 /* Polygon stipple is provided in OpenGL order, i.e. bottom
829 * row first. If we're rendering to a window (i.e. the
830 * default frame buffer object, 0), then we need to invert
831 * it to match our pixel layout. But if we're rendering
832 * to a FBO (i.e. any named frame buffer object), we *don't*
833 * need to invert - we already match the layout.
835 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
836 for (i
= 0; i
< 32; i
++)
837 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
840 for (i
= 0; i
< 32; i
++)
841 OUT_BATCH(ctx
->PolygonStipple
[i
]);
846 const struct brw_tracked_state brw_polygon_stipple
= {
848 .mesa
= (_NEW_POLYGONSTIPPLE
|
850 .brw
= BRW_NEW_CONTEXT
,
853 .emit
= upload_polygon_stipple
857 /***********************************************************************
858 * Polygon stipple offset packet
861 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
863 struct gl_context
*ctx
= &brw
->ctx
;
866 if (!ctx
->Polygon
.StippleFlag
)
870 intel_emit_post_sync_nonzero_flush(brw
);
873 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
877 * If we're drawing to a system window we have to invert the Y axis
878 * in order to match the OpenGL pixel coordinate system, and our
879 * offset must be matched to the window position. If we're drawing
880 * to a user-created FBO then our native pixel coordinate system
881 * works just fine, and there's no window system to worry about.
883 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
884 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
890 const struct brw_tracked_state brw_polygon_stipple_offset
= {
892 .mesa
= (_NEW_BUFFERS
|
894 .brw
= BRW_NEW_CONTEXT
,
897 .emit
= upload_polygon_stipple_offset
900 /**********************************************************************
903 static void upload_aa_line_parameters(struct brw_context
*brw
)
905 struct gl_context
*ctx
= &brw
->ctx
;
907 if (!ctx
->Line
.SmoothFlag
|| !brw
->has_aa_line_parameters
)
911 intel_emit_post_sync_nonzero_flush(brw
);
913 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
914 /* use legacy aa line coverage computation */
920 const struct brw_tracked_state brw_aa_line_parameters
= {
923 .brw
= BRW_NEW_CONTEXT
,
926 .emit
= upload_aa_line_parameters
929 /***********************************************************************
930 * Line stipple packet
933 static void upload_line_stipple(struct brw_context
*brw
)
935 struct gl_context
*ctx
= &brw
->ctx
;
939 if (!ctx
->Line
.StippleFlag
)
943 intel_emit_post_sync_nonzero_flush(brw
);
946 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
947 OUT_BATCH(ctx
->Line
.StipplePattern
);
951 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
952 tmpi
= tmp
* (1<<16);
953 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
957 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
958 tmpi
= tmp
* (1<<13);
959 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
965 const struct brw_tracked_state brw_line_stipple
= {
968 .brw
= BRW_NEW_CONTEXT
,
971 .emit
= upload_line_stipple
975 /***********************************************************************
976 * Misc invariant state packets
980 brw_upload_invariant_state(struct brw_context
*brw
)
982 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
984 intel_emit_post_sync_nonzero_flush(brw
);
986 /* Select the 3D pipeline (as opposed to media) */
988 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16 | 0);
992 /* Disable depth offset clamping. */
994 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
1000 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
1005 OUT_BATCH(brw
->CMD_VF_STATISTICS
<< 16 |
1006 (unlikely(INTEL_DEBUG
& DEBUG_STATS
) ? 1 : 0));
1010 const struct brw_tracked_state brw_invariant_state
= {
1013 .brw
= BRW_NEW_CONTEXT
,
1016 .emit
= brw_upload_invariant_state
1020 * Define the base addresses which some state is referenced from.
1022 * This allows us to avoid having to emit relocations for the objects,
1023 * and is actually required for binding table pointers on gen6.
1025 * Surface state base address covers binding table pointers and
1026 * surface state objects, but not the surfaces that the surface state
1029 static void upload_state_base_address( struct brw_context
*brw
)
1031 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
1032 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
1033 * programmed prior to STATE_BASE_ADDRESS.
1035 * However, given that the instruction SBA (general state base
1036 * address) on this chipset is always set to 0 across X and GL,
1037 * maybe this isn't required for us in particular.
1040 if (brw
->gen
>= 6) {
1041 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
1044 intel_emit_post_sync_nonzero_flush(brw
);
1047 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
1048 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
1049 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
1050 1); /* General State Base Address Modify Enable */
1051 /* Surface state base address:
1052 * BINDING_TABLE_STATE
1055 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
1056 /* Dynamic state base address:
1058 * SAMPLER_BORDER_COLOR_STATE
1059 * CLIP, SF, WM/CC viewport state
1061 * DEPTH_STENCIL_STATE
1063 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
1064 * Disable is clear, which we rely on)
1066 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
1067 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
1069 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
1070 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1071 1); /* Instruction base address: shader kernels (incl. SIP) */
1073 OUT_BATCH(1); /* General state upper bound */
1074 /* Dynamic state upper bound. Although the documentation says that
1075 * programming it to zero will cause it to be ignored, that is a lie.
1076 * If this isn't programmed to a real bound, the sampler border color
1077 * pointer is rejected, causing border color to mysteriously fail.
1079 OUT_BATCH(0xfffff001);
1080 OUT_BATCH(1); /* Indirect object upper bound */
1081 OUT_BATCH(1); /* Instruction access upper bound */
1083 } else if (brw
->gen
== 5) {
1085 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
1086 OUT_BATCH(1); /* General state base address */
1087 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1088 1); /* Surface state base address */
1089 OUT_BATCH(1); /* Indirect object base address */
1090 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1091 1); /* Instruction base address */
1092 OUT_BATCH(0xfffff001); /* General state upper bound */
1093 OUT_BATCH(1); /* Indirect object upper bound */
1094 OUT_BATCH(1); /* Instruction access upper bound */
1098 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1099 OUT_BATCH(1); /* General state base address */
1100 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1101 1); /* Surface state base address */
1102 OUT_BATCH(1); /* Indirect object base address */
1103 OUT_BATCH(1); /* General state upper bound */
1104 OUT_BATCH(1); /* Indirect object upper bound */
1108 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1109 * STATE_BASE_ADDRESS updates require a reissue of:
1111 * 3DSTATE_PIPELINE_POINTERS
1112 * 3DSTATE_BINDING_TABLE_POINTERS
1113 * MEDIA_STATE_POINTERS
1115 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1116 * 1 part 1 says that the folowing packets must be reissued:
1118 * 3DSTATE_CC_POINTERS
1119 * 3DSTATE_BINDING_TABLE_POINTERS
1120 * 3DSTATE_SAMPLER_STATE_POINTERS
1121 * 3DSTATE_VIEWPORT_STATE_POINTERS
1122 * MEDIA_STATE_POINTERS
1124 * Those are always reissued following SBA updates anyway (new
1125 * batch time), except in the case of the program cache BO
1126 * changing. Having a separate state flag makes the sequence more
1130 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
1133 const struct brw_tracked_state brw_state_base_address
= {
1136 .brw
= (BRW_NEW_BATCH
|
1137 BRW_NEW_PROGRAM_CACHE
),
1140 .emit
= upload_state_base_address