src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "intel_regions.h"
  37
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40 #include "brw_defines.h"
  41
  42 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  43 static void upload_drawing_rect(struct brw_context *brw)
  44 {
  45    struct intel_context *intel = &brw->intel;
  46    struct gl_context *ctx = &intel->ctx;
  47
  48    BEGIN_BATCH(4);
  49    OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
  50    OUT_BATCH(0); /* xmin, ymin */
  51    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  52             ((ctx->DrawBuffer->Height - 1) << 16));
  53    OUT_BATCH(0);
  54    ADVANCE_BATCH();
  55 }
  56
  57 const struct brw_tracked_state brw_drawing_rect = {
  58    .dirty = {
  59       .mesa = _NEW_BUFFERS,
  60       .brw = BRW_NEW_CONTEXT,
  61       .cache = 0
  62    },
  63    .emit = upload_drawing_rect
  64 };
  65
  66 /**
  67  * Upload the binding table pointers, which point each stage's array of surface
  68  * state pointers.
  69  *
  70  * The binding table pointers are relative to the surface state base address,
  71  * which points at the batchbuffer containing the streamed batch state.
  72  */
  73 static void upload_binding_table_pointers(struct brw_context *brw)
  74 {
  75    struct intel_context *intel = &brw->intel;
  76
  77    BEGIN_BATCH(6);
  78    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
  79    OUT_BATCH(brw->vs.bind_bo_offset);
  80    OUT_BATCH(0); /* gs */
  81    OUT_BATCH(0); /* clip */
  82    OUT_BATCH(0); /* sf */
  83    OUT_BATCH(brw->wm.bind_bo_offset);
  84    ADVANCE_BATCH();
  85 }
  86
  87 const struct brw_tracked_state brw_binding_table_pointers = {
  88    .dirty = {
  89       .mesa = 0,
  90       .brw = BRW_NEW_BATCH
  91            | BRW_NEW_VS_BINDING_TABLE
  92            | BRW_NEW_GS_BINDING_TABLE
  93            | BRW_NEW_PS_BINDING_TABLE,
  94       .cache = 0,
  95    },
  96    .emit = upload_binding_table_pointers,
  97 };
  98
  99 /**
 100  * Upload the binding table pointers, which point each stage's array of surface
 101  * state pointers.
 102  *
 103  * The binding table pointers are relative to the surface state base address,
 104  * which points at the batchbuffer containing the streamed batch state.
 105  */
 106 static void upload_gen6_binding_table_pointers(struct brw_context *brw)
 107 {
 108    struct intel_context *intel = &brw->intel;
 109
 110    BEGIN_BATCH(4);
 111    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 112              GEN6_BINDING_TABLE_MODIFY_VS |
 113              GEN6_BINDING_TABLE_MODIFY_GS |
 114              GEN6_BINDING_TABLE_MODIFY_PS |
 115              (4 - 2));
 116    OUT_BATCH(brw->vs.bind_bo_offset); /* vs */
 117    OUT_BATCH(0); /* gs */
 118    OUT_BATCH(brw->wm.bind_bo_offset); /* wm/ps */
 119    ADVANCE_BATCH();
 120 }
 121
 122 const struct brw_tracked_state gen6_binding_table_pointers = {
 123    .dirty = {
 124       .mesa = 0,
 125       .brw = BRW_NEW_BATCH
 126            | BRW_NEW_VS_BINDING_TABLE
 127            | BRW_NEW_GS_BINDING_TABLE
 128            | BRW_NEW_PS_BINDING_TABLE,
 129       .cache = 0,
 130    },
 131    .emit = upload_gen6_binding_table_pointers,
 132 };
 133
 134 /**
 135  * Upload pointers to the per-stage state.
 136  *
 137  * The state pointers in this packet are all relative to the general state
 138  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 139  */
 140 static void upload_pipelined_state_pointers(struct brw_context *brw )
 141 {
 142    struct intel_context *intel = &brw->intel;
 143
 144    if (intel->gen == 5) {
 145       /* Need to flush before changing clip max threads for errata. */
 146       BEGIN_BATCH(1);
 147       OUT_BATCH(MI_FLUSH);
 148       ADVANCE_BATCH();
 149    }
 150
 151    BEGIN_BATCH(7);
 152    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
 153    OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 154              brw->vs.state_offset);
 155    if (brw->gs.prog_active)
 156       OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 157                 brw->gs.state_offset | 1);
 158    else
 159       OUT_BATCH(0);
 160    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 161              brw->clip.state_offset | 1);
 162    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 163              brw->sf.state_offset);
 164    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 165              brw->wm.state_offset);
 166    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 167              brw->cc.state_offset);
 168    ADVANCE_BATCH();
 169
 170    brw->state.dirty.brw |= BRW_NEW_PSP;
 171 }
 172
 173 static void upload_psp_urb_cbs(struct brw_context *brw )
 174 {
 175    upload_pipelined_state_pointers(brw);
 176    brw_upload_urb_fence(brw);
 177    brw_upload_cs_urb_state(brw);
 178 }
 179
 180 const struct brw_tracked_state brw_psp_urb_cbs = {
 181    .dirty = {
 182       .mesa = 0,
 183       .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH,
 184       .cache = (CACHE_NEW_VS_UNIT |
 185                 CACHE_NEW_GS_UNIT |
 186                 CACHE_NEW_GS_PROG |
 187                 CACHE_NEW_CLIP_UNIT |
 188                 CACHE_NEW_SF_UNIT |
 189                 CACHE_NEW_WM_UNIT |
 190                 CACHE_NEW_CC_UNIT)
 191    },
 192    .emit = upload_psp_urb_cbs,
 193 };
 194
 195 static void prepare_depthbuffer(struct brw_context *brw)
 196 {
 197    struct intel_context *intel = &brw->intel;
 198    struct gl_context *ctx = &intel->ctx;
 199    struct gl_framebuffer *fb = ctx->DrawBuffer;
 200    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 201    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 202
 203    if (drb)
 204       brw_add_validated_bo(brw, drb->region->buffer);
 205    if (drb && drb->hiz_region)
 206       brw_add_validated_bo(brw, drb->hiz_region->buffer);
 207    if (srb)
 208       brw_add_validated_bo(brw, srb->region->buffer);
 209 }
 210
 211 static void emit_depthbuffer(struct brw_context *brw)
 212 {
 213    struct intel_context *intel = &brw->intel;
 214    struct gl_context *ctx = &intel->ctx;
 215    struct gl_framebuffer *fb = ctx->DrawBuffer;
 216    /* _NEW_BUFFERS */
 217    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 218    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 219    struct intel_region *hiz_region = depth_irb ? depth_irb->hiz_region : NULL;
 220    unsigned int len;
 221
 222    /*
 223     * If either depth or stencil buffer has packed depth/stencil format,
 224     * then don't use separate stencil. Emit only a depth buffer.
 225     */
 226    if (depth_irb && depth_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 227       stencil_irb = NULL;
 228    } else if (!depth_irb && stencil_irb
 229               && stencil_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 230       depth_irb = stencil_irb;
 231       stencil_irb = NULL;
 232    }
 233
 234    if (intel->gen >= 6)
 235       len = 7;
 236    else if (intel->is_g4x || intel->gen == 5)
 237       len = 6;
 238    else
 239       len = 5;
 240
 241    if (!depth_irb && !stencil_irb) {
 242       BEGIN_BATCH(len);
 243       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 244       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 245                 (BRW_SURFACE_NULL << 29));
 246       OUT_BATCH(0);
 247       OUT_BATCH(0);
 248       OUT_BATCH(0);
 249
 250       if (intel->is_g4x || intel->gen >= 5)
 251          OUT_BATCH(0);
 252
 253       if (intel->gen >= 6)
 254          OUT_BATCH(0);
 255
 256       ADVANCE_BATCH();
 257
 258    } else if (!depth_irb && stencil_irb) {
 259       /*
 260        * There exists a separate stencil buffer but no depth buffer.
 261        *
 262        * The stencil buffer inherits most of its fields from
 263        * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
 264        * height.
 265        *
 266        * Since the stencil buffer has quirky pitch requirements, its region
 267        * was allocated with half height and double cpp. So we need
 268        * a multiplier of 2 to obtain the surface's real height.
 269        *
 270        * Enable the hiz bit because it and the separate stencil bit must have
 271        * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
 272        * 1.21 "Separate Stencil Enable":
 273        *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
 274        *     Enable must also be enabled.
 275        *
 276        *     [DevGT]: This field must be set to the same value (enabled or
 277        *     disabled) as Hierarchical Depth Buffer Enable
 278        */
 279       assert(intel->has_separate_stencil);
 280       assert(stencil_irb->Base.Format == MESA_FORMAT_S8);
 281
 282       BEGIN_BATCH(len);
 283       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 284       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 285                 (1 << 21) | /* separate stencil enable */
 286                 (1 << 22) | /* hiz enable */
 287                 (BRW_TILEWALK_YMAJOR << 26) |
 288                 (BRW_SURFACE_2D << 29));
 289       OUT_BATCH(0);
 290       OUT_BATCH(((stencil_irb->region->width - 1) << 6) |
 291                  (2 * stencil_irb->region->height - 1) << 19);
 292       OUT_BATCH(0);
 293       OUT_BATCH(0);
 294
 295       if (intel->gen >= 6)
 296          OUT_BATCH(0);
 297
 298       ADVANCE_BATCH();
 299
 300    } else {
 301       struct intel_region *region = depth_irb->region;
 302       unsigned int format;
 303       uint32_t tile_x, tile_y, offset;
 304
 305       /* If using separate stencil, hiz must be enabled. */
 306       assert(!stencil_irb || hiz_region);
 307
 308       switch (region->cpp) {
 309       case 2:
 310          format = BRW_DEPTHFORMAT_D16_UNORM;
 311          break;
 312       case 4:
 313          if (intel->depth_buffer_is_float)
 314             format = BRW_DEPTHFORMAT_D32_FLOAT;
 315          else if (hiz_region)
 316             format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 317          else
 318             format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 319          break;
 320       default:
 321          assert(0);
 322          return;
 323       }
 324
 325       offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y);
 326
 327       assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
 328       assert(!hiz_region || region->tiling == I915_TILING_Y);
 329
 330       BEGIN_BATCH(len);
 331       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 332       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 333                 (format << 18) |
 334                 ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */
 335                 ((hiz_region ? 1 : 0) << 22) | /* hiz enable */
 336                 (BRW_TILEWALK_YMAJOR << 26) |
 337                 ((region->tiling != I915_TILING_NONE) << 27) |
 338                 (BRW_SURFACE_2D << 29));
 339       OUT_RELOC(region->buffer,
 340                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 341                 offset);
 342       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 343                 ((region->width - 1) << 6) |
 344                 ((region->height - 1) << 19));
 345       OUT_BATCH(0);
 346
 347       if (intel->is_g4x || intel->gen >= 5)
 348          OUT_BATCH(tile_x | (tile_y << 16));
 349       else
 350          assert(tile_x == 0 && tile_y == 0);
 351
 352       if (intel->gen >= 6)
 353          OUT_BATCH(0);
 354
 355       ADVANCE_BATCH();
 356    }
 357
 358    if (hiz_region || stencil_irb) {
 359       /*
 360        * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
 361        * stencil enable' and 'hiz enable' bits were set. Therefore we must
 362        * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
 363        * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
 364        * failure to do so causes hangs on gen5 and a stall on gen6.
 365        */
 366
 367       /* Emit hiz buffer. */
 368       if (hiz_region) {
 369          BEGIN_BATCH(3);
 370          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 371          OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 372          OUT_RELOC(hiz_region->buffer,
 373                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 374                    0);
 375          ADVANCE_BATCH();
 376       } else {
 377          BEGIN_BATCH(3);
 378          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 379          OUT_BATCH(0);
 380          OUT_BATCH(0);
 381          ADVANCE_BATCH();
 382       }
 383
 384       /* Emit stencil buffer. */
 385       if (stencil_irb) {
 386          BEGIN_BATCH(3);
 387          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 388          OUT_BATCH(stencil_irb->region->pitch * stencil_irb->region->cpp - 1);
 389          OUT_RELOC(stencil_irb->region->buffer,
 390                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 391                    0);
 392          ADVANCE_BATCH();
 393       } else {
 394          BEGIN_BATCH(3);
 395          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 396          OUT_BATCH(0);
 397          OUT_BATCH(0);
 398          ADVANCE_BATCH();
 399       }
 400    }
 401
 402    /*
 403     * On Gen >= 6, emit clear params for safety. If using hiz, then clear
 404     * params must be emitted.
 405     *
 406     * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
 407     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
 408     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 409     */
 410    if (intel->gen >= 6 || hiz_region) {
 411       BEGIN_BATCH(2);
 412       OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
 413       OUT_BATCH(0);
 414       ADVANCE_BATCH();
 415    }
 416 }
 417
 418 const struct brw_tracked_state brw_depthbuffer = {
 419    .dirty = {
 420       .mesa = _NEW_BUFFERS,
 421       .brw = BRW_NEW_BATCH,
 422       .cache = 0,
 423    },
 424    .prepare = prepare_depthbuffer,
 425    .emit = emit_depthbuffer,
 426 };
 427
 428
 429
 430 /***********************************************************************
 431  * Polygon stipple packet
 432  */
 433
 434 static void upload_polygon_stipple(struct brw_context *brw)
 435 {
 436    struct intel_context *intel = &brw->intel;
 437    struct gl_context *ctx = &brw->intel.ctx;
 438    GLuint i;
 439
 440    if (!ctx->Polygon.StippleFlag)
 441       return;
 442
 443    BEGIN_BATCH(33);
 444    OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
 445
 446    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 447     * row first.  If we're rendering to a window (i.e. the
 448     * default frame buffer object, 0), then we need to invert
 449     * it to match our pixel layout.  But if we're rendering
 450     * to a FBO (i.e. any named frame buffer object), we *don't*
 451     * need to invert - we already match the layout.
 452     */
 453    if (ctx->DrawBuffer->Name == 0) {
 454       for (i = 0; i < 32; i++)
 455           OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
 456    }
 457    else {
 458       for (i = 0; i < 32; i++)
 459          OUT_BATCH(ctx->PolygonStipple[i]);
 460    }
 461    CACHED_BATCH();
 462 }
 463
 464 const struct brw_tracked_state brw_polygon_stipple = {
 465    .dirty = {
 466       .mesa = _NEW_POLYGONSTIPPLE,
 467       .brw = BRW_NEW_CONTEXT,
 468       .cache = 0
 469    },
 470    .emit = upload_polygon_stipple
 471 };
 472
 473
 474 /***********************************************************************
 475  * Polygon stipple offset packet
 476  */
 477
 478 static void upload_polygon_stipple_offset(struct brw_context *brw)
 479 {
 480    struct intel_context *intel = &brw->intel;
 481    struct gl_context *ctx = &brw->intel.ctx;
 482
 483    if (!ctx->Polygon.StippleFlag)
 484       return;
 485
 486    BEGIN_BATCH(2);
 487    OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
 488
 489    /* If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 490     * we have to invert the Y axis in order to match the OpenGL
 491     * pixel coordinate system, and our offset must be matched
 492     * to the window position.  If we're drawing to a FBO
 493     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 494     * system works just fine, and there's no window system to
 495     * worry about.
 496     */
 497    if (brw->intel.ctx.DrawBuffer->Name == 0)
 498       OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
 499    else
 500       OUT_BATCH(0);
 501    CACHED_BATCH();
 502 }
 503
 504 #define _NEW_WINDOW_POS 0x40000000
 505
 506 const struct brw_tracked_state brw_polygon_stipple_offset = {
 507    .dirty = {
 508       .mesa = _NEW_WINDOW_POS | _NEW_POLYGONSTIPPLE,
 509       .brw = BRW_NEW_CONTEXT,
 510       .cache = 0
 511    },
 512    .emit = upload_polygon_stipple_offset
 513 };
 514
 515 /**********************************************************************
 516  * AA Line parameters
 517  */
 518 static void upload_aa_line_parameters(struct brw_context *brw)
 519 {
 520    struct intel_context *intel = &brw->intel;
 521    struct gl_context *ctx = &brw->intel.ctx;
 522
 523    if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
 524       return;
 525
 526    OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
 527    /* use legacy aa line coverage computation */
 528    OUT_BATCH(0);
 529    OUT_BATCH(0);
 530    CACHED_BATCH();
 531 }
 532
 533 const struct brw_tracked_state brw_aa_line_parameters = {
 534    .dirty = {
 535       .mesa = _NEW_LINE,
 536       .brw = BRW_NEW_CONTEXT,
 537       .cache = 0
 538    },
 539    .emit = upload_aa_line_parameters
 540 };
 541
 542 /***********************************************************************
 543  * Line stipple packet
 544  */
 545
 546 static void upload_line_stipple(struct brw_context *brw)
 547 {
 548    struct intel_context *intel = &brw->intel;
 549    struct gl_context *ctx = &brw->intel.ctx;
 550    GLfloat tmp;
 551    GLint tmpi;
 552
 553    if (!ctx->Line.StippleFlag)
 554       return;
 555
 556    BEGIN_BATCH(3);
 557    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
 558    OUT_BATCH(ctx->Line.StipplePattern);
 559    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 560    tmpi = tmp * (1<<13);
 561    OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
 562    CACHED_BATCH();
 563 }
 564
 565 const struct brw_tracked_state brw_line_stipple = {
 566    .dirty = {
 567       .mesa = _NEW_LINE,
 568       .brw = BRW_NEW_CONTEXT,
 569       .cache = 0
 570    },
 571    .emit = upload_line_stipple
 572 };
 573
 574
 575 /***********************************************************************
 576  * Misc invarient state packets
 577  */
 578
 579 static void upload_invarient_state( struct brw_context *brw )
 580 {
 581    struct intel_context *intel = &brw->intel;
 582
 583    {
 584       /* 0x61040000  Pipeline Select */
 585       /*     PipelineSelect            : 0 */
 586       struct brw_pipeline_select ps;
 587
 588       memset(&ps, 0, sizeof(ps));
 589       ps.header.opcode = brw->CMD_PIPELINE_SELECT;
 590       ps.header.pipeline_select = 0;
 591       BRW_BATCH_STRUCT(brw, &ps);
 592    }
 593
 594    if (intel->gen < 6) {
 595       struct brw_global_depth_offset_clamp gdo;
 596       memset(&gdo, 0, sizeof(gdo));
 597
 598       /* Disable depth offset clamping.
 599        */
 600       gdo.header.opcode = _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP;
 601       gdo.header.length = sizeof(gdo)/4 - 2;
 602       gdo.depth_offset_clamp = 0.0;
 603
 604       BRW_BATCH_STRUCT(brw, &gdo);
 605    }
 606
 607    if (intel->gen >= 6) {
 608       int i;
 609       int len = intel->gen >= 7 ? 4 : 3;
 610
 611       BEGIN_BATCH(len);
 612       OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
 613       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
 614                 MS_NUMSAMPLES_1);
 615       OUT_BATCH(0); /* positions for 4/8-sample */
 616       if (intel->gen >= 7)
 617          OUT_BATCH(0);
 618       ADVANCE_BATCH();
 619
 620       BEGIN_BATCH(2);
 621       OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
 622       OUT_BATCH(1);
 623       ADVANCE_BATCH();
 624
 625       if (intel->gen < 7) {
 626          for (i = 0; i < 4; i++) {
 627             BEGIN_BATCH(4);
 628             OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
 629             OUT_BATCH(i << SVB_INDEX_SHIFT);
 630             OUT_BATCH(0);
 631             OUT_BATCH(0xffffffff);
 632             ADVANCE_BATCH();
 633          }
 634       }
 635    }
 636
 637    /* 0x61020000  State Instruction Pointer */
 638    {
 639       struct brw_system_instruction_pointer sip;
 640       memset(&sip, 0, sizeof(sip));
 641
 642       sip.header.opcode = CMD_STATE_INSN_POINTER;
 643       sip.header.length = 0;
 644       sip.bits0.pad = 0;
 645       sip.bits0.system_instruction_pointer = 0;
 646       BRW_BATCH_STRUCT(brw, &sip);
 647    }
 648
 649
 650    {
 651       struct brw_vf_statistics vfs;
 652       memset(&vfs, 0, sizeof(vfs));
 653
 654       vfs.opcode = brw->CMD_VF_STATISTICS;
 655       if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 656          vfs.statistics_enable = 1;
 657
 658       BRW_BATCH_STRUCT(brw, &vfs);
 659    }
 660 }
 661
 662 const struct brw_tracked_state brw_invarient_state = {
 663    .dirty = {
 664       .mesa = 0,
 665       .brw = BRW_NEW_CONTEXT,
 666       .cache = 0
 667    },
 668    .emit = upload_invarient_state
 669 };
 670
 671 /**
 672  * Define the base addresses which some state is referenced from.
 673  *
 674  * This allows us to avoid having to emit relocations for the objects,
 675  * and is actually required for binding table pointers on gen6.
 676  *
 677  * Surface state base address covers binding table pointers and
 678  * surface state objects, but not the surfaces that the surface state
 679  * objects point to.
 680  */
 681 static void upload_state_base_address( struct brw_context *brw )
 682 {
 683    struct intel_context *intel = &brw->intel;
 684
 685    if (intel->gen >= 6) {
 686        BEGIN_BATCH(10);
 687        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
 688        /* General state base address: stateless DP read/write requests */
 689        OUT_BATCH(1);
 690        /* Surface state base address:
 691         * BINDING_TABLE_STATE
 692         * SURFACE_STATE
 693         */
 694        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
 695         /* Dynamic state base address:
 696          * SAMPLER_STATE
 697          * SAMPLER_BORDER_COLOR_STATE
 698          * CLIP, SF, WM/CC viewport state
 699          * COLOR_CALC_STATE
 700          * DEPTH_STENCIL_STATE
 701          * BLEND_STATE
 702          * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
 703          * Disable is clear, which we rely on)
 704          */
 705        OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
 706                                    I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
 707
 708        OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
 709        OUT_BATCH(1); /* Instruction base address: shader kernels (incl. SIP) */
 710        OUT_BATCH(1); /* General state upper bound */
 711        OUT_BATCH(1); /* Dynamic state upper bound */
 712        OUT_BATCH(1); /* Indirect object upper bound */
 713        OUT_BATCH(1); /* Instruction access upper bound */
 714        ADVANCE_BATCH();
 715    } else if (intel->gen == 5) {
 716        BEGIN_BATCH(8);
 717        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 718        OUT_BATCH(1); /* General state base address */
 719        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 720                  1); /* Surface state base address */
 721        OUT_BATCH(1); /* Indirect object base address */
 722        OUT_BATCH(1); /* Instruction base address */
 723        OUT_BATCH(1); /* General state upper bound */
 724        OUT_BATCH(1); /* Indirect object upper bound */
 725        OUT_BATCH(1); /* Instruction access upper bound */
 726        ADVANCE_BATCH();
 727    } else {
 728        BEGIN_BATCH(6);
 729        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 730        OUT_BATCH(1); /* General state base address */
 731        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 732                  1); /* Surface state base address */
 733        OUT_BATCH(1); /* Indirect object base address */
 734        OUT_BATCH(1); /* General state upper bound */
 735        OUT_BATCH(1); /* Indirect object upper bound */
 736        ADVANCE_BATCH();
 737    }
 738 }
 739
 740 const struct brw_tracked_state brw_state_base_address = {
 741    .dirty = {
 742       .mesa = 0,
 743       .brw = BRW_NEW_BATCH,
 744       .cache = 0,
 745    },
 746    .emit = upload_state_base_address
 747 };