src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "intel_mipmap_tree.h"
  37 #include "intel_regions.h"
  38
  39 #include "brw_context.h"
  40 #include "brw_state.h"
  41 #include "brw_defines.h"
  42
  43 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  44 static void upload_drawing_rect(struct brw_context *brw)
  45 {
  46    struct intel_context *intel = &brw->intel;
  47    struct gl_context *ctx = &intel->ctx;
  48
  49    BEGIN_BATCH(4);
  50    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
  51    OUT_BATCH(0); /* xmin, ymin */
  52    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  53             ((ctx->DrawBuffer->Height - 1) << 16));
  54    OUT_BATCH(0);
  55    ADVANCE_BATCH();
  56 }
  57
  58 const struct brw_tracked_state brw_drawing_rect = {
  59    .dirty = {
  60       .mesa = _NEW_BUFFERS,
  61       .brw = BRW_NEW_CONTEXT,
  62       .cache = 0
  63    },
  64    .emit = upload_drawing_rect
  65 };
  66
  67 /**
  68  * Upload the binding table pointers, which point each stage's array of surface
  69  * state pointers.
  70  *
  71  * The binding table pointers are relative to the surface state base address,
  72  * which points at the batchbuffer containing the streamed batch state.
  73  */
  74 static void upload_binding_table_pointers(struct brw_context *brw)
  75 {
  76    struct intel_context *intel = &brw->intel;
  77
  78    BEGIN_BATCH(6);
  79    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
  80    OUT_BATCH(brw->bind.bo_offset);
  81    OUT_BATCH(0); /* gs */
  82    OUT_BATCH(0); /* clip */
  83    OUT_BATCH(0); /* sf */
  84    OUT_BATCH(brw->bind.bo_offset);
  85    ADVANCE_BATCH();
  86 }
  87
  88 const struct brw_tracked_state brw_binding_table_pointers = {
  89    .dirty = {
  90       .mesa = 0,
  91       .brw = (BRW_NEW_BATCH |
  92               BRW_NEW_STATE_BASE_ADDRESS |
  93               BRW_NEW_VS_BINDING_TABLE |
  94               BRW_NEW_GS_BINDING_TABLE |
  95               BRW_NEW_PS_BINDING_TABLE),
  96       .cache = 0,
  97    },
  98    .emit = upload_binding_table_pointers,
  99 };
 100
 101 /**
 102  * Upload the binding table pointers, which point each stage's array of surface
 103  * state pointers.
 104  *
 105  * The binding table pointers are relative to the surface state base address,
 106  * which points at the batchbuffer containing the streamed batch state.
 107  */
 108 static void upload_gen6_binding_table_pointers(struct brw_context *brw)
 109 {
 110    struct intel_context *intel = &brw->intel;
 111
 112    BEGIN_BATCH(4);
 113    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 114              GEN6_BINDING_TABLE_MODIFY_VS |
 115              GEN6_BINDING_TABLE_MODIFY_GS |
 116              GEN6_BINDING_TABLE_MODIFY_PS |
 117              (4 - 2));
 118    OUT_BATCH(brw->bind.bo_offset); /* vs */
 119    OUT_BATCH(0); /* gs */
 120    OUT_BATCH(brw->bind.bo_offset); /* wm/ps */
 121    ADVANCE_BATCH();
 122 }
 123
 124 const struct brw_tracked_state gen6_binding_table_pointers = {
 125    .dirty = {
 126       .mesa = 0,
 127       .brw = (BRW_NEW_BATCH |
 128               BRW_NEW_STATE_BASE_ADDRESS |
 129               BRW_NEW_VS_BINDING_TABLE |
 130               BRW_NEW_GS_BINDING_TABLE |
 131               BRW_NEW_PS_BINDING_TABLE),
 132       .cache = 0,
 133    },
 134    .emit = upload_gen6_binding_table_pointers,
 135 };
 136
 137 /**
 138  * Upload pointers to the per-stage state.
 139  *
 140  * The state pointers in this packet are all relative to the general state
 141  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 142  */
 143 static void upload_pipelined_state_pointers(struct brw_context *brw )
 144 {
 145    struct intel_context *intel = &brw->intel;
 146
 147    if (intel->gen == 5) {
 148       /* Need to flush before changing clip max threads for errata. */
 149       BEGIN_BATCH(1);
 150       OUT_BATCH(MI_FLUSH);
 151       ADVANCE_BATCH();
 152    }
 153
 154    BEGIN_BATCH(7);
 155    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
 156    OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 157              brw->vs.state_offset);
 158    if (brw->gs.prog_active)
 159       OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 160                 brw->gs.state_offset | 1);
 161    else
 162       OUT_BATCH(0);
 163    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 164              brw->clip.state_offset | 1);
 165    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 166              brw->sf.state_offset);
 167    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 168              brw->wm.state_offset);
 169    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 170              brw->cc.state_offset);
 171    ADVANCE_BATCH();
 172
 173    brw->state.dirty.brw |= BRW_NEW_PSP;
 174 }
 175
 176 static void upload_psp_urb_cbs(struct brw_context *brw )
 177 {
 178    upload_pipelined_state_pointers(brw);
 179    brw_upload_urb_fence(brw);
 180    brw_upload_cs_urb_state(brw);
 181 }
 182
 183 const struct brw_tracked_state brw_psp_urb_cbs = {
 184    .dirty = {
 185       .mesa = 0,
 186       .brw = (BRW_NEW_URB_FENCE |
 187               BRW_NEW_BATCH |
 188               BRW_NEW_STATE_BASE_ADDRESS),
 189       .cache = (CACHE_NEW_VS_UNIT |
 190                 CACHE_NEW_GS_UNIT |
 191                 CACHE_NEW_GS_PROG |
 192                 CACHE_NEW_CLIP_UNIT |
 193                 CACHE_NEW_SF_UNIT |
 194                 CACHE_NEW_WM_UNIT |
 195                 CACHE_NEW_CC_UNIT)
 196    },
 197    .emit = upload_psp_urb_cbs,
 198 };
 199
 200 uint32_t
 201 brw_depthbuffer_format(struct brw_context *brw)
 202 {
 203    struct intel_context *intel = &brw->intel;
 204    struct gl_context *ctx = &intel->ctx;
 205    struct gl_framebuffer *fb = ctx->DrawBuffer;
 206    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 207    struct intel_renderbuffer *srb;
 208
 209    if (!drb &&
 210        (srb = intel_get_renderbuffer(fb, BUFFER_STENCIL)) &&
 211        srb->Base.Format == MESA_FORMAT_S8_Z24) {
 212       drb = srb;
 213    }
 214
 215    if (!drb)
 216       return BRW_DEPTHFORMAT_D32_FLOAT;
 217
 218    switch (drb->Base.Format) {
 219    case MESA_FORMAT_Z16:
 220       return BRW_DEPTHFORMAT_D16_UNORM;
 221    case MESA_FORMAT_Z32_FLOAT:
 222       return BRW_DEPTHFORMAT_D32_FLOAT;
 223    case MESA_FORMAT_X8_Z24:
 224       return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 225    case MESA_FORMAT_S8_Z24:
 226       return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 227    default:
 228       _mesa_problem(ctx, "Unexpected depth format %s\n",
 229                     _mesa_get_format_name(drb->Base.Format));
 230       return BRW_DEPTHFORMAT_D16_UNORM;
 231    }
 232 }
 233
 234 static void emit_depthbuffer(struct brw_context *brw)
 235 {
 236    struct intel_context *intel = &brw->intel;
 237    struct gl_context *ctx = &intel->ctx;
 238    struct gl_framebuffer *fb = ctx->DrawBuffer;
 239    /* _NEW_BUFFERS */
 240    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 241    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 242    struct intel_region *hiz_region = NULL;
 243    unsigned int len;
 244
 245    if (depth_irb &&
 246        depth_irb->mt &&
 247        depth_irb->mt->hiz_mt) {
 248       hiz_region = depth_irb->mt->hiz_mt->region;
 249    }
 250
 251    /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
 252     * non-pipelined state that will need the PIPE_CONTROL workaround.
 253     */
 254    if (intel->gen == 6) {
 255       intel_emit_post_sync_nonzero_flush(intel);
 256       intel_emit_depth_stall_flushes(intel);
 257    }
 258
 259    /*
 260     * If either depth or stencil buffer has packed depth/stencil format,
 261     * then don't use separate stencil. Emit only a depth buffer.
 262     */
 263    if (depth_irb && depth_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 264       stencil_irb = NULL;
 265    } else if (!depth_irb && stencil_irb
 266               && stencil_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 267       depth_irb = stencil_irb;
 268       stencil_irb = NULL;
 269    }
 270
 271    if (intel->gen >= 6)
 272       len = 7;
 273    else if (intel->is_g4x || intel->gen == 5)
 274       len = 6;
 275    else
 276       len = 5;
 277
 278    if (!depth_irb && !stencil_irb) {
 279       BEGIN_BATCH(len);
 280       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 281       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 282                 (BRW_SURFACE_NULL << 29));
 283       OUT_BATCH(0);
 284       OUT_BATCH(0);
 285       OUT_BATCH(0);
 286
 287       if (intel->is_g4x || intel->gen >= 5)
 288          OUT_BATCH(0);
 289
 290       if (intel->gen >= 6)
 291          OUT_BATCH(0);
 292
 293       ADVANCE_BATCH();
 294
 295    } else if (!depth_irb && stencil_irb) {
 296       /*
 297        * There exists a separate stencil buffer but no depth buffer.
 298        *
 299        * The stencil buffer inherits most of its fields from
 300        * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
 301        * height.
 302        *
 303        * Since the stencil buffer has quirky pitch requirements, its region
 304        * was allocated with half height and double cpp. So we need
 305        * a multiplier of 2 to obtain the surface's real height.
 306        *
 307        * Enable the hiz bit because it and the separate stencil bit must have
 308        * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
 309        * 1.21 "Separate Stencil Enable":
 310        *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
 311        *     Enable must also be enabled.
 312        *
 313        *     [DevGT]: This field must be set to the same value (enabled or
 314        *     disabled) as Hierarchical Depth Buffer Enable
 315        *
 316        * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
 317        * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
 318        *     [DevGT+]: This field must be set to TRUE.
 319        */
 320       struct intel_region *region = stencil_irb->mt->region;
 321
 322       assert(intel->has_separate_stencil);
 323       assert(stencil_irb->Base.Format == MESA_FORMAT_S8);
 324
 325       BEGIN_BATCH(len);
 326       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 327       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 328                 (1 << 21) | /* separate stencil enable */
 329                 (1 << 22) | /* hiz enable */
 330                 (BRW_TILEWALK_YMAJOR << 26) |
 331                 (1 << 27) | /* tiled surface */
 332                 (BRW_SURFACE_2D << 29));
 333       OUT_BATCH(0);
 334       OUT_BATCH(((region->width - 1) << 6) |
 335                  (2 * region->height - 1) << 19);
 336       OUT_BATCH(0);
 337       OUT_BATCH(0);
 338
 339       if (intel->gen >= 6)
 340          OUT_BATCH(0);
 341
 342       ADVANCE_BATCH();
 343
 344    } else {
 345       struct intel_region *region = depth_irb->mt->region;
 346       uint32_t tile_x, tile_y, offset;
 347
 348       /* If using separate stencil, hiz must be enabled. */
 349       assert(!stencil_irb || hiz_region);
 350
 351       offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y);
 352
 353       assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
 354       assert(!hiz_region || region->tiling == I915_TILING_Y);
 355
 356       BEGIN_BATCH(len);
 357       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 358       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 359                 (brw_depthbuffer_format(brw) << 18) |
 360                 ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */
 361                 ((hiz_region ? 1 : 0) << 22) | /* hiz enable */
 362                 (BRW_TILEWALK_YMAJOR << 26) |
 363                 ((region->tiling != I915_TILING_NONE) << 27) |
 364                 (BRW_SURFACE_2D << 29));
 365       OUT_RELOC(region->bo,
 366                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 367                 offset);
 368       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 369                 ((region->width - 1) << 6) |
 370                 ((region->height - 1) << 19));
 371       OUT_BATCH(0);
 372
 373       if (intel->is_g4x || intel->gen >= 5)
 374          OUT_BATCH(tile_x | (tile_y << 16));
 375       else
 376          assert(tile_x == 0 && tile_y == 0);
 377
 378       if (intel->gen >= 6)
 379          OUT_BATCH(0);
 380
 381       ADVANCE_BATCH();
 382    }
 383
 384    if (hiz_region || stencil_irb) {
 385       /*
 386        * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
 387        * stencil enable' and 'hiz enable' bits were set. Therefore we must
 388        * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
 389        * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
 390        * failure to do so causes hangs on gen5 and a stall on gen6.
 391        */
 392
 393       /* Emit hiz buffer. */
 394       if (hiz_region) {
 395          BEGIN_BATCH(3);
 396          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 397          OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 398          OUT_RELOC(hiz_region->bo,
 399                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 400                    0);
 401          ADVANCE_BATCH();
 402       } else {
 403          BEGIN_BATCH(3);
 404          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 405          OUT_BATCH(0);
 406          OUT_BATCH(0);
 407          ADVANCE_BATCH();
 408       }
 409
 410       /* Emit stencil buffer. */
 411       if (stencil_irb) {
 412          struct intel_region *region = stencil_irb->mt->region;
 413          BEGIN_BATCH(3);
 414          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 415          OUT_BATCH(region->pitch * region->cpp - 1);
 416          OUT_RELOC(region->bo,
 417                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 418                    0);
 419          ADVANCE_BATCH();
 420       } else {
 421          BEGIN_BATCH(3);
 422          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 423          OUT_BATCH(0);
 424          OUT_BATCH(0);
 425          ADVANCE_BATCH();
 426       }
 427    }
 428
 429    /*
 430     * On Gen >= 6, emit clear params for safety. If using hiz, then clear
 431     * params must be emitted.
 432     *
 433     * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
 434     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
 435     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 436     */
 437    if (intel->gen >= 6 || hiz_region) {
 438       if (intel->gen == 6)
 439          intel_emit_post_sync_nonzero_flush(intel);
 440
 441       BEGIN_BATCH(2);
 442       OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
 443       OUT_BATCH(0);
 444       ADVANCE_BATCH();
 445    }
 446 }
 447
 448 const struct brw_tracked_state brw_depthbuffer = {
 449    .dirty = {
 450       .mesa = _NEW_BUFFERS,
 451       .brw = BRW_NEW_BATCH,
 452       .cache = 0,
 453    },
 454    .emit = emit_depthbuffer,
 455 };
 456
 457
 458
 459 /***********************************************************************
 460  * Polygon stipple packet
 461  */
 462
 463 static void upload_polygon_stipple(struct brw_context *brw)
 464 {
 465    struct intel_context *intel = &brw->intel;
 466    struct gl_context *ctx = &brw->intel.ctx;
 467    GLuint i;
 468
 469    /* _NEW_POLYGON */
 470    if (!ctx->Polygon.StippleFlag)
 471       return;
 472
 473    if (intel->gen == 6)
 474       intel_emit_post_sync_nonzero_flush(intel);
 475
 476    BEGIN_BATCH(33);
 477    OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
 478
 479    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 480     * row first.  If we're rendering to a window (i.e. the
 481     * default frame buffer object, 0), then we need to invert
 482     * it to match our pixel layout.  But if we're rendering
 483     * to a FBO (i.e. any named frame buffer object), we *don't*
 484     * need to invert - we already match the layout.
 485     */
 486    if (ctx->DrawBuffer->Name == 0) {
 487       for (i = 0; i < 32; i++)
 488           OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
 489    }
 490    else {
 491       for (i = 0; i < 32; i++)
 492          OUT_BATCH(ctx->PolygonStipple[i]);
 493    }
 494    CACHED_BATCH();
 495 }
 496
 497 const struct brw_tracked_state brw_polygon_stipple = {
 498    .dirty = {
 499       .mesa = (_NEW_POLYGONSTIPPLE |
 500                _NEW_POLYGON),
 501       .brw = BRW_NEW_CONTEXT,
 502       .cache = 0
 503    },
 504    .emit = upload_polygon_stipple
 505 };
 506
 507
 508 /***********************************************************************
 509  * Polygon stipple offset packet
 510  */
 511
 512 static void upload_polygon_stipple_offset(struct brw_context *brw)
 513 {
 514    struct intel_context *intel = &brw->intel;
 515    struct gl_context *ctx = &brw->intel.ctx;
 516
 517    /* _NEW_POLYGON */
 518    if (!ctx->Polygon.StippleFlag)
 519       return;
 520
 521    if (intel->gen == 6)
 522       intel_emit_post_sync_nonzero_flush(intel);
 523
 524    BEGIN_BATCH(2);
 525    OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
 526
 527    /* _NEW_BUFFERS
 528     *
 529     * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 530     * we have to invert the Y axis in order to match the OpenGL
 531     * pixel coordinate system, and our offset must be matched
 532     * to the window position.  If we're drawing to a FBO
 533     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 534     * system works just fine, and there's no window system to
 535     * worry about.
 536     */
 537    if (brw->intel.ctx.DrawBuffer->Name == 0)
 538       OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
 539    else
 540       OUT_BATCH(0);
 541    CACHED_BATCH();
 542 }
 543
 544 const struct brw_tracked_state brw_polygon_stipple_offset = {
 545    .dirty = {
 546       .mesa = (_NEW_BUFFERS |
 547                _NEW_POLYGON),
 548       .brw = BRW_NEW_CONTEXT,
 549       .cache = 0
 550    },
 551    .emit = upload_polygon_stipple_offset
 552 };
 553
 554 /**********************************************************************
 555  * AA Line parameters
 556  */
 557 static void upload_aa_line_parameters(struct brw_context *brw)
 558 {
 559    struct intel_context *intel = &brw->intel;
 560    struct gl_context *ctx = &brw->intel.ctx;
 561
 562    if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
 563       return;
 564
 565    if (intel->gen == 6)
 566       intel_emit_post_sync_nonzero_flush(intel);
 567
 568    OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
 569    /* use legacy aa line coverage computation */
 570    OUT_BATCH(0);
 571    OUT_BATCH(0);
 572    CACHED_BATCH();
 573 }
 574
 575 const struct brw_tracked_state brw_aa_line_parameters = {
 576    .dirty = {
 577       .mesa = _NEW_LINE,
 578       .brw = BRW_NEW_CONTEXT,
 579       .cache = 0
 580    },
 581    .emit = upload_aa_line_parameters
 582 };
 583
 584 /***********************************************************************
 585  * Line stipple packet
 586  */
 587
 588 static void upload_line_stipple(struct brw_context *brw)
 589 {
 590    struct intel_context *intel = &brw->intel;
 591    struct gl_context *ctx = &brw->intel.ctx;
 592    GLfloat tmp;
 593    GLint tmpi;
 594
 595    if (!ctx->Line.StippleFlag)
 596       return;
 597
 598    if (intel->gen == 6)
 599       intel_emit_post_sync_nonzero_flush(intel);
 600
 601    BEGIN_BATCH(3);
 602    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
 603    OUT_BATCH(ctx->Line.StipplePattern);
 604    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 605    tmpi = tmp * (1<<13);
 606    OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
 607    CACHED_BATCH();
 608 }
 609
 610 const struct brw_tracked_state brw_line_stipple = {
 611    .dirty = {
 612       .mesa = _NEW_LINE,
 613       .brw = BRW_NEW_CONTEXT,
 614       .cache = 0
 615    },
 616    .emit = upload_line_stipple
 617 };
 618
 619
 620 /***********************************************************************
 621  * Misc invarient state packets
 622  */
 623
 624 static void upload_invarient_state( struct brw_context *brw )
 625 {
 626    struct intel_context *intel = &brw->intel;
 627
 628    /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
 629    if (intel->gen == 6)
 630       intel_emit_post_sync_nonzero_flush(intel);
 631
 632    /* Select the 3D pipeline (as opposed to media) */
 633    BEGIN_BATCH(1);
 634    OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0);
 635    ADVANCE_BATCH();
 636
 637    if (intel->gen < 6) {
 638       /* Disable depth offset clamping. */
 639       BEGIN_BATCH(2);
 640       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
 641       OUT_BATCH_F(0.0);
 642       ADVANCE_BATCH();
 643    }
 644
 645    if (intel->gen >= 6) {
 646       int i;
 647       int len = intel->gen >= 7 ? 4 : 3;
 648
 649       BEGIN_BATCH(len);
 650       OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
 651       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
 652                 MS_NUMSAMPLES_1);
 653       OUT_BATCH(0); /* positions for 4/8-sample */
 654       if (intel->gen >= 7)
 655          OUT_BATCH(0);
 656       ADVANCE_BATCH();
 657
 658       BEGIN_BATCH(2);
 659       OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
 660       OUT_BATCH(1);
 661       ADVANCE_BATCH();
 662
 663       if (intel->gen < 7) {
 664          for (i = 0; i < 4; i++) {
 665             BEGIN_BATCH(4);
 666             OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
 667             OUT_BATCH(i << SVB_INDEX_SHIFT);
 668             OUT_BATCH(0);
 669             OUT_BATCH(0xffffffff);
 670             ADVANCE_BATCH();
 671          }
 672       }
 673    }
 674
 675    BEGIN_BATCH(2);
 676    OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2));
 677    OUT_BATCH(0);
 678    ADVANCE_BATCH();
 679
 680    BEGIN_BATCH(1);
 681    OUT_BATCH(brw->CMD_VF_STATISTICS << 16 |
 682              (unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0));
 683    ADVANCE_BATCH();
 684 }
 685
 686 const struct brw_tracked_state brw_invarient_state = {
 687    .dirty = {
 688       .mesa = 0,
 689       .brw = BRW_NEW_CONTEXT,
 690       .cache = 0
 691    },
 692    .emit = upload_invarient_state
 693 };
 694
 695 /**
 696  * Define the base addresses which some state is referenced from.
 697  *
 698  * This allows us to avoid having to emit relocations for the objects,
 699  * and is actually required for binding table pointers on gen6.
 700  *
 701  * Surface state base address covers binding table pointers and
 702  * surface state objects, but not the surfaces that the surface state
 703  * objects point to.
 704  */
 705 static void upload_state_base_address( struct brw_context *brw )
 706 {
 707    struct intel_context *intel = &brw->intel;
 708
 709    /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
 710     * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
 711     * programmed prior to STATE_BASE_ADDRESS.
 712     *
 713     * However, given that the instruction SBA (general state base
 714     * address) on this chipset is always set to 0 across X and GL,
 715     * maybe this isn't required for us in particular.
 716     */
 717
 718    if (intel->gen >= 6) {
 719       if (intel->gen == 6)
 720          intel_emit_post_sync_nonzero_flush(intel);
 721
 722        BEGIN_BATCH(10);
 723        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
 724        /* General state base address: stateless DP read/write requests */
 725        OUT_BATCH(1);
 726        /* Surface state base address:
 727         * BINDING_TABLE_STATE
 728         * SURFACE_STATE
 729         */
 730        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
 731         /* Dynamic state base address:
 732          * SAMPLER_STATE
 733          * SAMPLER_BORDER_COLOR_STATE
 734          * CLIP, SF, WM/CC viewport state
 735          * COLOR_CALC_STATE
 736          * DEPTH_STENCIL_STATE
 737          * BLEND_STATE
 738          * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
 739          * Disable is clear, which we rely on)
 740          */
 741        OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
 742                                    I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
 743
 744        OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
 745        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 746                  1); /* Instruction base address: shader kernels (incl. SIP) */
 747
 748        OUT_BATCH(1); /* General state upper bound */
 749        OUT_BATCH(1); /* Dynamic state upper bound */
 750        OUT_BATCH(1); /* Indirect object upper bound */
 751        OUT_BATCH(1); /* Instruction access upper bound */
 752        ADVANCE_BATCH();
 753    } else if (intel->gen == 5) {
 754        BEGIN_BATCH(8);
 755        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 756        OUT_BATCH(1); /* General state base address */
 757        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 758                  1); /* Surface state base address */
 759        OUT_BATCH(1); /* Indirect object base address */
 760        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 761                  1); /* Instruction base address */
 762        OUT_BATCH(1); /* General state upper bound */
 763        OUT_BATCH(1); /* Indirect object upper bound */
 764        OUT_BATCH(1); /* Instruction access upper bound */
 765        ADVANCE_BATCH();
 766    } else {
 767        BEGIN_BATCH(6);
 768        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 769        OUT_BATCH(1); /* General state base address */
 770        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 771                  1); /* Surface state base address */
 772        OUT_BATCH(1); /* Indirect object base address */
 773        OUT_BATCH(1); /* General state upper bound */
 774        OUT_BATCH(1); /* Indirect object upper bound */
 775        ADVANCE_BATCH();
 776    }
 777
 778    /* According to section 3.6.1 of VOL1 of the 965 PRM,
 779     * STATE_BASE_ADDRESS updates require a reissue of:
 780     *
 781     * 3DSTATE_PIPELINE_POINTERS
 782     * 3DSTATE_BINDING_TABLE_POINTERS
 783     * MEDIA_STATE_POINTERS
 784     *
 785     * and this continues through Ironlake.  The Sandy Bridge PRM, vol
 786     * 1 part 1 says that the folowing packets must be reissued:
 787     *
 788     * 3DSTATE_CC_POINTERS
 789     * 3DSTATE_BINDING_TABLE_POINTERS
 790     * 3DSTATE_SAMPLER_STATE_POINTERS
 791     * 3DSTATE_VIEWPORT_STATE_POINTERS
 792     * MEDIA_STATE_POINTERS
 793     *
 794     * Those are always reissued following SBA updates anyway (new
 795     * batch time), except in the case of the program cache BO
 796     * changing.  Having a separate state flag makes the sequence more
 797     * obvious.
 798     */
 799
 800    brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
 801 }
 802
 803 const struct brw_tracked_state brw_state_base_address = {
 804    .dirty = {
 805       .mesa = 0,
 806       .brw = (BRW_NEW_BATCH |
 807               BRW_NEW_PROGRAM_CACHE),
 808       .cache = 0,
 809    },
 810    .emit = upload_state_base_address
 811 };