2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_regions.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
39 #include "brw_defines.h"
45 /***********************************************************************
49 static void upload_blend_constant_color(struct brw_context
*brw
)
51 GLcontext
*ctx
= &brw
->intel
.ctx
;
52 struct brw_blend_constant_color bcc
;
54 memset(&bcc
, 0, sizeof(bcc
));
55 bcc
.header
.opcode
= CMD_BLEND_CONSTANT_COLOR
;
56 bcc
.header
.length
= sizeof(bcc
)/4-2;
57 bcc
.blend_constant_color
[0] = ctx
->Color
.BlendColor
[0];
58 bcc
.blend_constant_color
[1] = ctx
->Color
.BlendColor
[1];
59 bcc
.blend_constant_color
[2] = ctx
->Color
.BlendColor
[2];
60 bcc
.blend_constant_color
[3] = ctx
->Color
.BlendColor
[3];
62 BRW_CACHED_BATCH_STRUCT(brw
, &bcc
);
66 const struct brw_tracked_state brw_blend_constant_color
= {
69 .brw
= BRW_NEW_CONTEXT
,
72 .emit
= upload_blend_constant_color
75 /* Constant single cliprect for framebuffer object or DRI2 drawing */
76 static void upload_drawing_rect(struct brw_context
*brw
)
78 struct intel_context
*intel
= &brw
->intel
;
79 GLcontext
*ctx
= &intel
->ctx
;
81 if (!intel
->constant_cliprect
)
84 BEGIN_BATCH(4, NO_LOOP_CLIPRECTS
);
85 OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965
);
86 OUT_BATCH(0); /* xmin, ymin */
87 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
88 ((ctx
->DrawBuffer
->Height
- 1) << 16));
93 const struct brw_tracked_state brw_drawing_rect
= {
96 .brw
= BRW_NEW_CONTEXT
,
99 .emit
= upload_drawing_rect
102 static void prepare_binding_table_pointers(struct brw_context
*brw
)
104 brw_add_validated_bo(brw
, brw
->vs
.bind_bo
);
105 brw_add_validated_bo(brw
, brw
->wm
.bind_bo
);
109 * Upload the binding table pointers, which point each stage's array of surface
112 * The binding table pointers are relative to the surface state base address,
115 static void upload_binding_table_pointers(struct brw_context
*brw
)
117 struct intel_context
*intel
= &brw
->intel
;
119 BEGIN_BATCH(6, IGNORE_CLIPRECTS
);
120 OUT_BATCH(CMD_BINDING_TABLE_PTRS
<< 16 | (6 - 2));
121 if (brw
->vs
.bind_bo
!= NULL
)
122 OUT_RELOC(brw
->vs
.bind_bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 0); /* vs */
125 OUT_BATCH(0); /* gs */
126 OUT_BATCH(0); /* clip */
127 OUT_BATCH(0); /* sf */
128 OUT_RELOC(brw
->wm
.bind_bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 0); /* wm/ps */
132 const struct brw_tracked_state brw_binding_table_pointers
= {
135 .brw
= BRW_NEW_BATCH
,
136 .cache
= CACHE_NEW_SURF_BIND
,
138 .prepare
= prepare_binding_table_pointers
,
139 .emit
= upload_binding_table_pointers
,
144 * Upload pointers to the per-stage state.
146 * The state pointers in this packet are all relative to the general state
147 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
149 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
151 struct intel_context
*intel
= &brw
->intel
;
153 BEGIN_BATCH(7, IGNORE_CLIPRECTS
);
154 OUT_BATCH(CMD_PIPELINED_STATE_POINTERS
<< 16 | (7 - 2));
155 OUT_RELOC(brw
->vs
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
156 if (brw
->gs
.prog_active
)
157 OUT_RELOC(brw
->gs
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 1);
160 OUT_RELOC(brw
->clip
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 1);
161 OUT_RELOC(brw
->sf
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
162 OUT_RELOC(brw
->wm
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
163 OUT_RELOC(brw
->cc
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
166 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
170 static void prepare_psp_urb_cbs(struct brw_context
*brw
)
172 brw_add_validated_bo(brw
, brw
->vs
.state_bo
);
173 brw_add_validated_bo(brw
, brw
->gs
.state_bo
);
174 brw_add_validated_bo(brw
, brw
->clip
.state_bo
);
175 brw_add_validated_bo(brw
, brw
->sf
.state_bo
);
176 brw_add_validated_bo(brw
, brw
->wm
.state_bo
);
177 brw_add_validated_bo(brw
, brw
->cc
.state_bo
);
180 static void upload_psp_urb_cbs(struct brw_context
*brw
)
182 upload_pipelined_state_pointers(brw
);
183 brw_upload_urb_fence(brw
);
184 brw_upload_cs_urb_state(brw
);
187 const struct brw_tracked_state brw_psp_urb_cbs
= {
190 .brw
= BRW_NEW_URB_FENCE
| BRW_NEW_BATCH
,
191 .cache
= (CACHE_NEW_VS_UNIT
|
194 CACHE_NEW_CLIP_UNIT
|
199 .prepare
= prepare_psp_urb_cbs
,
200 .emit
= upload_psp_urb_cbs
,
203 static void prepare_depthbuffer(struct brw_context
*brw
)
205 struct intel_region
*region
= brw
->state
.depth_region
;
208 brw_add_validated_bo(brw
, region
->buffer
);
211 static void emit_depthbuffer(struct brw_context
*brw
)
213 struct intel_context
*intel
= &brw
->intel
;
214 struct intel_region
*region
= brw
->state
.depth_region
;
215 unsigned int len
= (BRW_IS_G4X(brw
) || BRW_IS_IGDNG(brw
)) ? 6 : 5;
217 if (region
== NULL
) {
218 BEGIN_BATCH(len
, IGNORE_CLIPRECTS
);
219 OUT_BATCH(CMD_DEPTH_BUFFER
<< 16 | (len
- 2));
220 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
221 (BRW_SURFACE_NULL
<< 29));
226 if (BRW_IS_G4X(brw
) || BRW_IS_IGDNG(brw
))
233 switch (region
->cpp
) {
235 format
= BRW_DEPTHFORMAT_D16_UNORM
;
238 if (intel
->depth_buffer_is_float
)
239 format
= BRW_DEPTHFORMAT_D32_FLOAT
;
241 format
= BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
248 assert(region
->tiling
!= I915_TILING_X
);
250 BEGIN_BATCH(len
, IGNORE_CLIPRECTS
);
251 OUT_BATCH(CMD_DEPTH_BUFFER
<< 16 | (len
- 2));
252 OUT_BATCH(((region
->pitch
* region
->cpp
) - 1) |
254 (BRW_TILEWALK_YMAJOR
<< 26) |
255 ((region
->tiling
!= I915_TILING_NONE
) << 27) |
256 (BRW_SURFACE_2D
<< 29));
257 OUT_RELOC(region
->buffer
,
258 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
260 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1) |
261 ((region
->pitch
- 1) << 6) |
262 ((region
->height
- 1) << 19));
265 if (BRW_IS_G4X(brw
) || BRW_IS_IGDNG(brw
))
272 const struct brw_tracked_state brw_depthbuffer
= {
275 .brw
= BRW_NEW_DEPTH_BUFFER
| BRW_NEW_BATCH
,
278 .prepare
= prepare_depthbuffer
,
279 .emit
= emit_depthbuffer
,
284 /***********************************************************************
285 * Polygon stipple packet
288 static void upload_polygon_stipple(struct brw_context
*brw
)
290 GLcontext
*ctx
= &brw
->intel
.ctx
;
291 struct brw_polygon_stipple bps
;
294 memset(&bps
, 0, sizeof(bps
));
295 bps
.header
.opcode
= CMD_POLY_STIPPLE_PATTERN
;
296 bps
.header
.length
= sizeof(bps
)/4-2;
298 /* Polygon stipple is provided in OpenGL order, i.e. bottom
299 * row first. If we're rendering to a window (i.e. the
300 * default frame buffer object, 0), then we need to invert
301 * it to match our pixel layout. But if we're rendering
302 * to a FBO (i.e. any named frame buffer object), we *don't*
303 * need to invert - we already match the layout.
305 if (ctx
->DrawBuffer
->Name
== 0) {
306 for (i
= 0; i
< 32; i
++)
307 bps
.stipple
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
310 for (i
= 0; i
< 32; i
++)
311 bps
.stipple
[i
] = ctx
->PolygonStipple
[i
]; /* don't invert */
314 BRW_CACHED_BATCH_STRUCT(brw
, &bps
);
317 const struct brw_tracked_state brw_polygon_stipple
= {
319 .mesa
= _NEW_POLYGONSTIPPLE
,
320 .brw
= BRW_NEW_CONTEXT
,
323 .emit
= upload_polygon_stipple
327 /***********************************************************************
328 * Polygon stipple offset packet
331 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
333 __DRIdrawablePrivate
*dPriv
= brw
->intel
.driDrawable
;
334 struct brw_polygon_stipple_offset bpso
;
336 memset(&bpso
, 0, sizeof(bpso
));
337 bpso
.header
.opcode
= CMD_POLY_STIPPLE_OFFSET
;
338 bpso
.header
.length
= sizeof(bpso
)/4-2;
340 /* If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
341 * we have to invert the Y axis in order to match the OpenGL
342 * pixel coordinate system, and our offset must be matched
343 * to the window position. If we're drawing to a FBO
344 * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
345 * system works just fine, and there's no window system to
348 if (brw
->intel
.ctx
.DrawBuffer
->Name
== 0) {
349 bpso
.bits0
.x_offset
= (32 - (dPriv
->x
& 31)) & 31;
350 bpso
.bits0
.y_offset
= (32 - ((dPriv
->y
+ dPriv
->h
) & 31)) & 31;
353 bpso
.bits0
.y_offset
= 0;
354 bpso
.bits0
.x_offset
= 0;
357 BRW_CACHED_BATCH_STRUCT(brw
, &bpso
);
360 #define _NEW_WINDOW_POS 0x40000000
362 const struct brw_tracked_state brw_polygon_stipple_offset
= {
364 .mesa
= _NEW_WINDOW_POS
,
365 .brw
= BRW_NEW_CONTEXT
,
368 .emit
= upload_polygon_stipple_offset
371 /**********************************************************************
374 static void upload_aa_line_parameters(struct brw_context
*brw
)
376 struct brw_aa_line_parameters balp
;
381 /* use legacy aa line coverage computation */
382 memset(&balp
, 0, sizeof(balp
));
383 balp
.header
.opcode
= CMD_AA_LINE_PARAMETERS
;
384 balp
.header
.length
= sizeof(balp
) / 4 - 2;
386 BRW_CACHED_BATCH_STRUCT(brw
, &balp
);
389 const struct brw_tracked_state brw_aa_line_parameters
= {
392 .brw
= BRW_NEW_CONTEXT
,
395 .emit
= upload_aa_line_parameters
398 /***********************************************************************
399 * Line stipple packet
402 static void upload_line_stipple(struct brw_context
*brw
)
404 GLcontext
*ctx
= &brw
->intel
.ctx
;
405 struct brw_line_stipple bls
;
409 memset(&bls
, 0, sizeof(bls
));
410 bls
.header
.opcode
= CMD_LINE_STIPPLE_PATTERN
;
411 bls
.header
.length
= sizeof(bls
)/4 - 2;
413 bls
.bits0
.pattern
= ctx
->Line
.StipplePattern
;
414 bls
.bits1
.repeat_count
= ctx
->Line
.StippleFactor
;
416 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
417 tmpi
= tmp
* (1<<13);
420 bls
.bits1
.inverse_repeat_count
= tmpi
;
422 BRW_CACHED_BATCH_STRUCT(brw
, &bls
);
425 const struct brw_tracked_state brw_line_stipple
= {
428 .brw
= BRW_NEW_CONTEXT
,
431 .emit
= upload_line_stipple
435 /***********************************************************************
436 * Misc invarient state packets
439 static void upload_invarient_state( struct brw_context
*brw
)
442 /* 0x61040000 Pipeline Select */
443 /* PipelineSelect : 0 */
444 struct brw_pipeline_select ps
;
446 memset(&ps
, 0, sizeof(ps
));
447 ps
.header
.opcode
= CMD_PIPELINE_SELECT(brw
);
448 ps
.header
.pipeline_select
= 0;
449 BRW_BATCH_STRUCT(brw
, &ps
);
453 struct brw_global_depth_offset_clamp gdo
;
454 memset(&gdo
, 0, sizeof(gdo
));
456 /* Disable depth offset clamping.
458 gdo
.header
.opcode
= CMD_GLOBAL_DEPTH_OFFSET_CLAMP
;
459 gdo
.header
.length
= sizeof(gdo
)/4 - 2;
460 gdo
.depth_offset_clamp
= 0.0;
462 BRW_BATCH_STRUCT(brw
, &gdo
);
466 /* 0x61020000 State Instruction Pointer */
468 struct brw_system_instruction_pointer sip
;
469 memset(&sip
, 0, sizeof(sip
));
471 sip
.header
.opcode
= CMD_STATE_INSN_POINTER
;
472 sip
.header
.length
= 0;
474 sip
.bits0
.system_instruction_pointer
= 0;
475 BRW_BATCH_STRUCT(brw
, &sip
);
480 struct brw_vf_statistics vfs
;
481 memset(&vfs
, 0, sizeof(vfs
));
483 vfs
.opcode
= CMD_VF_STATISTICS(brw
);
484 if (INTEL_DEBUG
& DEBUG_STATS
)
485 vfs
.statistics_enable
= 1;
487 BRW_BATCH_STRUCT(brw
, &vfs
);
491 const struct brw_tracked_state brw_invarient_state
= {
494 .brw
= BRW_NEW_CONTEXT
,
497 .emit
= upload_invarient_state
501 * Define the base addresses which some state is referenced from.
503 * This allows us to avoid having to emit relocations in many places for
504 * cached state, and instead emit pointers inside of large, mostly-static
505 * state pools. This comes at the expense of memory, and more expensive cache
508 static void upload_state_base_address( struct brw_context
*brw
)
510 struct intel_context
*intel
= &brw
->intel
;
512 /* Output the structure (brw_state_base_address) directly to the
513 * batchbuffer, so we can emit relocations inline.
515 if (BRW_IS_IGDNG(brw
)) {
516 BEGIN_BATCH(8, IGNORE_CLIPRECTS
);
517 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
518 OUT_BATCH(1); /* General state base address */
519 OUT_BATCH(1); /* Surface state base address */
520 OUT_BATCH(1); /* Indirect object base address */
521 OUT_BATCH(1); /* Instruction base address */
522 OUT_BATCH(1); /* General state upper bound */
523 OUT_BATCH(1); /* Indirect object upper bound */
524 OUT_BATCH(1); /* Instruction access upper bound */
527 BEGIN_BATCH(6, IGNORE_CLIPRECTS
);
528 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
529 OUT_BATCH(1); /* General state base address */
530 OUT_BATCH(1); /* Surface state base address */
531 OUT_BATCH(1); /* Indirect object base address */
532 OUT_BATCH(1); /* General state upper bound */
533 OUT_BATCH(1); /* Indirect object upper bound */
538 const struct brw_tracked_state brw_state_base_address
= {
541 .brw
= BRW_NEW_CONTEXT
,
544 .emit
= upload_state_base_address