2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
42 #include "main/framebuffer.h"
43 #include "main/fbobject.h"
44 #include "main/glformats.h"
46 /* Constant single cliprect for framebuffer object or DRI2 drawing */
47 static void upload_drawing_rect(struct brw_context
*brw
)
49 struct gl_context
*ctx
= &brw
->ctx
;
50 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
51 const unsigned int fb_width
= _mesa_geometric_width(fb
);
52 const unsigned int fb_height
= _mesa_geometric_height(fb
);
55 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
56 OUT_BATCH(0); /* xmin, ymin */
57 OUT_BATCH(((fb_width
- 1) & 0xffff) | ((fb_height
- 1) << 16));
62 const struct brw_tracked_state brw_drawing_rect
= {
65 .brw
= BRW_NEW_CONTEXT
,
67 .emit
= upload_drawing_rect
71 * Upload pointers to the per-stage state.
73 * The state pointers in this packet are all relative to the general state
74 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
76 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
79 /* Need to flush before changing clip max threads for errata. */
86 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
87 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
88 brw
->vs
.base
.state_offset
);
89 if (brw
->ff_gs
.prog_active
)
90 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
91 brw
->ff_gs
.state_offset
| 1);
94 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
95 brw
->clip
.state_offset
| 1);
96 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
97 brw
->sf
.state_offset
);
98 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
99 brw
->wm
.base
.state_offset
);
100 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
101 brw
->cc
.state_offset
);
104 brw
->ctx
.NewDriverState
|= BRW_NEW_PSP
;
107 static void upload_psp_urb_cbs(struct brw_context
*brw
)
109 upload_pipelined_state_pointers(brw
);
110 brw_upload_urb_fence(brw
);
111 brw_upload_cs_urb_state(brw
);
114 const struct brw_tracked_state brw_psp_urb_cbs
= {
117 .brw
= BRW_NEW_BATCH
|
118 BRW_NEW_FF_GS_PROG_DATA
|
119 BRW_NEW_GEN4_UNIT_STATE
|
120 BRW_NEW_STATE_BASE_ADDRESS
|
123 .emit
= upload_psp_urb_cbs
,
127 brw_depthbuffer_format(struct brw_context
*brw
)
129 struct gl_context
*ctx
= &brw
->ctx
;
130 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
131 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
132 struct intel_renderbuffer
*srb
;
135 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
136 !srb
->mt
->stencil_mt
&&
137 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
138 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
143 return BRW_DEPTHFORMAT_D32_FLOAT
;
145 return brw_depth_format(brw
, drb
->mt
->format
);
149 * Returns the mask of how many bits of x and y must be handled through the
150 * depthbuffer's draw offset x and y fields.
152 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
153 * between the depth, hiz, and stencil buffers. Because it can be hard to get
154 * all 3 to agree on this value, we want to do as much drawing offset
155 * adjustment as possible by moving the base offset of the 3 buffers, which is
156 * restricted to tile boundaries.
158 * For each buffer, the remainder must be applied through the x/y draw offset.
159 * This returns the worst-case mask of the low bits that have to go into the
160 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
161 * mask, then we're in trouble.
164 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
165 uint32_t depth_level
,
166 uint32_t depth_layer
,
167 struct intel_mipmap_tree
*stencil_mt
,
168 uint32_t *out_tile_mask_x
,
169 uint32_t *out_tile_mask_y
)
171 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
174 intel_miptree_get_tile_masks(depth_mt
, &tile_mask_x
, &tile_mask_y
, false);
176 if (intel_miptree_level_has_hiz(depth_mt
, depth_level
)) {
177 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
178 intel_miptree_get_tile_masks(depth_mt
->hiz_buf
->mt
,
179 &hiz_tile_mask_x
, &hiz_tile_mask_y
,
182 /* Each HiZ row represents 2 rows of pixels */
183 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
185 tile_mask_x
|= hiz_tile_mask_x
;
186 tile_mask_y
|= hiz_tile_mask_y
;
191 if (stencil_mt
->stencil_mt
)
192 stencil_mt
= stencil_mt
->stencil_mt
;
194 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
195 /* Separate stencil buffer uses 64x64 tiles. */
199 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
200 intel_miptree_get_tile_masks(stencil_mt
,
201 &stencil_tile_mask_x
,
202 &stencil_tile_mask_y
, false);
204 tile_mask_x
|= stencil_tile_mask_x
;
205 tile_mask_y
|= stencil_tile_mask_y
;
209 *out_tile_mask_x
= tile_mask_x
;
210 *out_tile_mask_y
= tile_mask_y
;
213 static struct intel_mipmap_tree
*
214 get_stencil_miptree(struct intel_renderbuffer
*irb
)
218 if (irb
->mt
->stencil_mt
)
219 return irb
->mt
->stencil_mt
;
224 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
225 GLbitfield clear_mask
)
227 struct gl_context
*ctx
= &brw
->ctx
;
228 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
229 bool rebase_depth
= false;
230 bool rebase_stencil
= false;
231 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
232 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
233 struct intel_mipmap_tree
*depth_mt
= NULL
;
234 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
235 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
236 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
237 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
238 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
241 depth_mt
= depth_irb
->mt
;
243 /* Initialize brw->depthstencil to 'nop' workaround state.
245 brw
->depthstencil
.tile_x
= 0;
246 brw
->depthstencil
.tile_y
= 0;
247 brw
->depthstencil
.depth_offset
= 0;
248 brw
->depthstencil
.stencil_offset
= 0;
249 brw
->depthstencil
.hiz_offset
= 0;
250 brw
->depthstencil
.depth_mt
= NULL
;
251 brw
->depthstencil
.stencil_mt
= NULL
;
253 brw
->depthstencil
.depth_mt
= depth_mt
;
255 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
257 /* Gen6+ doesn't require the workarounds, since we always program the
258 * surface state at the start of the whole surface.
263 /* Check if depth buffer is in depth/stencil format. If so, then it's only
264 * safe to invalidate it if we're also clearing stencil, and both depth_irb
265 * and stencil_irb point to the same miptree.
267 * Note: it's not sufficient to check for the case where
268 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
269 * because this fails to catch depth/stencil buffers on hardware that uses
270 * separate stencil. To catch that case, we check whether
271 * depth_mt->stencil_mt is non-NULL.
273 if (depth_irb
&& invalidate_depth
&&
274 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
275 depth_mt
->stencil_mt
)) {
276 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
277 && depth_irb
->mt
== stencil_irb
->mt
;
280 uint32_t tile_mask_x
, tile_mask_y
;
281 brw_get_depthstencil_tile_masks(depth_mt
,
282 depth_mt
? depth_irb
->mt_level
: 0,
283 depth_mt
? depth_irb
->mt_layer
: 0,
285 &tile_mask_x
, &tile_mask_y
);
288 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
289 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
291 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
292 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
293 * Coordinate Offset X/Y":
295 * "The 3 LSBs of both offsets must be zero to ensure correct
298 if (tile_x
& 7 || tile_y
& 7)
301 /* We didn't even have intra-tile offsets before g45. */
302 if (!brw
->has_surface_tile_offset
) {
303 if (tile_x
|| tile_y
)
308 perf_debug("HW workaround: blitting depth level %d to a temporary "
309 "to fix alignment (depth tile offset %d,%d)\n",
310 depth_irb
->mt_level
, tile_x
, tile_y
);
311 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
312 /* In the case of stencil_irb being the same packed depth/stencil
313 * texture but not the same rb, make it point at our rebased mt, too.
316 stencil_irb
!= depth_irb
&&
317 stencil_irb
->mt
== depth_mt
) {
318 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
319 intel_renderbuffer_set_draw_offset(stencil_irb
);
322 stencil_mt
= get_stencil_miptree(stencil_irb
);
324 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
325 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
329 stencil_mt
= get_stencil_miptree(stencil_irb
);
330 intel_miptree_get_image_offset(stencil_mt
,
331 stencil_irb
->mt_level
,
332 stencil_irb
->mt_layer
,
333 &stencil_draw_x
, &stencil_draw_y
);
334 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
335 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
337 /* If stencil doesn't match depth, then we'll need to rebase stencil
338 * as well. (if we hadn't decided to rebase stencil before, the
339 * post-stencil depth test will also rebase depth to try to match it
342 if (tile_x
!= stencil_tile_x
||
343 tile_y
!= stencil_tile_y
) {
344 rebase_stencil
= true;
349 /* If we have (just) stencil, check it for ignored low bits as well */
351 intel_miptree_get_image_offset(stencil_mt
,
352 stencil_irb
->mt_level
,
353 stencil_irb
->mt_layer
,
354 &stencil_draw_x
, &stencil_draw_y
);
355 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
356 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
358 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
359 rebase_stencil
= true;
361 if (!brw
->has_surface_tile_offset
) {
362 if (stencil_tile_x
|| stencil_tile_y
)
363 rebase_stencil
= true;
367 if (rebase_stencil
) {
368 perf_debug("HW workaround: blitting stencil level %d to a temporary "
369 "to fix alignment (stencil tile offset %d,%d)\n",
370 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
372 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
373 stencil_mt
= get_stencil_miptree(stencil_irb
);
375 intel_miptree_get_image_offset(stencil_mt
,
376 stencil_irb
->mt_level
,
377 stencil_irb
->mt_layer
,
378 &stencil_draw_x
, &stencil_draw_y
);
379 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
380 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
382 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
383 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
384 intel_renderbuffer_set_draw_offset(depth_irb
);
385 } else if (depth_irb
&& !rebase_depth
) {
386 if (tile_x
!= stencil_tile_x
||
387 tile_y
!= stencil_tile_y
) {
388 perf_debug("HW workaround: blitting depth level %d to a temporary "
389 "to match stencil level %d alignment (depth tile offset "
390 "%d,%d, stencil offset %d,%d)\n",
392 stencil_irb
->mt_level
,
394 stencil_tile_x
, stencil_tile_y
);
396 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
398 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
399 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
401 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
402 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
403 intel_renderbuffer_set_draw_offset(stencil_irb
);
406 WARN_ONCE(stencil_tile_x
!= tile_x
||
407 stencil_tile_y
!= tile_y
,
408 "Rebased stencil tile offset (%d,%d) doesn't match depth "
409 "tile offset (%d,%d).\n",
410 stencil_tile_x
, stencil_tile_y
,
417 tile_x
= stencil_tile_x
;
418 tile_y
= stencil_tile_y
;
421 /* While we just tried to get everything aligned, we may have failed to do
422 * so in the case of rendering to array or 3D textures, where nonzero faces
423 * will still have an offset post-rebase. At least give an informative
426 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
427 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
428 "Truncating offset, bad rendering may occur.\n");
432 /* Now, after rebasing, save off the new dephtstencil state so the hardware
433 * packets can just dereference that without re-calculating tile offsets.
435 brw
->depthstencil
.tile_x
= tile_x
;
436 brw
->depthstencil
.tile_y
= tile_y
;
438 depth_mt
= depth_irb
->mt
;
439 brw
->depthstencil
.depth_mt
= depth_mt
;
440 brw
->depthstencil
.depth_offset
=
441 intel_miptree_get_aligned_offset(depth_mt
,
442 depth_irb
->draw_x
& ~tile_mask_x
,
443 depth_irb
->draw_y
& ~tile_mask_y
,
445 if (intel_renderbuffer_has_hiz(depth_irb
)) {
446 brw
->depthstencil
.hiz_offset
=
447 intel_miptree_get_aligned_offset(depth_mt
,
448 depth_irb
->draw_x
& ~tile_mask_x
,
449 (depth_irb
->draw_y
& ~tile_mask_y
) / 2,
454 stencil_mt
= get_stencil_miptree(stencil_irb
);
456 brw
->depthstencil
.stencil_mt
= stencil_mt
;
457 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
458 /* Note: we can't compute the stencil offset using
459 * intel_region_get_aligned_offset(), because stencil_region claims
460 * that the region is untiled even though it's W tiled.
462 brw
->depthstencil
.stencil_offset
=
463 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
464 (stencil_draw_x
& ~tile_mask_x
) * 64;
470 brw_emit_depthbuffer(struct brw_context
*brw
)
472 struct gl_context
*ctx
= &brw
->ctx
;
473 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
475 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
476 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
477 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
478 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
479 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
480 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
481 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
482 bool separate_stencil
= false;
483 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
484 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
485 uint32_t depth_offset
= 0;
486 uint32_t width
= 1, height
= 1;
489 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
491 /* Gen7 supports only separate stencil */
492 assert(separate_stencil
|| brw
->gen
< 7);
495 /* If there's a packed depth/stencil bound to stencil only, we need to
496 * emit the packed depth/stencil buffer packet.
498 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
499 depth_irb
= stencil_irb
;
500 depth_mt
= stencil_mt
;
503 if (depth_irb
&& depth_mt
) {
504 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
505 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
506 * depthstencil format.
508 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
509 * set to the same value. Gens after 7 implicitly always set
510 * Separate_Stencil_Enable; software cannot disable it.
512 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
513 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
516 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
517 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
519 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
520 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
522 depthbuffer_format
= brw_depthbuffer_format(brw
);
523 depth_surface_type
= BRW_SURFACE_2D
;
524 depth_offset
= brw
->depthstencil
.depth_offset
;
525 width
= depth_irb
->Base
.Base
.Width
;
526 height
= depth_irb
->Base
.Base
.Height
;
527 } else if (separate_stencil
) {
529 * There exists a separate stencil buffer but no depth buffer.
531 * The stencil buffer inherits most of its fields from
532 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
535 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
536 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
537 * [DevGT+]: This field must be set to TRUE.
539 assert(brw
->has_separate_stencil
);
541 depth_surface_type
= BRW_SURFACE_2D
;
542 width
= stencil_irb
->Base
.Base
.Width
;
543 height
= stencil_irb
->Base
.Base
.Height
;
547 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
549 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
551 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
552 depthbuffer_format
, depth_surface_type
,
553 stencil_mt
, hiz
, separate_stencil
,
554 width
, height
, tile_x
, tile_y
);
558 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
559 struct intel_mipmap_tree
*depth_mt
,
560 uint32_t depth_offset
, uint32_t depthbuffer_format
,
561 uint32_t depth_surface_type
,
562 struct intel_mipmap_tree
*stencil_mt
,
563 bool hiz
, bool separate_stencil
,
564 uint32_t width
, uint32_t height
,
565 uint32_t tile_x
, uint32_t tile_y
)
567 /* Enable the hiz bit if we're doing separate stencil, because it and the
568 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
569 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
570 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
571 * Enable must also be enabled.
573 * [DevGT]: This field must be set to the same value (enabled or
574 * disabled) as Hierarchical Depth Buffer Enable
576 bool enable_hiz_ss
= hiz
|| separate_stencil
;
579 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
580 * non-pipelined state that will need the PIPE_CONTROL workaround.
583 intel_emit_depth_stall_flushes(brw
);
589 else if (brw
->is_g4x
|| brw
->gen
== 5)
595 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
596 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
597 (depthbuffer_format
<< 18) |
598 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
599 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
600 (BRW_TILEWALK_YMAJOR
<< 26) |
601 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
603 (depth_surface_type
<< 29));
606 OUT_RELOC(depth_mt
->bo
,
607 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
613 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
614 ((height
+ tile_y
- 1) << 19));
617 if (brw
->is_g4x
|| brw
->gen
>= 5)
618 OUT_BATCH(tile_x
| (tile_y
<< 16));
620 assert(tile_x
== 0 && tile_y
== 0);
627 if (hiz
|| separate_stencil
) {
629 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
630 * stencil enable' and 'hiz enable' bits were set. Therefore we must
631 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
632 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
633 * failure to do so causes hangs on gen5 and a stall on gen6.
636 /* Emit hiz buffer. */
638 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_buf
->mt
;
640 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
641 OUT_BATCH(hiz_mt
->pitch
- 1);
642 OUT_RELOC(hiz_mt
->bo
,
643 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
644 brw
->depthstencil
.hiz_offset
);
648 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
654 /* Emit stencil buffer. */
655 if (separate_stencil
) {
657 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
658 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
659 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
660 * The pitch must be set to 2x the value computed based on width, as
661 * the stencil buffer is stored with two rows interleaved.
663 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
664 OUT_RELOC(stencil_mt
->bo
,
665 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
666 brw
->depthstencil
.stencil_offset
);
670 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
678 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
679 * params must be emitted.
681 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
682 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
683 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
685 if (brw
->gen
>= 6 || hiz
) {
687 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
688 GEN5_DEPTH_CLEAR_VALID
|
690 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
695 const struct brw_tracked_state brw_depthbuffer
= {
697 .mesa
= _NEW_BUFFERS
,
698 .brw
= BRW_NEW_BATCH
,
700 .emit
= brw_emit_depthbuffer
,
705 /***********************************************************************
706 * Polygon stipple packet
709 static void upload_polygon_stipple(struct brw_context
*brw
)
711 struct gl_context
*ctx
= &brw
->ctx
;
715 if (!ctx
->Polygon
.StippleFlag
)
719 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
721 /* Polygon stipple is provided in OpenGL order, i.e. bottom
722 * row first. If we're rendering to a window (i.e. the
723 * default frame buffer object, 0), then we need to invert
724 * it to match our pixel layout. But if we're rendering
725 * to a FBO (i.e. any named frame buffer object), we *don't*
726 * need to invert - we already match the layout.
728 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
729 for (i
= 0; i
< 32; i
++)
730 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
733 for (i
= 0; i
< 32; i
++)
734 OUT_BATCH(ctx
->PolygonStipple
[i
]);
739 const struct brw_tracked_state brw_polygon_stipple
= {
741 .mesa
= _NEW_POLYGON
|
743 .brw
= BRW_NEW_CONTEXT
,
745 .emit
= upload_polygon_stipple
749 /***********************************************************************
750 * Polygon stipple offset packet
753 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
755 struct gl_context
*ctx
= &brw
->ctx
;
758 if (!ctx
->Polygon
.StippleFlag
)
762 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
766 * If we're drawing to a system window we have to invert the Y axis
767 * in order to match the OpenGL pixel coordinate system, and our
768 * offset must be matched to the window position. If we're drawing
769 * to a user-created FBO then our native pixel coordinate system
770 * works just fine, and there's no window system to worry about.
772 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
773 OUT_BATCH((32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31);
779 const struct brw_tracked_state brw_polygon_stipple_offset
= {
781 .mesa
= _NEW_BUFFERS
|
783 .brw
= BRW_NEW_CONTEXT
,
785 .emit
= upload_polygon_stipple_offset
788 /**********************************************************************
791 static void upload_aa_line_parameters(struct brw_context
*brw
)
793 struct gl_context
*ctx
= &brw
->ctx
;
795 if (!ctx
->Line
.SmoothFlag
)
798 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
799 if (brw
->gen
== 4 && !brw
->is_g4x
)
803 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
804 /* use legacy aa line coverage computation */
810 const struct brw_tracked_state brw_aa_line_parameters
= {
813 .brw
= BRW_NEW_CONTEXT
,
815 .emit
= upload_aa_line_parameters
818 /***********************************************************************
819 * Line stipple packet
822 static void upload_line_stipple(struct brw_context
*brw
)
824 struct gl_context
*ctx
= &brw
->ctx
;
828 if (!ctx
->Line
.StippleFlag
)
832 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
833 OUT_BATCH(ctx
->Line
.StipplePattern
);
837 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
838 tmpi
= tmp
* (1<<16);
839 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
843 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
844 tmpi
= tmp
* (1<<13);
845 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
851 const struct brw_tracked_state brw_line_stipple
= {
854 .brw
= BRW_NEW_CONTEXT
,
856 .emit
= upload_line_stipple
861 brw_emit_select_pipeline(struct brw_context
*brw
, enum brw_pipeline pipeline
)
863 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
864 const uint32_t _3DSTATE_PIPELINE_SELECT
=
865 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
867 /* Select the pipeline */
869 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 |
870 (brw
->gen
>= 9 ? (3 << 8) : 0) |
871 (pipeline
== BRW_COMPUTE_PIPELINE
? 2 : 0));
876 /***********************************************************************
877 * Misc invariant state packets
881 brw_upload_invariant_state(struct brw_context
*brw
)
883 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
885 brw_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
888 /* Disable depth offset clamping. */
890 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
897 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
903 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
908 const uint32_t _3DSTATE_VF_STATISTICS
=
909 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
911 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 | 1);
915 const struct brw_tracked_state brw_invariant_state
= {
918 .brw
= BRW_NEW_CONTEXT
,
920 .emit
= brw_upload_invariant_state
924 * Define the base addresses which some state is referenced from.
926 * This allows us to avoid having to emit relocations for the objects,
927 * and is actually required for binding table pointers on gen6.
929 * Surface state base address covers binding table pointers and
930 * surface state objects, but not the surfaces that the surface state
933 static void upload_state_base_address( struct brw_context
*brw
)
935 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
936 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
937 * programmed prior to STATE_BASE_ADDRESS.
939 * However, given that the instruction SBA (general state base
940 * address) on this chipset is always set to 0 across X and GL,
941 * maybe this isn't required for us in particular.
945 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
948 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
949 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
950 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
951 1); /* General State Base Address Modify Enable */
952 /* Surface state base address:
953 * BINDING_TABLE_STATE
956 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
957 /* Dynamic state base address:
959 * SAMPLER_BORDER_COLOR_STATE
960 * CLIP, SF, WM/CC viewport state
962 * DEPTH_STENCIL_STATE
964 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
965 * Disable is clear, which we rely on)
967 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
968 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
970 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
971 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
972 1); /* Instruction base address: shader kernels (incl. SIP) */
974 OUT_BATCH(1); /* General state upper bound */
975 /* Dynamic state upper bound. Although the documentation says that
976 * programming it to zero will cause it to be ignored, that is a lie.
977 * If this isn't programmed to a real bound, the sampler border color
978 * pointer is rejected, causing border color to mysteriously fail.
980 OUT_BATCH(0xfffff001);
981 OUT_BATCH(1); /* Indirect object upper bound */
982 OUT_BATCH(1); /* Instruction access upper bound */
984 } else if (brw
->gen
== 5) {
986 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
987 OUT_BATCH(1); /* General state base address */
988 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
989 1); /* Surface state base address */
990 OUT_BATCH(1); /* Indirect object base address */
991 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
992 1); /* Instruction base address */
993 OUT_BATCH(0xfffff001); /* General state upper bound */
994 OUT_BATCH(1); /* Indirect object upper bound */
995 OUT_BATCH(1); /* Instruction access upper bound */
999 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1000 OUT_BATCH(1); /* General state base address */
1001 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1002 1); /* Surface state base address */
1003 OUT_BATCH(1); /* Indirect object base address */
1004 OUT_BATCH(1); /* General state upper bound */
1005 OUT_BATCH(1); /* Indirect object upper bound */
1009 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1010 * STATE_BASE_ADDRESS updates require a reissue of:
1012 * 3DSTATE_PIPELINE_POINTERS
1013 * 3DSTATE_BINDING_TABLE_POINTERS
1014 * MEDIA_STATE_POINTERS
1016 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1017 * 1 part 1 says that the folowing packets must be reissued:
1019 * 3DSTATE_CC_POINTERS
1020 * 3DSTATE_BINDING_TABLE_POINTERS
1021 * 3DSTATE_SAMPLER_STATE_POINTERS
1022 * 3DSTATE_VIEWPORT_STATE_POINTERS
1023 * MEDIA_STATE_POINTERS
1025 * Those are always reissued following SBA updates anyway (new
1026 * batch time), except in the case of the program cache BO
1027 * changing. Having a separate state flag makes the sequence more
1031 brw
->ctx
.NewDriverState
|= BRW_NEW_STATE_BASE_ADDRESS
;
1034 const struct brw_tracked_state brw_state_base_address
= {
1037 .brw
= BRW_NEW_BATCH
|
1038 BRW_NEW_PROGRAM_CACHE
,
1040 .emit
= upload_state_base_address