2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
42 #include "main/fbobject.h"
43 #include "main/glformats.h"
45 /* Constant single cliprect for framebuffer object or DRI2 drawing */
46 static void upload_drawing_rect(struct brw_context
*brw
)
48 struct gl_context
*ctx
= &brw
->ctx
;
50 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined. */
52 intel_emit_post_sync_nonzero_flush(brw
);
55 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
56 OUT_BATCH(0); /* xmin, ymin */
57 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
58 ((ctx
->DrawBuffer
->Height
- 1) << 16));
63 const struct brw_tracked_state brw_drawing_rect
= {
66 .brw
= BRW_NEW_CONTEXT
,
69 .emit
= upload_drawing_rect
73 * Upload pointers to the per-stage state.
75 * The state pointers in this packet are all relative to the general state
76 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
78 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
81 /* Need to flush before changing clip max threads for errata. */
88 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
89 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
90 brw
->vs
.base
.state_offset
);
91 if (brw
->ff_gs
.prog_active
)
92 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
93 brw
->ff_gs
.state_offset
| 1);
96 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
97 brw
->clip
.state_offset
| 1);
98 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
99 brw
->sf
.state_offset
);
100 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
101 brw
->wm
.base
.state_offset
);
102 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
103 brw
->cc
.state_offset
);
106 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
109 static void upload_psp_urb_cbs(struct brw_context
*brw
)
111 upload_pipelined_state_pointers(brw
);
112 brw_upload_urb_fence(brw
);
113 brw_upload_cs_urb_state(brw
);
116 const struct brw_tracked_state brw_psp_urb_cbs
= {
119 .brw
= (BRW_NEW_URB_FENCE
|
121 BRW_NEW_STATE_BASE_ADDRESS
),
122 .cache
= (CACHE_NEW_VS_UNIT
|
123 CACHE_NEW_FF_GS_UNIT
|
124 CACHE_NEW_FF_GS_PROG
|
125 CACHE_NEW_CLIP_UNIT
|
130 .emit
= upload_psp_urb_cbs
,
134 brw_depthbuffer_format(struct brw_context
*brw
)
136 struct gl_context
*ctx
= &brw
->ctx
;
137 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
138 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
139 struct intel_renderbuffer
*srb
;
142 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
143 !srb
->mt
->stencil_mt
&&
144 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
145 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
150 return BRW_DEPTHFORMAT_D32_FLOAT
;
152 return brw_depth_format(brw
, drb
->mt
->format
);
156 * Returns the mask of how many bits of x and y must be handled through the
157 * depthbuffer's draw offset x and y fields.
159 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
160 * between the depth, hiz, and stencil buffers. Because it can be hard to get
161 * all 3 to agree on this value, we want to do as much drawing offset
162 * adjustment as possible by moving the base offset of the 3 buffers, which is
163 * restricted to tile boundaries.
165 * For each buffer, the remainder must be applied through the x/y draw offset.
166 * This returns the worst-case mask of the low bits that have to go into the
167 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
168 * mask, then we're in trouble.
171 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
172 uint32_t depth_level
,
173 uint32_t depth_layer
,
174 struct intel_mipmap_tree
*stencil_mt
,
175 uint32_t *out_tile_mask_x
,
176 uint32_t *out_tile_mask_y
)
178 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
181 intel_miptree_get_tile_masks(depth_mt
, &tile_mask_x
, &tile_mask_y
, false);
183 if (intel_miptree_level_has_hiz(depth_mt
, depth_level
)) {
184 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
185 intel_miptree_get_tile_masks(depth_mt
->hiz_mt
,
186 &hiz_tile_mask_x
, &hiz_tile_mask_y
,
189 /* Each HiZ row represents 2 rows of pixels */
190 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
192 tile_mask_x
|= hiz_tile_mask_x
;
193 tile_mask_y
|= hiz_tile_mask_y
;
198 if (stencil_mt
->stencil_mt
)
199 stencil_mt
= stencil_mt
->stencil_mt
;
201 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
202 /* Separate stencil buffer uses 64x64 tiles. */
206 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
207 intel_miptree_get_tile_masks(stencil_mt
,
208 &stencil_tile_mask_x
,
209 &stencil_tile_mask_y
, false);
211 tile_mask_x
|= stencil_tile_mask_x
;
212 tile_mask_y
|= stencil_tile_mask_y
;
216 *out_tile_mask_x
= tile_mask_x
;
217 *out_tile_mask_y
= tile_mask_y
;
220 static struct intel_mipmap_tree
*
221 get_stencil_miptree(struct intel_renderbuffer
*irb
)
225 if (irb
->mt
->stencil_mt
)
226 return irb
->mt
->stencil_mt
;
231 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
232 GLbitfield clear_mask
)
234 struct gl_context
*ctx
= &brw
->ctx
;
235 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
236 bool rebase_depth
= false;
237 bool rebase_stencil
= false;
238 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
239 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
240 struct intel_mipmap_tree
*depth_mt
= NULL
;
241 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
242 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
243 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
244 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
245 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
248 depth_mt
= depth_irb
->mt
;
250 /* Initialize brw->depthstencil to 'nop' workaround state.
252 brw
->depthstencil
.tile_x
= 0;
253 brw
->depthstencil
.tile_y
= 0;
254 brw
->depthstencil
.depth_offset
= 0;
255 brw
->depthstencil
.stencil_offset
= 0;
256 brw
->depthstencil
.hiz_offset
= 0;
257 brw
->depthstencil
.depth_mt
= NULL
;
258 brw
->depthstencil
.stencil_mt
= NULL
;
260 brw
->depthstencil
.depth_mt
= depth_mt
;
262 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
264 /* Gen7+ doesn't require the workarounds, since we always program the
265 * surface state at the start of the whole surface.
270 /* Check if depth buffer is in depth/stencil format. If so, then it's only
271 * safe to invalidate it if we're also clearing stencil, and both depth_irb
272 * and stencil_irb point to the same miptree.
274 * Note: it's not sufficient to check for the case where
275 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
276 * because this fails to catch depth/stencil buffers on hardware that uses
277 * separate stencil. To catch that case, we check whether
278 * depth_mt->stencil_mt is non-NULL.
280 if (depth_irb
&& invalidate_depth
&&
281 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
282 depth_mt
->stencil_mt
)) {
283 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
284 && depth_irb
->mt
== stencil_irb
->mt
;
287 uint32_t tile_mask_x
, tile_mask_y
;
288 brw_get_depthstencil_tile_masks(depth_mt
,
289 depth_mt
? depth_irb
->mt_level
: 0,
290 depth_mt
? depth_irb
->mt_layer
: 0,
292 &tile_mask_x
, &tile_mask_y
);
295 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
296 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
298 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
299 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
300 * Coordinate Offset X/Y":
302 * "The 3 LSBs of both offsets must be zero to ensure correct
305 if (tile_x
& 7 || tile_y
& 7)
308 /* We didn't even have intra-tile offsets before g45. */
309 if (!brw
->has_surface_tile_offset
) {
310 if (tile_x
|| tile_y
)
315 perf_debug("HW workaround: blitting depth level %d to a temporary "
316 "to fix alignment (depth tile offset %d,%d)\n",
317 depth_irb
->mt_level
, tile_x
, tile_y
);
318 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
319 /* In the case of stencil_irb being the same packed depth/stencil
320 * texture but not the same rb, make it point at our rebased mt, too.
323 stencil_irb
!= depth_irb
&&
324 stencil_irb
->mt
== depth_mt
) {
325 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
326 intel_renderbuffer_set_draw_offset(stencil_irb
);
329 stencil_mt
= get_stencil_miptree(stencil_irb
);
331 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
332 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
336 stencil_mt
= get_stencil_miptree(stencil_irb
);
337 intel_miptree_get_image_offset(stencil_mt
,
338 stencil_irb
->mt_level
,
339 stencil_irb
->mt_layer
,
340 &stencil_draw_x
, &stencil_draw_y
);
341 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
342 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
344 /* If stencil doesn't match depth, then we'll need to rebase stencil
345 * as well. (if we hadn't decided to rebase stencil before, the
346 * post-stencil depth test will also rebase depth to try to match it
349 if (tile_x
!= stencil_tile_x
||
350 tile_y
!= stencil_tile_y
) {
351 rebase_stencil
= true;
356 /* If we have (just) stencil, check it for ignored low bits as well */
358 intel_miptree_get_image_offset(stencil_mt
,
359 stencil_irb
->mt_level
,
360 stencil_irb
->mt_layer
,
361 &stencil_draw_x
, &stencil_draw_y
);
362 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
363 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
365 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
366 rebase_stencil
= true;
368 if (!brw
->has_surface_tile_offset
) {
369 if (stencil_tile_x
|| stencil_tile_y
)
370 rebase_stencil
= true;
374 if (rebase_stencil
) {
375 perf_debug("HW workaround: blitting stencil level %d to a temporary "
376 "to fix alignment (stencil tile offset %d,%d)\n",
377 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
379 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
380 stencil_mt
= get_stencil_miptree(stencil_irb
);
382 intel_miptree_get_image_offset(stencil_mt
,
383 stencil_irb
->mt_level
,
384 stencil_irb
->mt_layer
,
385 &stencil_draw_x
, &stencil_draw_y
);
386 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
387 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
389 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
390 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
391 intel_renderbuffer_set_draw_offset(depth_irb
);
392 } else if (depth_irb
&& !rebase_depth
) {
393 if (tile_x
!= stencil_tile_x
||
394 tile_y
!= stencil_tile_y
) {
395 perf_debug("HW workaround: blitting depth level %d to a temporary "
396 "to match stencil level %d alignment (depth tile offset "
397 "%d,%d, stencil offset %d,%d)\n",
399 stencil_irb
->mt_level
,
401 stencil_tile_x
, stencil_tile_y
);
403 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
405 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
406 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
408 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
409 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
410 intel_renderbuffer_set_draw_offset(stencil_irb
);
413 WARN_ONCE(stencil_tile_x
!= tile_x
||
414 stencil_tile_y
!= tile_y
,
415 "Rebased stencil tile offset (%d,%d) doesn't match depth "
416 "tile offset (%d,%d).\n",
417 stencil_tile_x
, stencil_tile_y
,
424 tile_x
= stencil_tile_x
;
425 tile_y
= stencil_tile_y
;
428 /* While we just tried to get everything aligned, we may have failed to do
429 * so in the case of rendering to array or 3D textures, where nonzero faces
430 * will still have an offset post-rebase. At least give an informative
433 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
434 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
435 "Truncating offset, bad rendering may occur.\n");
439 /* Now, after rebasing, save off the new dephtstencil state so the hardware
440 * packets can just dereference that without re-calculating tile offsets.
442 brw
->depthstencil
.tile_x
= tile_x
;
443 brw
->depthstencil
.tile_y
= tile_y
;
445 depth_mt
= depth_irb
->mt
;
446 brw
->depthstencil
.depth_mt
= depth_mt
;
447 brw
->depthstencil
.depth_offset
=
448 intel_miptree_get_aligned_offset(depth_mt
,
449 depth_irb
->draw_x
& ~tile_mask_x
,
450 depth_irb
->draw_y
& ~tile_mask_y
,
452 if (intel_renderbuffer_has_hiz(depth_irb
)) {
453 brw
->depthstencil
.hiz_offset
=
454 intel_miptree_get_aligned_offset(depth_mt
,
455 depth_irb
->draw_x
& ~tile_mask_x
,
456 (depth_irb
->draw_y
& ~tile_mask_y
) / 2,
461 stencil_mt
= get_stencil_miptree(stencil_irb
);
463 brw
->depthstencil
.stencil_mt
= stencil_mt
;
464 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
465 /* Note: we can't compute the stencil offset using
466 * intel_region_get_aligned_offset(), because stencil_region claims
467 * that the region is untiled even though it's W tiled.
469 brw
->depthstencil
.stencil_offset
=
470 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
471 (stencil_draw_x
& ~tile_mask_x
) * 64;
477 brw_emit_depthbuffer(struct brw_context
*brw
)
479 struct gl_context
*ctx
= &brw
->ctx
;
480 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
482 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
483 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
484 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
485 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
486 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
487 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
488 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
489 bool separate_stencil
= false;
490 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
491 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
492 uint32_t depth_offset
= 0;
493 uint32_t width
= 1, height
= 1;
496 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
498 /* Gen7 supports only separate stencil */
499 assert(separate_stencil
|| brw
->gen
< 7);
502 /* If there's a packed depth/stencil bound to stencil only, we need to
503 * emit the packed depth/stencil buffer packet.
505 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
506 depth_irb
= stencil_irb
;
507 depth_mt
= stencil_mt
;
510 if (depth_irb
&& depth_mt
) {
511 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
512 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
513 * depthstencil format.
515 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
516 * set to the same value. Gens after 7 implicitly always set
517 * Separate_Stencil_Enable; software cannot disable it.
519 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
520 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
523 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
524 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
526 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
527 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
529 depthbuffer_format
= brw_depthbuffer_format(brw
);
530 depth_surface_type
= BRW_SURFACE_2D
;
531 depth_offset
= brw
->depthstencil
.depth_offset
;
532 width
= depth_irb
->Base
.Base
.Width
;
533 height
= depth_irb
->Base
.Base
.Height
;
534 } else if (separate_stencil
) {
536 * There exists a separate stencil buffer but no depth buffer.
538 * The stencil buffer inherits most of its fields from
539 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
542 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
543 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
544 * [DevGT+]: This field must be set to TRUE.
546 assert(brw
->has_separate_stencil
);
548 depth_surface_type
= BRW_SURFACE_2D
;
549 width
= stencil_irb
->Base
.Base
.Width
;
550 height
= stencil_irb
->Base
.Base
.Height
;
554 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
556 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
558 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
559 depthbuffer_format
, depth_surface_type
,
560 stencil_mt
, hiz
, separate_stencil
,
561 width
, height
, tile_x
, tile_y
);
565 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
566 struct intel_mipmap_tree
*depth_mt
,
567 uint32_t depth_offset
, uint32_t depthbuffer_format
,
568 uint32_t depth_surface_type
,
569 struct intel_mipmap_tree
*stencil_mt
,
570 bool hiz
, bool separate_stencil
,
571 uint32_t width
, uint32_t height
,
572 uint32_t tile_x
, uint32_t tile_y
)
574 /* Enable the hiz bit if we're doing separate stencil, because it and the
575 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
576 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
577 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
578 * Enable must also be enabled.
580 * [DevGT]: This field must be set to the same value (enabled or
581 * disabled) as Hierarchical Depth Buffer Enable
583 bool enable_hiz_ss
= hiz
|| separate_stencil
;
586 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
587 * non-pipelined state that will need the PIPE_CONTROL workaround.
590 intel_emit_post_sync_nonzero_flush(brw
);
591 intel_emit_depth_stall_flushes(brw
);
597 else if (brw
->is_g4x
|| brw
->gen
== 5)
603 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
604 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
605 (depthbuffer_format
<< 18) |
606 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
607 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
608 (BRW_TILEWALK_YMAJOR
<< 26) |
609 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
611 (depth_surface_type
<< 29));
614 OUT_RELOC(depth_mt
->bo
,
615 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
621 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
622 ((height
+ tile_y
- 1) << 19));
625 if (brw
->is_g4x
|| brw
->gen
>= 5)
626 OUT_BATCH(tile_x
| (tile_y
<< 16));
628 assert(tile_x
== 0 && tile_y
== 0);
635 if (hiz
|| separate_stencil
) {
637 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
638 * stencil enable' and 'hiz enable' bits were set. Therefore we must
639 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
640 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
641 * failure to do so causes hangs on gen5 and a stall on gen6.
644 /* Emit hiz buffer. */
646 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_mt
;
648 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
649 OUT_BATCH(hiz_mt
->pitch
- 1);
650 OUT_RELOC(hiz_mt
->bo
,
651 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
652 brw
->depthstencil
.hiz_offset
);
656 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
662 /* Emit stencil buffer. */
663 if (separate_stencil
) {
665 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
666 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
667 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
668 * The pitch must be set to 2x the value computed based on width, as
669 * the stencil buffer is stored with two rows interleaved.
671 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
672 OUT_RELOC(stencil_mt
->bo
,
673 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
674 brw
->depthstencil
.stencil_offset
);
678 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
686 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
687 * params must be emitted.
689 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
690 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
691 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
693 if (brw
->gen
>= 6 || hiz
) {
695 intel_emit_post_sync_nonzero_flush(brw
);
698 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
699 GEN5_DEPTH_CLEAR_VALID
|
701 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
706 const struct brw_tracked_state brw_depthbuffer
= {
708 .mesa
= _NEW_BUFFERS
,
709 .brw
= BRW_NEW_BATCH
,
712 .emit
= brw_emit_depthbuffer
,
717 /***********************************************************************
718 * Polygon stipple packet
721 static void upload_polygon_stipple(struct brw_context
*brw
)
723 struct gl_context
*ctx
= &brw
->ctx
;
727 if (!ctx
->Polygon
.StippleFlag
)
731 intel_emit_post_sync_nonzero_flush(brw
);
734 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
736 /* Polygon stipple is provided in OpenGL order, i.e. bottom
737 * row first. If we're rendering to a window (i.e. the
738 * default frame buffer object, 0), then we need to invert
739 * it to match our pixel layout. But if we're rendering
740 * to a FBO (i.e. any named frame buffer object), we *don't*
741 * need to invert - we already match the layout.
743 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
744 for (i
= 0; i
< 32; i
++)
745 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
748 for (i
= 0; i
< 32; i
++)
749 OUT_BATCH(ctx
->PolygonStipple
[i
]);
754 const struct brw_tracked_state brw_polygon_stipple
= {
756 .mesa
= (_NEW_POLYGONSTIPPLE
|
758 .brw
= BRW_NEW_CONTEXT
,
761 .emit
= upload_polygon_stipple
765 /***********************************************************************
766 * Polygon stipple offset packet
769 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
771 struct gl_context
*ctx
= &brw
->ctx
;
774 if (!ctx
->Polygon
.StippleFlag
)
778 intel_emit_post_sync_nonzero_flush(brw
);
781 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
785 * If we're drawing to a system window we have to invert the Y axis
786 * in order to match the OpenGL pixel coordinate system, and our
787 * offset must be matched to the window position. If we're drawing
788 * to a user-created FBO then our native pixel coordinate system
789 * works just fine, and there's no window system to worry about.
791 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
792 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
798 const struct brw_tracked_state brw_polygon_stipple_offset
= {
800 .mesa
= (_NEW_BUFFERS
|
802 .brw
= BRW_NEW_CONTEXT
,
805 .emit
= upload_polygon_stipple_offset
808 /**********************************************************************
811 static void upload_aa_line_parameters(struct brw_context
*brw
)
813 struct gl_context
*ctx
= &brw
->ctx
;
815 if (!ctx
->Line
.SmoothFlag
)
818 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
819 if (brw
->gen
== 4 && !brw
->is_g4x
)
823 intel_emit_post_sync_nonzero_flush(brw
);
826 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
827 /* use legacy aa line coverage computation */
833 const struct brw_tracked_state brw_aa_line_parameters
= {
836 .brw
= BRW_NEW_CONTEXT
,
839 .emit
= upload_aa_line_parameters
842 /***********************************************************************
843 * Line stipple packet
846 static void upload_line_stipple(struct brw_context
*brw
)
848 struct gl_context
*ctx
= &brw
->ctx
;
852 if (!ctx
->Line
.StippleFlag
)
856 intel_emit_post_sync_nonzero_flush(brw
);
859 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
860 OUT_BATCH(ctx
->Line
.StipplePattern
);
864 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
865 tmpi
= tmp
* (1<<16);
866 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
870 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
871 tmpi
= tmp
* (1<<13);
872 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
878 const struct brw_tracked_state brw_line_stipple
= {
881 .brw
= BRW_NEW_CONTEXT
,
884 .emit
= upload_line_stipple
888 /***********************************************************************
889 * Misc invariant state packets
893 brw_upload_invariant_state(struct brw_context
*brw
)
895 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
897 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
899 intel_emit_post_sync_nonzero_flush(brw
);
901 /* Select the 3D pipeline (as opposed to media) */
902 const uint32_t _3DSTATE_PIPELINE_SELECT
=
903 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
905 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 | 0);
909 /* Disable depth offset clamping. */
911 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
918 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
924 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
929 const uint32_t _3DSTATE_VF_STATISTICS
=
930 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
932 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 |
933 (unlikely(INTEL_DEBUG
& DEBUG_STATS
) ? 1 : 0));
937 const struct brw_tracked_state brw_invariant_state
= {
940 .brw
= BRW_NEW_CONTEXT
,
943 .emit
= brw_upload_invariant_state
947 * Define the base addresses which some state is referenced from.
949 * This allows us to avoid having to emit relocations for the objects,
950 * and is actually required for binding table pointers on gen6.
952 * Surface state base address covers binding table pointers and
953 * surface state objects, but not the surfaces that the surface state
956 static void upload_state_base_address( struct brw_context
*brw
)
958 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
959 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
960 * programmed prior to STATE_BASE_ADDRESS.
962 * However, given that the instruction SBA (general state base
963 * address) on this chipset is always set to 0 across X and GL,
964 * maybe this isn't required for us in particular.
968 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
971 intel_emit_post_sync_nonzero_flush(brw
);
974 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
975 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
976 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
977 1); /* General State Base Address Modify Enable */
978 /* Surface state base address:
979 * BINDING_TABLE_STATE
982 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
983 /* Dynamic state base address:
985 * SAMPLER_BORDER_COLOR_STATE
986 * CLIP, SF, WM/CC viewport state
988 * DEPTH_STENCIL_STATE
990 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
991 * Disable is clear, which we rely on)
993 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
994 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
996 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
997 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
998 1); /* Instruction base address: shader kernels (incl. SIP) */
1000 OUT_BATCH(1); /* General state upper bound */
1001 /* Dynamic state upper bound. Although the documentation says that
1002 * programming it to zero will cause it to be ignored, that is a lie.
1003 * If this isn't programmed to a real bound, the sampler border color
1004 * pointer is rejected, causing border color to mysteriously fail.
1006 OUT_BATCH(0xfffff001);
1007 OUT_BATCH(1); /* Indirect object upper bound */
1008 OUT_BATCH(1); /* Instruction access upper bound */
1010 } else if (brw
->gen
== 5) {
1012 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
1013 OUT_BATCH(1); /* General state base address */
1014 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1015 1); /* Surface state base address */
1016 OUT_BATCH(1); /* Indirect object base address */
1017 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1018 1); /* Instruction base address */
1019 OUT_BATCH(0xfffff001); /* General state upper bound */
1020 OUT_BATCH(1); /* Indirect object upper bound */
1021 OUT_BATCH(1); /* Instruction access upper bound */
1025 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1026 OUT_BATCH(1); /* General state base address */
1027 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1028 1); /* Surface state base address */
1029 OUT_BATCH(1); /* Indirect object base address */
1030 OUT_BATCH(1); /* General state upper bound */
1031 OUT_BATCH(1); /* Indirect object upper bound */
1035 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1036 * STATE_BASE_ADDRESS updates require a reissue of:
1038 * 3DSTATE_PIPELINE_POINTERS
1039 * 3DSTATE_BINDING_TABLE_POINTERS
1040 * MEDIA_STATE_POINTERS
1042 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1043 * 1 part 1 says that the folowing packets must be reissued:
1045 * 3DSTATE_CC_POINTERS
1046 * 3DSTATE_BINDING_TABLE_POINTERS
1047 * 3DSTATE_SAMPLER_STATE_POINTERS
1048 * 3DSTATE_VIEWPORT_STATE_POINTERS
1049 * MEDIA_STATE_POINTERS
1051 * Those are always reissued following SBA updates anyway (new
1052 * batch time), except in the case of the program cache BO
1053 * changing. Having a separate state flag makes the sequence more
1057 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
1060 const struct brw_tracked_state brw_state_base_address
= {
1063 .brw
= (BRW_NEW_BATCH
|
1064 BRW_NEW_PROGRAM_CACHE
),
1067 .emit
= upload_state_base_address