2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
41 #include "compiler/brw_eu_defines.h"
43 #include "main/framebuffer.h"
44 #include "main/fbobject.h"
45 #include "main/glformats.h"
47 /* Constant single cliprect for framebuffer object or DRI2 drawing */
49 upload_drawing_rect(struct brw_context
*brw
)
51 struct gl_context
*ctx
= &brw
->ctx
;
52 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
53 const unsigned int fb_width
= _mesa_geometric_width(fb
);
54 const unsigned int fb_height
= _mesa_geometric_height(fb
);
57 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
58 OUT_BATCH(0); /* xmin, ymin */
59 OUT_BATCH(((fb_width
- 1) & 0xffff) | ((fb_height
- 1) << 16));
64 const struct brw_tracked_state brw_drawing_rect
= {
67 .brw
= BRW_NEW_BLORP
|
70 .emit
= upload_drawing_rect
74 * Upload pointers to the per-stage state.
76 * The state pointers in this packet are all relative to the general state
77 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
80 upload_pipelined_state_pointers(struct brw_context
*brw
)
83 /* Need to flush before changing clip max threads for errata. */
90 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
91 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
92 brw
->vs
.base
.state_offset
);
93 if (brw
->ff_gs
.prog_active
)
94 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
95 brw
->ff_gs
.state_offset
| 1);
98 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
99 brw
->clip
.state_offset
| 1);
100 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
101 brw
->sf
.state_offset
);
102 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
103 brw
->wm
.base
.state_offset
);
104 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
105 brw
->cc
.state_offset
);
108 brw
->ctx
.NewDriverState
|= BRW_NEW_PSP
;
112 upload_psp_urb_cbs(struct brw_context
*brw
)
114 upload_pipelined_state_pointers(brw
);
115 brw_upload_urb_fence(brw
);
116 brw_upload_cs_urb_state(brw
);
119 const struct brw_tracked_state brw_psp_urb_cbs
= {
122 .brw
= BRW_NEW_BATCH
|
124 BRW_NEW_FF_GS_PROG_DATA
|
125 BRW_NEW_GEN4_UNIT_STATE
|
126 BRW_NEW_STATE_BASE_ADDRESS
|
129 .emit
= upload_psp_urb_cbs
,
133 brw_depthbuffer_format(struct brw_context
*brw
)
135 struct gl_context
*ctx
= &brw
->ctx
;
136 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
137 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
138 struct intel_renderbuffer
*srb
;
141 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
142 !srb
->mt
->stencil_mt
&&
143 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
144 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
149 return BRW_DEPTHFORMAT_D32_FLOAT
;
151 return brw_depth_format(brw
, drb
->mt
->format
);
155 * Returns the mask of how many bits of x and y must be handled through the
156 * depthbuffer's draw offset x and y fields.
158 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
159 * between the depth, hiz, and stencil buffers. Because it can be hard to get
160 * all 3 to agree on this value, we want to do as much drawing offset
161 * adjustment as possible by moving the base offset of the 3 buffers, which is
162 * restricted to tile boundaries.
164 * For each buffer, the remainder must be applied through the x/y draw offset.
165 * This returns the worst-case mask of the low bits that have to go into the
166 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
167 * mask, then we're in trouble.
170 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
171 uint32_t depth_level
,
172 uint32_t depth_layer
,
173 struct intel_mipmap_tree
*stencil_mt
,
174 uint32_t *out_tile_mask_x
,
175 uint32_t *out_tile_mask_y
)
177 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
180 intel_get_tile_masks(depth_mt
->tiling
,
182 &tile_mask_x
, &tile_mask_y
);
183 assert(!intel_miptree_level_has_hiz(depth_mt
, depth_level
));
187 if (stencil_mt
->stencil_mt
)
188 stencil_mt
= stencil_mt
->stencil_mt
;
190 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
191 /* Separate stencil buffer uses 64x64 tiles. */
195 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
196 intel_get_tile_masks(stencil_mt
->tiling
,
198 &stencil_tile_mask_x
,
199 &stencil_tile_mask_y
);
201 tile_mask_x
|= stencil_tile_mask_x
;
202 tile_mask_y
|= stencil_tile_mask_y
;
206 *out_tile_mask_x
= tile_mask_x
;
207 *out_tile_mask_y
= tile_mask_y
;
210 static struct intel_mipmap_tree
*
211 get_stencil_miptree(struct intel_renderbuffer
*irb
)
215 if (irb
->mt
->stencil_mt
)
216 return irb
->mt
->stencil_mt
;
221 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
222 GLbitfield clear_mask
)
224 struct gl_context
*ctx
= &brw
->ctx
;
225 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
226 bool rebase_depth
= false;
227 bool rebase_stencil
= false;
228 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
229 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
230 struct intel_mipmap_tree
*depth_mt
= NULL
;
231 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
232 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
233 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
234 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
235 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
238 depth_mt
= depth_irb
->mt
;
240 /* Initialize brw->depthstencil to 'nop' workaround state.
242 brw
->depthstencil
.tile_x
= 0;
243 brw
->depthstencil
.tile_y
= 0;
244 brw
->depthstencil
.depth_offset
= 0;
245 brw
->depthstencil
.stencil_offset
= 0;
246 brw
->depthstencil
.hiz_offset
= 0;
247 brw
->depthstencil
.depth_mt
= NULL
;
248 brw
->depthstencil
.stencil_mt
= NULL
;
250 brw
->depthstencil
.depth_mt
= depth_mt
;
252 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
254 /* Gen6+ doesn't require the workarounds, since we always program the
255 * surface state at the start of the whole surface.
260 /* Check if depth buffer is in depth/stencil format. If so, then it's only
261 * safe to invalidate it if we're also clearing stencil, and both depth_irb
262 * and stencil_irb point to the same miptree.
264 * Note: it's not sufficient to check for the case where
265 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
266 * because this fails to catch depth/stencil buffers on hardware that uses
267 * separate stencil. To catch that case, we check whether
268 * depth_mt->stencil_mt is non-NULL.
270 if (depth_irb
&& invalidate_depth
&&
271 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
272 depth_mt
->stencil_mt
)) {
273 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
274 && depth_irb
->mt
== stencil_irb
->mt
;
277 uint32_t tile_mask_x
, tile_mask_y
;
278 brw_get_depthstencil_tile_masks(depth_mt
,
279 depth_mt
? depth_irb
->mt_level
: 0,
280 depth_mt
? depth_irb
->mt_layer
: 0,
282 &tile_mask_x
, &tile_mask_y
);
285 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
286 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
288 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
289 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
290 * Coordinate Offset X/Y":
292 * "The 3 LSBs of both offsets must be zero to ensure correct
295 if (tile_x
& 7 || tile_y
& 7)
298 /* We didn't even have intra-tile offsets before g45. */
299 if (!brw
->has_surface_tile_offset
) {
300 if (tile_x
|| tile_y
)
305 perf_debug("HW workaround: blitting depth level %d to a temporary "
306 "to fix alignment (depth tile offset %d,%d)\n",
307 depth_irb
->mt_level
, tile_x
, tile_y
);
308 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
309 /* In the case of stencil_irb being the same packed depth/stencil
310 * texture but not the same rb, make it point at our rebased mt, too.
313 stencil_irb
!= depth_irb
&&
314 stencil_irb
->mt
== depth_mt
) {
315 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
316 intel_renderbuffer_set_draw_offset(stencil_irb
);
319 stencil_mt
= get_stencil_miptree(stencil_irb
);
321 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
322 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
326 stencil_mt
= get_stencil_miptree(stencil_irb
);
327 intel_miptree_get_image_offset(stencil_mt
,
328 stencil_irb
->mt_level
,
329 stencil_irb
->mt_layer
,
330 &stencil_draw_x
, &stencil_draw_y
);
331 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
332 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
334 /* If stencil doesn't match depth, then we'll need to rebase stencil
335 * as well. (if we hadn't decided to rebase stencil before, the
336 * post-stencil depth test will also rebase depth to try to match it
339 if (tile_x
!= stencil_tile_x
||
340 tile_y
!= stencil_tile_y
) {
341 rebase_stencil
= true;
346 /* If we have (just) stencil, check it for ignored low bits as well */
348 intel_miptree_get_image_offset(stencil_mt
,
349 stencil_irb
->mt_level
,
350 stencil_irb
->mt_layer
,
351 &stencil_draw_x
, &stencil_draw_y
);
352 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
353 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
355 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
356 rebase_stencil
= true;
358 if (!brw
->has_surface_tile_offset
) {
359 if (stencil_tile_x
|| stencil_tile_y
)
360 rebase_stencil
= true;
364 if (rebase_stencil
) {
365 perf_debug("HW workaround: blitting stencil level %d to a temporary "
366 "to fix alignment (stencil tile offset %d,%d)\n",
367 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
369 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
370 stencil_mt
= get_stencil_miptree(stencil_irb
);
372 intel_miptree_get_image_offset(stencil_mt
,
373 stencil_irb
->mt_level
,
374 stencil_irb
->mt_layer
,
375 &stencil_draw_x
, &stencil_draw_y
);
376 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
377 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
379 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
380 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
381 intel_renderbuffer_set_draw_offset(depth_irb
);
382 } else if (depth_irb
&& !rebase_depth
) {
383 if (tile_x
!= stencil_tile_x
||
384 tile_y
!= stencil_tile_y
) {
385 perf_debug("HW workaround: blitting depth level %d to a temporary "
386 "to match stencil level %d alignment (depth tile offset "
387 "%d,%d, stencil offset %d,%d)\n",
389 stencil_irb
->mt_level
,
391 stencil_tile_x
, stencil_tile_y
);
393 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
395 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
396 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
398 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
399 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
400 intel_renderbuffer_set_draw_offset(stencil_irb
);
403 WARN_ONCE(stencil_tile_x
!= tile_x
||
404 stencil_tile_y
!= tile_y
,
405 "Rebased stencil tile offset (%d,%d) doesn't match depth "
406 "tile offset (%d,%d).\n",
407 stencil_tile_x
, stencil_tile_y
,
414 tile_x
= stencil_tile_x
;
415 tile_y
= stencil_tile_y
;
418 /* While we just tried to get everything aligned, we may have failed to do
419 * so in the case of rendering to array or 3D textures, where nonzero faces
420 * will still have an offset post-rebase. At least give an informative
423 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
424 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
425 "Truncating offset, bad rendering may occur.\n");
429 /* Now, after rebasing, save off the new dephtstencil state so the hardware
430 * packets can just dereference that without re-calculating tile offsets.
432 brw
->depthstencil
.tile_x
= tile_x
;
433 brw
->depthstencil
.tile_y
= tile_y
;
435 depth_mt
= depth_irb
->mt
;
436 brw
->depthstencil
.depth_mt
= depth_mt
;
437 brw
->depthstencil
.depth_offset
=
438 intel_miptree_get_aligned_offset(depth_mt
,
439 depth_irb
->draw_x
& ~tile_mask_x
,
440 depth_irb
->draw_y
& ~tile_mask_y
);
441 if (intel_renderbuffer_has_hiz(depth_irb
)) {
442 brw
->depthstencil
.hiz_offset
=
443 intel_miptree_get_aligned_offset(depth_mt
,
444 depth_irb
->draw_x
& ~tile_mask_x
,
445 (depth_irb
->draw_y
& ~tile_mask_y
) / 2);
449 stencil_mt
= get_stencil_miptree(stencil_irb
);
451 brw
->depthstencil
.stencil_mt
= stencil_mt
;
452 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
453 /* Note: we can't compute the stencil offset using
454 * intel_region_get_aligned_offset(), because stencil_region claims
455 * that the region is untiled even though it's W tiled.
457 brw
->depthstencil
.stencil_offset
=
458 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
459 (stencil_draw_x
& ~tile_mask_x
) * 64;
465 brw_emit_depthbuffer(struct brw_context
*brw
)
467 struct gl_context
*ctx
= &brw
->ctx
;
468 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
470 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
471 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
472 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
473 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
474 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
475 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
476 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
477 bool separate_stencil
= false;
478 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
479 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
480 uint32_t depth_offset
= 0;
481 uint32_t width
= 1, height
= 1;
484 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
486 /* Gen7 supports only separate stencil */
487 assert(separate_stencil
|| brw
->gen
< 7);
490 /* If there's a packed depth/stencil bound to stencil only, we need to
491 * emit the packed depth/stencil buffer packet.
493 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
494 depth_irb
= stencil_irb
;
495 depth_mt
= stencil_mt
;
498 if (depth_irb
&& depth_mt
) {
499 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
500 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
501 * depthstencil format.
503 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
504 * set to the same value. Gens after 7 implicitly always set
505 * Separate_Stencil_Enable; software cannot disable it.
507 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
508 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
511 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
512 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
514 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
515 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
517 depthbuffer_format
= brw_depthbuffer_format(brw
);
518 depth_surface_type
= BRW_SURFACE_2D
;
519 depth_offset
= brw
->depthstencil
.depth_offset
;
520 width
= depth_irb
->Base
.Base
.Width
;
521 height
= depth_irb
->Base
.Base
.Height
;
522 } else if (separate_stencil
) {
524 * There exists a separate stencil buffer but no depth buffer.
526 * The stencil buffer inherits most of its fields from
527 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
530 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
531 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
532 * [DevGT+]: This field must be set to TRUE.
534 assert(brw
->has_separate_stencil
);
536 depth_surface_type
= BRW_SURFACE_2D
;
537 width
= stencil_irb
->Base
.Base
.Width
;
538 height
= stencil_irb
->Base
.Base
.Height
;
542 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
544 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
546 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
547 depthbuffer_format
, depth_surface_type
,
548 stencil_mt
, hiz
, separate_stencil
,
549 width
, height
, tile_x
, tile_y
);
553 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
554 struct intel_mipmap_tree
*depth_mt
,
555 uint32_t depth_offset
, uint32_t depthbuffer_format
,
556 uint32_t depth_surface_type
,
557 struct intel_mipmap_tree
*stencil_mt
,
558 bool hiz
, bool separate_stencil
,
559 uint32_t width
, uint32_t height
,
560 uint32_t tile_x
, uint32_t tile_y
)
562 /* Enable the hiz bit if we're doing separate stencil, because it and the
563 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
564 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
565 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
566 * Enable must also be enabled.
568 * [DevGT]: This field must be set to the same value (enabled or
569 * disabled) as Hierarchical Depth Buffer Enable
571 bool enable_hiz_ss
= hiz
|| separate_stencil
;
574 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
575 * non-pipelined state that will need the PIPE_CONTROL workaround.
578 brw_emit_depth_stall_flushes(brw
);
584 else if (brw
->is_g4x
|| brw
->gen
== 5)
590 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
591 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
592 (depthbuffer_format
<< 18) |
593 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
594 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
595 (BRW_TILEWALK_YMAJOR
<< 26) |
596 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
598 (depth_surface_type
<< 29));
601 OUT_RELOC(depth_mt
->bo
,
602 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
608 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
609 ((height
+ tile_y
- 1) << 19));
612 if (brw
->is_g4x
|| brw
->gen
>= 5)
613 OUT_BATCH(tile_x
| (tile_y
<< 16));
615 assert(tile_x
== 0 && tile_y
== 0);
622 if (hiz
|| separate_stencil
) {
624 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
625 * stencil enable' and 'hiz enable' bits were set. Therefore we must
626 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
627 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
628 * failure to do so causes hangs on gen5 and a stall on gen6.
631 /* Emit hiz buffer. */
635 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
636 OUT_BATCH(depth_mt
->hiz_buf
->aux_base
.pitch
- 1);
637 OUT_RELOC(depth_mt
->hiz_buf
->aux_base
.bo
,
638 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
639 brw
->depthstencil
.hiz_offset
);
643 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
649 /* Emit stencil buffer. */
650 if (separate_stencil
) {
652 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
653 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
654 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
655 * The pitch must be set to 2x the value computed based on width, as
656 * the stencil buffer is stored with two rows interleaved.
658 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
659 OUT_RELOC(stencil_mt
->bo
,
660 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
661 brw
->depthstencil
.stencil_offset
);
665 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
673 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
674 * params must be emitted.
676 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
677 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
678 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
680 if (brw
->gen
>= 6 || hiz
) {
682 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
683 GEN5_DEPTH_CLEAR_VALID
|
685 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
690 const struct brw_tracked_state brw_depthbuffer
= {
692 .mesa
= _NEW_BUFFERS
,
693 .brw
= BRW_NEW_BATCH
|
696 .emit
= brw_emit_depthbuffer
,
700 * Polygon stipple packet
703 upload_polygon_stipple(struct brw_context
*brw
)
705 struct gl_context
*ctx
= &brw
->ctx
;
709 if (!ctx
->Polygon
.StippleFlag
)
713 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
715 /* Polygon stipple is provided in OpenGL order, i.e. bottom
716 * row first. If we're rendering to a window (i.e. the
717 * default frame buffer object, 0), then we need to invert
718 * it to match our pixel layout. But if we're rendering
719 * to a FBO (i.e. any named frame buffer object), we *don't*
720 * need to invert - we already match the layout.
722 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
723 for (i
= 0; i
< 32; i
++)
724 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
726 for (i
= 0; i
< 32; i
++)
727 OUT_BATCH(ctx
->PolygonStipple
[i
]);
732 const struct brw_tracked_state brw_polygon_stipple
= {
734 .mesa
= _NEW_POLYGON
|
736 .brw
= BRW_NEW_CONTEXT
,
738 .emit
= upload_polygon_stipple
742 * Polygon stipple offset packet
745 upload_polygon_stipple_offset(struct brw_context
*brw
)
747 struct gl_context
*ctx
= &brw
->ctx
;
750 if (!ctx
->Polygon
.StippleFlag
)
754 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
758 * If we're drawing to a system window we have to invert the Y axis
759 * in order to match the OpenGL pixel coordinate system, and our
760 * offset must be matched to the window position. If we're drawing
761 * to a user-created FBO then our native pixel coordinate system
762 * works just fine, and there's no window system to worry about.
764 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
765 OUT_BATCH((32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31);
771 const struct brw_tracked_state brw_polygon_stipple_offset
= {
773 .mesa
= _NEW_BUFFERS
|
775 .brw
= BRW_NEW_CONTEXT
,
777 .emit
= upload_polygon_stipple_offset
781 * Line stipple packet
784 upload_line_stipple(struct brw_context
*brw
)
786 struct gl_context
*ctx
= &brw
->ctx
;
790 if (!ctx
->Line
.StippleFlag
)
794 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
795 OUT_BATCH(ctx
->Line
.StipplePattern
);
799 tmp
= 1.0f
/ ctx
->Line
.StippleFactor
;
800 tmpi
= tmp
* (1<<16);
801 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
804 tmp
= 1.0f
/ ctx
->Line
.StippleFactor
;
805 tmpi
= tmp
* (1<<13);
806 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
812 const struct brw_tracked_state brw_line_stipple
= {
815 .brw
= BRW_NEW_CONTEXT
,
817 .emit
= upload_line_stipple
821 brw_emit_select_pipeline(struct brw_context
*brw
, enum brw_pipeline pipeline
)
823 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
824 const uint32_t _3DSTATE_PIPELINE_SELECT
=
825 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
827 if (brw
->gen
>= 8 && brw
->gen
< 10) {
828 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
830 * Software must clear the COLOR_CALC_STATE Valid field in
831 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
832 * with Pipeline Select set to GPGPU.
834 * The internal hardware docs recommend the same workaround for Gen9
837 if (pipeline
== BRW_COMPUTE_PIPELINE
) {
839 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
843 brw
->ctx
.NewDriverState
|= BRW_NEW_CC_STATE
;
848 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
849 * PIPELINE_SELECT [DevBWR+]":
853 * Software must ensure all the write caches are flushed through a
854 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
855 * command to invalidate read only caches prior to programming
856 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
858 const unsigned dc_flush
=
859 brw
->gen
>= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH
: 0;
861 brw_emit_pipe_control_flush(brw
,
862 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
863 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
865 PIPE_CONTROL_NO_WRITE
|
866 PIPE_CONTROL_CS_STALL
);
868 brw_emit_pipe_control_flush(brw
,
869 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
870 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
871 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
872 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
873 PIPE_CONTROL_NO_WRITE
);
876 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
877 * PIPELINE_SELECT [DevBWR+]":
879 * Project: PRE-DEVSNB
881 * Software must ensure the current pipeline is flushed via an
882 * MI_FLUSH or PIPE_CONTROL prior to the execution of PIPELINE_SELECT.
889 /* Select the pipeline */
891 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 |
892 (brw
->gen
>= 9 ? (3 << 8) : 0) |
893 (pipeline
== BRW_COMPUTE_PIPELINE
? 2 : 0));
896 if (brw
->gen
== 7 && !brw
->is_haswell
&&
897 pipeline
== BRW_RENDER_PIPELINE
) {
898 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
899 * PIPELINE_SELECT [DevBWR+]":
901 * Project: DEVIVB, DEVHSW:GT3:A0
903 * Software must send a pipe_control with a CS stall and a post sync
904 * operation and then a dummy DRAW after every MI_SET_CONTEXT and
905 * after any PIPELINE_SELECT that is enabling 3D mode.
907 gen7_emit_cs_stall_flush(brw
);
910 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2));
911 OUT_BATCH(_3DPRIM_POINTLIST
);
922 * Misc invariant state packets
925 brw_upload_invariant_state(struct brw_context
*brw
)
927 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
929 brw_emit_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
930 brw
->last_pipeline
= BRW_RENDER_PIPELINE
;
934 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
940 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
945 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
948 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
949 /* use legacy aa line coverage computation */
955 const uint32_t _3DSTATE_VF_STATISTICS
=
956 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
958 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 | 1);
962 const struct brw_tracked_state brw_invariant_state
= {
965 .brw
= BRW_NEW_BLORP
|
968 .emit
= brw_upload_invariant_state
972 * Define the base addresses which some state is referenced from.
974 * This allows us to avoid having to emit relocations for the objects,
975 * and is actually required for binding table pointers on gen6.
977 * Surface state base address covers binding table pointers and
978 * surface state objects, but not the surfaces that the surface state
982 brw_upload_state_base_address(struct brw_context
*brw
)
984 if (brw
->batch
.state_base_address_emitted
)
987 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
988 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
989 * programmed prior to STATE_BASE_ADDRESS.
991 * However, given that the instruction SBA (general state base
992 * address) on this chipset is always set to 0 across X and GL,
993 * maybe this isn't required for us in particular.
997 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
998 int pkt_len
= brw
->gen
>= 9 ? 19 : 16;
1000 BEGIN_BATCH(pkt_len
);
1001 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (pkt_len
- 2));
1002 /* General state base address: stateless DP read/write requests */
1003 OUT_BATCH(mocs_wb
<< 4 | 1);
1005 OUT_BATCH(mocs_wb
<< 16);
1006 /* Surface state base address: */
1007 OUT_RELOC64(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1009 /* Dynamic state base address: */
1010 OUT_RELOC64(brw
->batch
.bo
,
1011 I915_GEM_DOMAIN_RENDER
| I915_GEM_DOMAIN_INSTRUCTION
, 0,
1013 /* Indirect object base address: MEDIA_OBJECT data */
1014 OUT_BATCH(mocs_wb
<< 4 | 1);
1016 /* Instruction base address: shader kernels (incl. SIP) */
1017 OUT_RELOC64(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1020 /* General state buffer size */
1021 OUT_BATCH(0xfffff001);
1022 /* Dynamic state buffer size */
1023 OUT_BATCH(ALIGN(brw
->batch
.bo
->size
, 4096) | 1);
1024 /* Indirect object upper bound */
1025 OUT_BATCH(0xfffff001);
1026 /* Instruction access upper bound */
1027 OUT_BATCH(ALIGN(brw
->cache
.bo
->size
, 4096) | 1);
1028 if (brw
->gen
>= 9) {
1034 } else if (brw
->gen
>= 6) {
1035 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
1038 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
1039 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
1040 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
1041 1); /* General State Base Address Modify Enable */
1042 /* Surface state base address:
1043 * BINDING_TABLE_STATE
1046 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
1047 /* Dynamic state base address:
1049 * SAMPLER_BORDER_COLOR_STATE
1050 * CLIP, SF, WM/CC viewport state
1052 * DEPTH_STENCIL_STATE
1054 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
1055 * Disable is clear, which we rely on)
1057 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
1058 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
1060 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
1061 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1062 1); /* Instruction base address: shader kernels (incl. SIP) */
1064 OUT_BATCH(1); /* General state upper bound */
1065 /* Dynamic state upper bound. Although the documentation says that
1066 * programming it to zero will cause it to be ignored, that is a lie.
1067 * If this isn't programmed to a real bound, the sampler border color
1068 * pointer is rejected, causing border color to mysteriously fail.
1070 OUT_BATCH(0xfffff001);
1071 OUT_BATCH(1); /* Indirect object upper bound */
1072 OUT_BATCH(1); /* Instruction access upper bound */
1074 } else if (brw
->gen
== 5) {
1076 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
1077 OUT_BATCH(1); /* General state base address */
1078 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1079 1); /* Surface state base address */
1080 OUT_BATCH(1); /* Indirect object base address */
1081 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1082 1); /* Instruction base address */
1083 OUT_BATCH(0xfffff001); /* General state upper bound */
1084 OUT_BATCH(1); /* Indirect object upper bound */
1085 OUT_BATCH(1); /* Instruction access upper bound */
1089 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1090 OUT_BATCH(1); /* General state base address */
1091 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1092 1); /* Surface state base address */
1093 OUT_BATCH(1); /* Indirect object base address */
1094 OUT_BATCH(1); /* General state upper bound */
1095 OUT_BATCH(1); /* Indirect object upper bound */
1099 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1100 * STATE_BASE_ADDRESS updates require a reissue of:
1102 * 3DSTATE_PIPELINE_POINTERS
1103 * 3DSTATE_BINDING_TABLE_POINTERS
1104 * MEDIA_STATE_POINTERS
1106 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1107 * 1 part 1 says that the folowing packets must be reissued:
1109 * 3DSTATE_CC_POINTERS
1110 * 3DSTATE_BINDING_TABLE_POINTERS
1111 * 3DSTATE_SAMPLER_STATE_POINTERS
1112 * 3DSTATE_VIEWPORT_STATE_POINTERS
1113 * MEDIA_STATE_POINTERS
1115 * Those are always reissued following SBA updates anyway (new
1116 * batch time), except in the case of the program cache BO
1117 * changing. Having a separate state flag makes the sequence more
1121 brw
->ctx
.NewDriverState
|= BRW_NEW_STATE_BASE_ADDRESS
;
1122 brw
->batch
.state_base_address_emitted
= true;