src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "intel_mipmap_tree.h"
  37 #include "intel_regions.h"
  38
  39 #include "brw_context.h"
  40 #include "brw_state.h"
  41 #include "brw_defines.h"
  42
  43 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  44 static void upload_drawing_rect(struct brw_context *brw)
  45 {
  46    struct intel_context *intel = &brw->intel;
  47    struct gl_context *ctx = &intel->ctx;
  48
  49    BEGIN_BATCH(4);
  50    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
  51    OUT_BATCH(0); /* xmin, ymin */
  52    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  53             ((ctx->DrawBuffer->Height - 1) << 16));
  54    OUT_BATCH(0);
  55    ADVANCE_BATCH();
  56 }
  57
  58 const struct brw_tracked_state brw_drawing_rect = {
  59    .dirty = {
  60       .mesa = _NEW_BUFFERS,
  61       .brw = BRW_NEW_CONTEXT,
  62       .cache = 0
  63    },
  64    .emit = upload_drawing_rect
  65 };
  66
  67 /**
  68  * Upload the binding table pointers, which point each stage's array of surface
  69  * state pointers.
  70  *
  71  * The binding table pointers are relative to the surface state base address,
  72  * which points at the batchbuffer containing the streamed batch state.
  73  */
  74 static void upload_binding_table_pointers(struct brw_context *brw)
  75 {
  76    struct intel_context *intel = &brw->intel;
  77
  78    BEGIN_BATCH(6);
  79    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
  80    OUT_BATCH(brw->bind.bo_offset);
  81    OUT_BATCH(0); /* gs */
  82    OUT_BATCH(0); /* clip */
  83    OUT_BATCH(0); /* sf */
  84    OUT_BATCH(brw->bind.bo_offset);
  85    ADVANCE_BATCH();
  86 }
  87
  88 const struct brw_tracked_state brw_binding_table_pointers = {
  89    .dirty = {
  90       .mesa = 0,
  91       .brw = (BRW_NEW_BATCH |
  92               BRW_NEW_STATE_BASE_ADDRESS |
  93               BRW_NEW_VS_BINDING_TABLE |
  94               BRW_NEW_GS_BINDING_TABLE |
  95               BRW_NEW_PS_BINDING_TABLE),
  96       .cache = 0,
  97    },
  98    .emit = upload_binding_table_pointers,
  99 };
 100
 101 /**
 102  * Upload the binding table pointers, which point each stage's array of surface
 103  * state pointers.
 104  *
 105  * The binding table pointers are relative to the surface state base address,
 106  * which points at the batchbuffer containing the streamed batch state.
 107  */
 108 static void upload_gen6_binding_table_pointers(struct brw_context *brw)
 109 {
 110    struct intel_context *intel = &brw->intel;
 111
 112    BEGIN_BATCH(4);
 113    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 114              GEN6_BINDING_TABLE_MODIFY_VS |
 115              GEN6_BINDING_TABLE_MODIFY_GS |
 116              GEN6_BINDING_TABLE_MODIFY_PS |
 117              (4 - 2));
 118    OUT_BATCH(brw->bind.bo_offset); /* vs */
 119    OUT_BATCH(0); /* gs */
 120    OUT_BATCH(brw->bind.bo_offset); /* wm/ps */
 121    ADVANCE_BATCH();
 122 }
 123
 124 const struct brw_tracked_state gen6_binding_table_pointers = {
 125    .dirty = {
 126       .mesa = 0,
 127       .brw = (BRW_NEW_BATCH |
 128               BRW_NEW_STATE_BASE_ADDRESS |
 129               BRW_NEW_VS_BINDING_TABLE |
 130               BRW_NEW_GS_BINDING_TABLE |
 131               BRW_NEW_PS_BINDING_TABLE),
 132       .cache = 0,
 133    },
 134    .emit = upload_gen6_binding_table_pointers,
 135 };
 136
 137 /**
 138  * Upload pointers to the per-stage state.
 139  *
 140  * The state pointers in this packet are all relative to the general state
 141  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 142  */
 143 static void upload_pipelined_state_pointers(struct brw_context *brw )
 144 {
 145    struct intel_context *intel = &brw->intel;
 146
 147    if (intel->gen == 5) {
 148       /* Need to flush before changing clip max threads for errata. */
 149       BEGIN_BATCH(1);
 150       OUT_BATCH(MI_FLUSH);
 151       ADVANCE_BATCH();
 152    }
 153
 154    BEGIN_BATCH(7);
 155    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
 156    OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 157              brw->vs.state_offset);
 158    if (brw->gs.prog_active)
 159       OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 160                 brw->gs.state_offset | 1);
 161    else
 162       OUT_BATCH(0);
 163    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 164              brw->clip.state_offset | 1);
 165    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 166              brw->sf.state_offset);
 167    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 168              brw->wm.state_offset);
 169    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 170              brw->cc.state_offset);
 171    ADVANCE_BATCH();
 172
 173    brw->state.dirty.brw |= BRW_NEW_PSP;
 174 }
 175
 176 static void upload_psp_urb_cbs(struct brw_context *brw )
 177 {
 178    upload_pipelined_state_pointers(brw);
 179    brw_upload_urb_fence(brw);
 180    brw_upload_cs_urb_state(brw);
 181 }
 182
 183 const struct brw_tracked_state brw_psp_urb_cbs = {
 184    .dirty = {
 185       .mesa = 0,
 186       .brw = (BRW_NEW_URB_FENCE |
 187               BRW_NEW_BATCH |
 188               BRW_NEW_STATE_BASE_ADDRESS),
 189       .cache = (CACHE_NEW_VS_UNIT |
 190                 CACHE_NEW_GS_UNIT |
 191                 CACHE_NEW_GS_PROG |
 192                 CACHE_NEW_CLIP_UNIT |
 193                 CACHE_NEW_SF_UNIT |
 194                 CACHE_NEW_WM_UNIT |
 195                 CACHE_NEW_CC_UNIT)
 196    },
 197    .emit = upload_psp_urb_cbs,
 198 };
 199
 200 uint32_t
 201 brw_depthbuffer_format(struct brw_context *brw)
 202 {
 203    struct intel_context *intel = &brw->intel;
 204    struct gl_context *ctx = &intel->ctx;
 205    struct gl_framebuffer *fb = ctx->DrawBuffer;
 206    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 207    struct intel_renderbuffer *srb;
 208
 209    if (!drb &&
 210        (srb = intel_get_renderbuffer(fb, BUFFER_STENCIL)) &&
 211        !srb->mt->stencil_mt &&
 212        srb->Base.Format == MESA_FORMAT_S8_Z24) {
 213       drb = srb;
 214    }
 215
 216    if (!drb)
 217       return BRW_DEPTHFORMAT_D32_FLOAT;
 218
 219    switch (drb->Base.Format) {
 220    case MESA_FORMAT_Z16:
 221       return BRW_DEPTHFORMAT_D16_UNORM;
 222    case MESA_FORMAT_Z32_FLOAT:
 223       return BRW_DEPTHFORMAT_D32_FLOAT;
 224    case MESA_FORMAT_X8_Z24:
 225       return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 226    case MESA_FORMAT_S8_Z24:
 227       return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 228    default:
 229       _mesa_problem(ctx, "Unexpected depth format %s\n",
 230                     _mesa_get_format_name(drb->Base.Format));
 231       return BRW_DEPTHFORMAT_D16_UNORM;
 232    }
 233 }
 234
 235 static void emit_depthbuffer(struct brw_context *brw)
 236 {
 237    struct intel_context *intel = &brw->intel;
 238    struct gl_context *ctx = &intel->ctx;
 239    struct gl_framebuffer *fb = ctx->DrawBuffer;
 240    /* _NEW_BUFFERS */
 241    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 242    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 243    struct intel_mipmap_tree *stencil_mt = NULL;
 244    struct intel_region *hiz_region = NULL;
 245    unsigned int len;
 246    bool separate_stencil = false;
 247
 248    if (depth_irb &&
 249        depth_irb->mt &&
 250        depth_irb->mt->hiz_mt) {
 251       hiz_region = depth_irb->mt->hiz_mt->region;
 252    }
 253
 254    /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
 255     * non-pipelined state that will need the PIPE_CONTROL workaround.
 256     */
 257    if (intel->gen == 6) {
 258       intel_emit_post_sync_nonzero_flush(intel);
 259       intel_emit_depth_stall_flushes(intel);
 260    }
 261
 262    /* Find the real separate stencil mt if present. */
 263    if (stencil_irb) {
 264       stencil_mt = stencil_irb->mt;
 265       if (stencil_mt->stencil_mt)
 266          stencil_mt = stencil_mt->stencil_mt;
 267
 268       if (stencil_mt->format == MESA_FORMAT_S8)
 269          separate_stencil = true;
 270    }
 271
 272    /* If there's a packed depth/stencil bound to stencil only, we need to
 273     * emit the packed depth/stencil buffer packet.
 274     */
 275    if (!depth_irb && stencil_irb && !separate_stencil)
 276       depth_irb = stencil_irb;
 277
 278    if (intel->gen >= 6)
 279       len = 7;
 280    else if (intel->is_g4x || intel->gen == 5)
 281       len = 6;
 282    else
 283       len = 5;
 284
 285    if (!depth_irb && !separate_stencil) {
 286       BEGIN_BATCH(len);
 287       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 288       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 289                 (BRW_SURFACE_NULL << 29));
 290       OUT_BATCH(0);
 291       OUT_BATCH(0);
 292       OUT_BATCH(0);
 293
 294       if (intel->is_g4x || intel->gen >= 5)
 295          OUT_BATCH(0);
 296
 297       if (intel->gen >= 6)
 298          OUT_BATCH(0);
 299
 300       ADVANCE_BATCH();
 301
 302    } else if (!depth_irb && separate_stencil) {
 303       /*
 304        * There exists a separate stencil buffer but no depth buffer.
 305        *
 306        * The stencil buffer inherits most of its fields from
 307        * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
 308        * height.
 309        *
 310        * Since the stencil buffer has quirky pitch requirements, its region
 311        * was allocated with half height and double cpp. So we need
 312        * a multiplier of 2 to obtain the surface's real height.
 313        *
 314        * Enable the hiz bit because it and the separate stencil bit must have
 315        * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
 316        * 1.21 "Separate Stencil Enable":
 317        *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
 318        *     Enable must also be enabled.
 319        *
 320        *     [DevGT]: This field must be set to the same value (enabled or
 321        *     disabled) as Hierarchical Depth Buffer Enable
 322        *
 323        * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
 324        * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
 325        *     [DevGT+]: This field must be set to TRUE.
 326        */
 327       struct intel_region *region = stencil_mt->region;
 328
 329       assert(intel->has_separate_stencil);
 330
 331       BEGIN_BATCH(len);
 332       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 333       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 334                 (1 << 21) | /* separate stencil enable */
 335                 (1 << 22) | /* hiz enable */
 336                 (BRW_TILEWALK_YMAJOR << 26) |
 337                 (1 << 27) | /* tiled surface */
 338                 (BRW_SURFACE_2D << 29));
 339       OUT_BATCH(0);
 340       OUT_BATCH(((region->width - 1) << 6) |
 341                  (2 * region->height - 1) << 19);
 342       OUT_BATCH(0);
 343       OUT_BATCH(0);
 344
 345       if (intel->gen >= 6)
 346          OUT_BATCH(0);
 347
 348       ADVANCE_BATCH();
 349
 350    } else {
 351       struct intel_region *region = depth_irb->mt->region;
 352       uint32_t tile_x, tile_y, offset;
 353
 354       /* If using separate stencil, hiz must be enabled. */
 355       assert(!separate_stencil || hiz_region);
 356
 357       offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y);
 358
 359       assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
 360       assert(!hiz_region || region->tiling == I915_TILING_Y);
 361
 362       BEGIN_BATCH(len);
 363       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 364       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 365                 (brw_depthbuffer_format(brw) << 18) |
 366                 ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */
 367                 ((hiz_region ? 1 : 0) << 22) | /* hiz enable */
 368                 (BRW_TILEWALK_YMAJOR << 26) |
 369                 ((region->tiling != I915_TILING_NONE) << 27) |
 370                 (BRW_SURFACE_2D << 29));
 371       OUT_RELOC(region->bo,
 372                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 373                 offset);
 374       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 375                 ((region->width - 1) << 6) |
 376                 ((region->height - 1) << 19));
 377       OUT_BATCH(0);
 378
 379       if (intel->is_g4x || intel->gen >= 5)
 380          OUT_BATCH(tile_x | (tile_y << 16));
 381       else
 382          assert(tile_x == 0 && tile_y == 0);
 383
 384       if (intel->gen >= 6)
 385          OUT_BATCH(0);
 386
 387       ADVANCE_BATCH();
 388    }
 389
 390    if (hiz_region || separate_stencil) {
 391       /*
 392        * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
 393        * stencil enable' and 'hiz enable' bits were set. Therefore we must
 394        * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
 395        * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
 396        * failure to do so causes hangs on gen5 and a stall on gen6.
 397        */
 398
 399       /* Emit hiz buffer. */
 400       if (hiz_region) {
 401          BEGIN_BATCH(3);
 402          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 403          OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 404          OUT_RELOC(hiz_region->bo,
 405                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 406                    0);
 407          ADVANCE_BATCH();
 408       } else {
 409          BEGIN_BATCH(3);
 410          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 411          OUT_BATCH(0);
 412          OUT_BATCH(0);
 413          ADVANCE_BATCH();
 414       }
 415
 416       /* Emit stencil buffer. */
 417       if (separate_stencil) {
 418          struct intel_region *region = stencil_mt->region;
 419          BEGIN_BATCH(3);
 420          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 421          OUT_BATCH(region->pitch * region->cpp - 1);
 422          OUT_RELOC(region->bo,
 423                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 424                    0);
 425          ADVANCE_BATCH();
 426       } else {
 427          BEGIN_BATCH(3);
 428          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 429          OUT_BATCH(0);
 430          OUT_BATCH(0);
 431          ADVANCE_BATCH();
 432       }
 433    }
 434
 435    /*
 436     * On Gen >= 6, emit clear params for safety. If using hiz, then clear
 437     * params must be emitted.
 438     *
 439     * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
 440     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
 441     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 442     */
 443    if (intel->gen >= 6 || hiz_region) {
 444       if (intel->gen == 6)
 445          intel_emit_post_sync_nonzero_flush(intel);
 446
 447       BEGIN_BATCH(2);
 448       OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
 449       OUT_BATCH(0);
 450       ADVANCE_BATCH();
 451    }
 452 }
 453
 454 const struct brw_tracked_state brw_depthbuffer = {
 455    .dirty = {
 456       .mesa = _NEW_BUFFERS,
 457       .brw = BRW_NEW_BATCH,
 458       .cache = 0,
 459    },
 460    .emit = emit_depthbuffer,
 461 };
 462
 463
 464
 465 /***********************************************************************
 466  * Polygon stipple packet
 467  */
 468
 469 static void upload_polygon_stipple(struct brw_context *brw)
 470 {
 471    struct intel_context *intel = &brw->intel;
 472    struct gl_context *ctx = &brw->intel.ctx;
 473    GLuint i;
 474
 475    /* _NEW_POLYGON */
 476    if (!ctx->Polygon.StippleFlag)
 477       return;
 478
 479    if (intel->gen == 6)
 480       intel_emit_post_sync_nonzero_flush(intel);
 481
 482    BEGIN_BATCH(33);
 483    OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
 484
 485    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 486     * row first.  If we're rendering to a window (i.e. the
 487     * default frame buffer object, 0), then we need to invert
 488     * it to match our pixel layout.  But if we're rendering
 489     * to a FBO (i.e. any named frame buffer object), we *don't*
 490     * need to invert - we already match the layout.
 491     */
 492    if (ctx->DrawBuffer->Name == 0) {
 493       for (i = 0; i < 32; i++)
 494           OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
 495    }
 496    else {
 497       for (i = 0; i < 32; i++)
 498          OUT_BATCH(ctx->PolygonStipple[i]);
 499    }
 500    CACHED_BATCH();
 501 }
 502
 503 const struct brw_tracked_state brw_polygon_stipple = {
 504    .dirty = {
 505       .mesa = (_NEW_POLYGONSTIPPLE |
 506                _NEW_POLYGON),
 507       .brw = BRW_NEW_CONTEXT,
 508       .cache = 0
 509    },
 510    .emit = upload_polygon_stipple
 511 };
 512
 513
 514 /***********************************************************************
 515  * Polygon stipple offset packet
 516  */
 517
 518 static void upload_polygon_stipple_offset(struct brw_context *brw)
 519 {
 520    struct intel_context *intel = &brw->intel;
 521    struct gl_context *ctx = &brw->intel.ctx;
 522
 523    /* _NEW_POLYGON */
 524    if (!ctx->Polygon.StippleFlag)
 525       return;
 526
 527    if (intel->gen == 6)
 528       intel_emit_post_sync_nonzero_flush(intel);
 529
 530    BEGIN_BATCH(2);
 531    OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
 532
 533    /* _NEW_BUFFERS
 534     *
 535     * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 536     * we have to invert the Y axis in order to match the OpenGL
 537     * pixel coordinate system, and our offset must be matched
 538     * to the window position.  If we're drawing to a FBO
 539     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 540     * system works just fine, and there's no window system to
 541     * worry about.
 542     */
 543    if (brw->intel.ctx.DrawBuffer->Name == 0)
 544       OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
 545    else
 546       OUT_BATCH(0);
 547    CACHED_BATCH();
 548 }
 549
 550 const struct brw_tracked_state brw_polygon_stipple_offset = {
 551    .dirty = {
 552       .mesa = (_NEW_BUFFERS |
 553                _NEW_POLYGON),
 554       .brw = BRW_NEW_CONTEXT,
 555       .cache = 0
 556    },
 557    .emit = upload_polygon_stipple_offset
 558 };
 559
 560 /**********************************************************************
 561  * AA Line parameters
 562  */
 563 static void upload_aa_line_parameters(struct brw_context *brw)
 564 {
 565    struct intel_context *intel = &brw->intel;
 566    struct gl_context *ctx = &brw->intel.ctx;
 567
 568    if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
 569       return;
 570
 571    if (intel->gen == 6)
 572       intel_emit_post_sync_nonzero_flush(intel);
 573
 574    OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
 575    /* use legacy aa line coverage computation */
 576    OUT_BATCH(0);
 577    OUT_BATCH(0);
 578    CACHED_BATCH();
 579 }
 580
 581 const struct brw_tracked_state brw_aa_line_parameters = {
 582    .dirty = {
 583       .mesa = _NEW_LINE,
 584       .brw = BRW_NEW_CONTEXT,
 585       .cache = 0
 586    },
 587    .emit = upload_aa_line_parameters
 588 };
 589
 590 /***********************************************************************
 591  * Line stipple packet
 592  */
 593
 594 static void upload_line_stipple(struct brw_context *brw)
 595 {
 596    struct intel_context *intel = &brw->intel;
 597    struct gl_context *ctx = &brw->intel.ctx;
 598    GLfloat tmp;
 599    GLint tmpi;
 600
 601    if (!ctx->Line.StippleFlag)
 602       return;
 603
 604    if (intel->gen == 6)
 605       intel_emit_post_sync_nonzero_flush(intel);
 606
 607    BEGIN_BATCH(3);
 608    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
 609    OUT_BATCH(ctx->Line.StipplePattern);
 610    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 611    tmpi = tmp * (1<<13);
 612    OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
 613    CACHED_BATCH();
 614 }
 615
 616 const struct brw_tracked_state brw_line_stipple = {
 617    .dirty = {
 618       .mesa = _NEW_LINE,
 619       .brw = BRW_NEW_CONTEXT,
 620       .cache = 0
 621    },
 622    .emit = upload_line_stipple
 623 };
 624
 625
 626 /***********************************************************************
 627  * Misc invarient state packets
 628  */
 629
 630 static void upload_invarient_state( struct brw_context *brw )
 631 {
 632    struct intel_context *intel = &brw->intel;
 633
 634    /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
 635    if (intel->gen == 6)
 636       intel_emit_post_sync_nonzero_flush(intel);
 637
 638    /* Select the 3D pipeline (as opposed to media) */
 639    BEGIN_BATCH(1);
 640    OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0);
 641    ADVANCE_BATCH();
 642
 643    if (intel->gen < 6) {
 644       /* Disable depth offset clamping. */
 645       BEGIN_BATCH(2);
 646       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
 647       OUT_BATCH_F(0.0);
 648       ADVANCE_BATCH();
 649    }
 650
 651    if (intel->gen >= 6) {
 652       int i;
 653       int len = intel->gen >= 7 ? 4 : 3;
 654
 655       BEGIN_BATCH(len);
 656       OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
 657       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
 658                 MS_NUMSAMPLES_1);
 659       OUT_BATCH(0); /* positions for 4/8-sample */
 660       if (intel->gen >= 7)
 661          OUT_BATCH(0);
 662       ADVANCE_BATCH();
 663
 664       BEGIN_BATCH(2);
 665       OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
 666       OUT_BATCH(1);
 667       ADVANCE_BATCH();
 668
 669       if (intel->gen < 7) {
 670          for (i = 0; i < 4; i++) {
 671             BEGIN_BATCH(4);
 672             OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
 673             OUT_BATCH(i << SVB_INDEX_SHIFT);
 674             OUT_BATCH(0);
 675             OUT_BATCH(0xffffffff);
 676             ADVANCE_BATCH();
 677          }
 678       }
 679    }
 680
 681    BEGIN_BATCH(2);
 682    OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2));
 683    OUT_BATCH(0);
 684    ADVANCE_BATCH();
 685
 686    BEGIN_BATCH(1);
 687    OUT_BATCH(brw->CMD_VF_STATISTICS << 16 |
 688              (unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0));
 689    ADVANCE_BATCH();
 690 }
 691
 692 const struct brw_tracked_state brw_invarient_state = {
 693    .dirty = {
 694       .mesa = 0,
 695       .brw = BRW_NEW_CONTEXT,
 696       .cache = 0
 697    },
 698    .emit = upload_invarient_state
 699 };
 700
 701 /**
 702  * Define the base addresses which some state is referenced from.
 703  *
 704  * This allows us to avoid having to emit relocations for the objects,
 705  * and is actually required for binding table pointers on gen6.
 706  *
 707  * Surface state base address covers binding table pointers and
 708  * surface state objects, but not the surfaces that the surface state
 709  * objects point to.
 710  */
 711 static void upload_state_base_address( struct brw_context *brw )
 712 {
 713    struct intel_context *intel = &brw->intel;
 714
 715    /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
 716     * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
 717     * programmed prior to STATE_BASE_ADDRESS.
 718     *
 719     * However, given that the instruction SBA (general state base
 720     * address) on this chipset is always set to 0 across X and GL,
 721     * maybe this isn't required for us in particular.
 722     */
 723
 724    if (intel->gen >= 6) {
 725       if (intel->gen == 6)
 726          intel_emit_post_sync_nonzero_flush(intel);
 727
 728        BEGIN_BATCH(10);
 729        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
 730        /* General state base address: stateless DP read/write requests */
 731        OUT_BATCH(1);
 732        /* Surface state base address:
 733         * BINDING_TABLE_STATE
 734         * SURFACE_STATE
 735         */
 736        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
 737         /* Dynamic state base address:
 738          * SAMPLER_STATE
 739          * SAMPLER_BORDER_COLOR_STATE
 740          * CLIP, SF, WM/CC viewport state
 741          * COLOR_CALC_STATE
 742          * DEPTH_STENCIL_STATE
 743          * BLEND_STATE
 744          * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
 745          * Disable is clear, which we rely on)
 746          */
 747        OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
 748                                    I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
 749
 750        OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
 751        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 752                  1); /* Instruction base address: shader kernels (incl. SIP) */
 753
 754        OUT_BATCH(1); /* General state upper bound */
 755        OUT_BATCH(1); /* Dynamic state upper bound */
 756        OUT_BATCH(1); /* Indirect object upper bound */
 757        OUT_BATCH(1); /* Instruction access upper bound */
 758        ADVANCE_BATCH();
 759    } else if (intel->gen == 5) {
 760        BEGIN_BATCH(8);
 761        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 762        OUT_BATCH(1); /* General state base address */
 763        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 764                  1); /* Surface state base address */
 765        OUT_BATCH(1); /* Indirect object base address */
 766        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 767                  1); /* Instruction base address */
 768        OUT_BATCH(1); /* General state upper bound */
 769        OUT_BATCH(1); /* Indirect object upper bound */
 770        OUT_BATCH(1); /* Instruction access upper bound */
 771        ADVANCE_BATCH();
 772    } else {
 773        BEGIN_BATCH(6);
 774        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 775        OUT_BATCH(1); /* General state base address */
 776        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 777                  1); /* Surface state base address */
 778        OUT_BATCH(1); /* Indirect object base address */
 779        OUT_BATCH(1); /* General state upper bound */
 780        OUT_BATCH(1); /* Indirect object upper bound */
 781        ADVANCE_BATCH();
 782    }
 783
 784    /* According to section 3.6.1 of VOL1 of the 965 PRM,
 785     * STATE_BASE_ADDRESS updates require a reissue of:
 786     *
 787     * 3DSTATE_PIPELINE_POINTERS
 788     * 3DSTATE_BINDING_TABLE_POINTERS
 789     * MEDIA_STATE_POINTERS
 790     *
 791     * and this continues through Ironlake.  The Sandy Bridge PRM, vol
 792     * 1 part 1 says that the folowing packets must be reissued:
 793     *
 794     * 3DSTATE_CC_POINTERS
 795     * 3DSTATE_BINDING_TABLE_POINTERS
 796     * 3DSTATE_SAMPLER_STATE_POINTERS
 797     * 3DSTATE_VIEWPORT_STATE_POINTERS
 798     * MEDIA_STATE_POINTERS
 799     *
 800     * Those are always reissued following SBA updates anyway (new
 801     * batch time), except in the case of the program cache BO
 802     * changing.  Having a separate state flag makes the sequence more
 803     * obvious.
 804     */
 805
 806    brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
 807 }
 808
 809 const struct brw_tracked_state brw_state_base_address = {
 810    .dirty = {
 811       .mesa = 0,
 812       .brw = (BRW_NEW_BATCH |
 813               BRW_NEW_PROGRAM_CACHE),
 814       .cache = 0,
 815    },
 816    .emit = upload_state_base_address
 817 };