src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_regions.h"
  36
  37 #include "brw_context.h"
  38 #include "brw_state.h"
  39 #include "brw_defines.h"
  40
  41 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  42 static void upload_drawing_rect(struct brw_context *brw)
  43 {
  44    struct intel_context *intel = &brw->intel;
  45    struct gl_context *ctx = &intel->ctx;
  46
  47    BEGIN_BATCH(4);
  48    OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
  49    OUT_BATCH(0); /* xmin, ymin */
  50    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  51             ((ctx->DrawBuffer->Height - 1) << 16));
  52    OUT_BATCH(0);
  53    ADVANCE_BATCH();
  54 }
  55
  56 const struct brw_tracked_state brw_drawing_rect = {
  57    .dirty = {
  58       .mesa = _NEW_BUFFERS,
  59       .brw = BRW_NEW_CONTEXT,
  60       .cache = 0
  61    },
  62    .emit = upload_drawing_rect
  63 };
  64
  65 /**
  66  * Upload the binding table pointers, which point each stage's array of surface
  67  * state pointers.
  68  *
  69  * The binding table pointers are relative to the surface state base address,
  70  * which points at the batchbuffer containing the streamed batch state.
  71  */
  72 static void upload_binding_table_pointers(struct brw_context *brw)
  73 {
  74    struct intel_context *intel = &brw->intel;
  75
  76    BEGIN_BATCH(6);
  77    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
  78    OUT_BATCH(brw->vs.bind_bo_offset);
  79    OUT_BATCH(0); /* gs */
  80    OUT_BATCH(0); /* clip */
  81    OUT_BATCH(0); /* sf */
  82    OUT_BATCH(brw->wm.bind_bo_offset);
  83    ADVANCE_BATCH();
  84 }
  85
  86 const struct brw_tracked_state brw_binding_table_pointers = {
  87    .dirty = {
  88       .mesa = 0,
  89       .brw = BRW_NEW_BATCH | BRW_NEW_BINDING_TABLE,
  90       .cache = 0,
  91    },
  92    .emit = upload_binding_table_pointers,
  93 };
  94
  95 /**
  96  * Upload the binding table pointers, which point each stage's array of surface
  97  * state pointers.
  98  *
  99  * The binding table pointers are relative to the surface state base address,
 100  * which points at the batchbuffer containing the streamed batch state.
 101  */
 102 static void upload_gen6_binding_table_pointers(struct brw_context *brw)
 103 {
 104    struct intel_context *intel = &brw->intel;
 105
 106    BEGIN_BATCH(4);
 107    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 108              GEN6_BINDING_TABLE_MODIFY_VS |
 109              GEN6_BINDING_TABLE_MODIFY_GS |
 110              GEN6_BINDING_TABLE_MODIFY_PS |
 111              (4 - 2));
 112    OUT_BATCH(brw->vs.bind_bo_offset); /* vs */
 113    OUT_BATCH(0); /* gs */
 114    OUT_BATCH(brw->wm.bind_bo_offset); /* wm/ps */
 115    ADVANCE_BATCH();
 116 }
 117
 118 const struct brw_tracked_state gen6_binding_table_pointers = {
 119    .dirty = {
 120       .mesa = 0,
 121       .brw = BRW_NEW_BATCH | BRW_NEW_BINDING_TABLE,
 122       .cache = 0,
 123    },
 124    .emit = upload_gen6_binding_table_pointers,
 125 };
 126
 127 /**
 128  * Upload pointers to the per-stage state.
 129  *
 130  * The state pointers in this packet are all relative to the general state
 131  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 132  */
 133 static void upload_pipelined_state_pointers(struct brw_context *brw )
 134 {
 135    struct intel_context *intel = &brw->intel;
 136
 137    if (intel->gen == 5) {
 138       /* Need to flush before changing clip max threads for errata. */
 139       BEGIN_BATCH(1);
 140       OUT_BATCH(MI_FLUSH);
 141       ADVANCE_BATCH();
 142    }
 143
 144    BEGIN_BATCH(7);
 145    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
 146    OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 147    if (brw->gs.prog_active)
 148       OUT_RELOC(brw->gs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
 149    else
 150       OUT_BATCH(0);
 151    OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
 152    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 153              brw->sf.state_offset);
 154    OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 155    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 156              brw->cc.state_offset);
 157    ADVANCE_BATCH();
 158
 159    brw->state.dirty.brw |= BRW_NEW_PSP;
 160 }
 161
 162
 163 static void prepare_psp_urb_cbs(struct brw_context *brw)
 164 {
 165    brw_add_validated_bo(brw, brw->vs.state_bo);
 166    brw_add_validated_bo(brw, brw->gs.state_bo);
 167    brw_add_validated_bo(brw, brw->clip.state_bo);
 168    brw_add_validated_bo(brw, brw->sf.state_bo);
 169    brw_add_validated_bo(brw, brw->wm.state_bo);
 170 }
 171
 172 static void upload_psp_urb_cbs(struct brw_context *brw )
 173 {
 174    upload_pipelined_state_pointers(brw);
 175    brw_upload_urb_fence(brw);
 176    brw_upload_cs_urb_state(brw);
 177 }
 178
 179 const struct brw_tracked_state brw_psp_urb_cbs = {
 180    .dirty = {
 181       .mesa = 0,
 182       .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH,
 183       .cache = (CACHE_NEW_VS_UNIT |
 184                 CACHE_NEW_GS_UNIT |
 185                 CACHE_NEW_GS_PROG |
 186                 CACHE_NEW_CLIP_UNIT |
 187                 CACHE_NEW_SF_UNIT |
 188                 CACHE_NEW_WM_UNIT |
 189                 CACHE_NEW_CC_UNIT)
 190    },
 191    .prepare = prepare_psp_urb_cbs,
 192    .emit = upload_psp_urb_cbs,
 193 };
 194
 195 static void prepare_depthbuffer(struct brw_context *brw)
 196 {
 197    struct intel_region *region = brw->state.depth_region;
 198
 199    if (region != NULL)
 200       brw_add_validated_bo(brw, region->buffer);
 201 }
 202
 203 static void emit_depthbuffer(struct brw_context *brw)
 204 {
 205    struct intel_context *intel = &brw->intel;
 206    struct intel_region *region = brw->state.depth_region;
 207    unsigned int len;
 208
 209    if (intel->gen >= 6)
 210       len = 7;
 211    else if (intel->is_g4x || intel->gen == 5)
 212       len = 6;
 213    else
 214       len = 5;
 215
 216    if (region == NULL) {
 217       BEGIN_BATCH(len);
 218       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 219       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 220                 (BRW_SURFACE_NULL << 29));
 221       OUT_BATCH(0);
 222       OUT_BATCH(0);
 223       OUT_BATCH(0);
 224
 225       if (intel->is_g4x || intel->gen >= 5)
 226          OUT_BATCH(0);
 227
 228       if (intel->gen >= 6)
 229          OUT_BATCH(0);
 230
 231       ADVANCE_BATCH();
 232    } else {
 233       unsigned int format;
 234
 235       switch (region->cpp) {
 236       case 2:
 237          format = BRW_DEPTHFORMAT_D16_UNORM;
 238          break;
 239       case 4:
 240          if (intel->depth_buffer_is_float)
 241             format = BRW_DEPTHFORMAT_D32_FLOAT;
 242          else
 243             format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 244          break;
 245       default:
 246          assert(0);
 247          return;
 248       }
 249
 250       assert(region->tiling != I915_TILING_X);
 251       if (intel->gen >= 6)
 252          assert(region->tiling != I915_TILING_NONE);
 253
 254       BEGIN_BATCH(len);
 255       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 256       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 257                 (format << 18) |
 258                 (BRW_TILEWALK_YMAJOR << 26) |
 259                 ((region->tiling != I915_TILING_NONE) << 27) |
 260                 (BRW_SURFACE_2D << 29));
 261       OUT_RELOC(region->buffer,
 262                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 263                 0);
 264       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 265                 ((region->width - 1) << 6) |
 266                 ((region->height - 1) << 19));
 267       OUT_BATCH(0);
 268
 269       if (intel->is_g4x || intel->gen >= 5)
 270          OUT_BATCH(0);
 271
 272       if (intel->gen >= 6)
 273          OUT_BATCH(0);
 274
 275       ADVANCE_BATCH();
 276    }
 277
 278    /* Initialize it for safety. */
 279    if (intel->gen >= 6) {
 280       BEGIN_BATCH(2);
 281       OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
 282       OUT_BATCH(0);
 283       ADVANCE_BATCH();
 284    }
 285 }
 286
 287 const struct brw_tracked_state brw_depthbuffer = {
 288    .dirty = {
 289       .mesa = 0,
 290       .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH,
 291       .cache = 0,
 292    },
 293    .prepare = prepare_depthbuffer,
 294    .emit = emit_depthbuffer,
 295 };
 296
 297
 298
 299 /***********************************************************************
 300  * Polygon stipple packet
 301  */
 302
 303 static void upload_polygon_stipple(struct brw_context *brw)
 304 {
 305    struct intel_context *intel = &brw->intel;
 306    struct gl_context *ctx = &brw->intel.ctx;
 307    GLuint i;
 308
 309    if (!ctx->Polygon.StippleFlag)
 310       return;
 311
 312    BEGIN_BATCH(33);
 313    OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
 314
 315    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 316     * row first.  If we're rendering to a window (i.e. the
 317     * default frame buffer object, 0), then we need to invert
 318     * it to match our pixel layout.  But if we're rendering
 319     * to a FBO (i.e. any named frame buffer object), we *don't*
 320     * need to invert - we already match the layout.
 321     */
 322    if (ctx->DrawBuffer->Name == 0) {
 323       for (i = 0; i < 32; i++)
 324           OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
 325    }
 326    else {
 327       for (i = 0; i < 32; i++)
 328          OUT_BATCH(ctx->PolygonStipple[i]);
 329    }
 330    CACHED_BATCH();
 331 }
 332
 333 const struct brw_tracked_state brw_polygon_stipple = {
 334    .dirty = {
 335       .mesa = _NEW_POLYGONSTIPPLE,
 336       .brw = BRW_NEW_CONTEXT,
 337       .cache = 0
 338    },
 339    .emit = upload_polygon_stipple
 340 };
 341
 342
 343 /***********************************************************************
 344  * Polygon stipple offset packet
 345  */
 346
 347 static void upload_polygon_stipple_offset(struct brw_context *brw)
 348 {
 349    struct intel_context *intel = &brw->intel;
 350    struct gl_context *ctx = &brw->intel.ctx;
 351
 352    if (!ctx->Polygon.StippleFlag)
 353       return;
 354
 355    BEGIN_BATCH(2);
 356    OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
 357
 358    /* If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 359     * we have to invert the Y axis in order to match the OpenGL
 360     * pixel coordinate system, and our offset must be matched
 361     * to the window position.  If we're drawing to a FBO
 362     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 363     * system works just fine, and there's no window system to
 364     * worry about.
 365     */
 366    if (brw->intel.ctx.DrawBuffer->Name == 0)
 367       OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
 368    else
 369       OUT_BATCH(0);
 370    CACHED_BATCH();
 371 }
 372
 373 #define _NEW_WINDOW_POS 0x40000000
 374
 375 const struct brw_tracked_state brw_polygon_stipple_offset = {
 376    .dirty = {
 377       .mesa = _NEW_WINDOW_POS | _NEW_POLYGONSTIPPLE,
 378       .brw = BRW_NEW_CONTEXT,
 379       .cache = 0
 380    },
 381    .emit = upload_polygon_stipple_offset
 382 };
 383
 384 /**********************************************************************
 385  * AA Line parameters
 386  */
 387 static void upload_aa_line_parameters(struct brw_context *brw)
 388 {
 389    struct intel_context *intel = &brw->intel;
 390    struct gl_context *ctx = &brw->intel.ctx;
 391
 392    if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
 393       return;
 394
 395    OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
 396    /* use legacy aa line coverage computation */
 397    OUT_BATCH(0);
 398    OUT_BATCH(0);
 399    CACHED_BATCH();
 400 }
 401
 402 const struct brw_tracked_state brw_aa_line_parameters = {
 403    .dirty = {
 404       .mesa = _NEW_LINE,
 405       .brw = BRW_NEW_CONTEXT,
 406       .cache = 0
 407    },
 408    .emit = upload_aa_line_parameters
 409 };
 410
 411 /***********************************************************************
 412  * Line stipple packet
 413  */
 414
 415 static void upload_line_stipple(struct brw_context *brw)
 416 {
 417    struct intel_context *intel = &brw->intel;
 418    struct gl_context *ctx = &brw->intel.ctx;
 419    GLfloat tmp;
 420    GLint tmpi;
 421
 422    if (!ctx->Line.StippleFlag)
 423       return;
 424
 425    BEGIN_BATCH(3);
 426    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
 427    OUT_BATCH(ctx->Line.StipplePattern);
 428    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 429    tmpi = tmp * (1<<13);
 430    OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
 431    CACHED_BATCH();
 432 }
 433
 434 const struct brw_tracked_state brw_line_stipple = {
 435    .dirty = {
 436       .mesa = _NEW_LINE,
 437       .brw = BRW_NEW_CONTEXT,
 438       .cache = 0
 439    },
 440    .emit = upload_line_stipple
 441 };
 442
 443
 444 /***********************************************************************
 445  * Misc invarient state packets
 446  */
 447
 448 static void upload_invarient_state( struct brw_context *brw )
 449 {
 450    struct intel_context *intel = &brw->intel;
 451
 452    {
 453       /* 0x61040000  Pipeline Select */
 454       /*     PipelineSelect            : 0 */
 455       struct brw_pipeline_select ps;
 456
 457       memset(&ps, 0, sizeof(ps));
 458       ps.header.opcode = brw->CMD_PIPELINE_SELECT;
 459       ps.header.pipeline_select = 0;
 460       BRW_BATCH_STRUCT(brw, &ps);
 461    }
 462
 463    if (intel->gen < 6) {
 464       struct brw_global_depth_offset_clamp gdo;
 465       memset(&gdo, 0, sizeof(gdo));
 466
 467       /* Disable depth offset clamping.
 468        */
 469       gdo.header.opcode = _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP;
 470       gdo.header.length = sizeof(gdo)/4 - 2;
 471       gdo.depth_offset_clamp = 0.0;
 472
 473       BRW_BATCH_STRUCT(brw, &gdo);
 474    }
 475
 476    if (intel->gen >= 6) {
 477       int i;
 478
 479       BEGIN_BATCH(3);
 480       OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (3 - 2));
 481       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
 482                 MS_NUMSAMPLES_1);
 483       OUT_BATCH(0); /* positions for 4/8-sample */
 484       ADVANCE_BATCH();
 485
 486       BEGIN_BATCH(2);
 487       OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
 488       OUT_BATCH(1);
 489       ADVANCE_BATCH();
 490
 491       for (i = 0; i < 4; i++) {
 492          BEGIN_BATCH(4);
 493          OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
 494          OUT_BATCH(i << SVB_INDEX_SHIFT);
 495          OUT_BATCH(0);
 496          OUT_BATCH(0xffffffff);
 497          ADVANCE_BATCH();
 498       }
 499    }
 500
 501    /* 0x61020000  State Instruction Pointer */
 502    {
 503       struct brw_system_instruction_pointer sip;
 504       memset(&sip, 0, sizeof(sip));
 505
 506       sip.header.opcode = CMD_STATE_INSN_POINTER;
 507       sip.header.length = 0;
 508       sip.bits0.pad = 0;
 509       sip.bits0.system_instruction_pointer = 0;
 510       BRW_BATCH_STRUCT(brw, &sip);
 511    }
 512
 513
 514    {
 515       struct brw_vf_statistics vfs;
 516       memset(&vfs, 0, sizeof(vfs));
 517
 518       vfs.opcode = brw->CMD_VF_STATISTICS;
 519       if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 520          vfs.statistics_enable = 1;
 521
 522       BRW_BATCH_STRUCT(brw, &vfs);
 523    }
 524 }
 525
 526 const struct brw_tracked_state brw_invarient_state = {
 527    .dirty = {
 528       .mesa = 0,
 529       .brw = BRW_NEW_CONTEXT,
 530       .cache = 0
 531    },
 532    .emit = upload_invarient_state
 533 };
 534
 535 /**
 536  * Define the base addresses which some state is referenced from.
 537  *
 538  * This allows us to avoid having to emit relocations for the objects,
 539  * and is actually required for binding table pointers on gen6.
 540  *
 541  * Surface state base address covers binding table pointers and
 542  * surface state objects, but not the surfaces that the surface state
 543  * objects point to.
 544  */
 545 static void upload_state_base_address( struct brw_context *brw )
 546 {
 547    struct intel_context *intel = &brw->intel;
 548
 549    if (intel->gen >= 6) {
 550        BEGIN_BATCH(10);
 551        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
 552        OUT_BATCH(1); /* General state base address */
 553        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 554                  1); /* Surface state base address */
 555        OUT_BATCH(1); /* Dynamic state base address */
 556        OUT_BATCH(1); /* Indirect object base address */
 557        OUT_BATCH(1); /* Instruction base address */
 558        OUT_BATCH(1); /* General state upper bound */
 559        OUT_BATCH(1); /* Dynamic state upper bound */
 560        OUT_BATCH(1); /* Indirect object upper bound */
 561        OUT_BATCH(1); /* Instruction access upper bound */
 562        ADVANCE_BATCH();
 563    } else if (intel->gen == 5) {
 564        BEGIN_BATCH(8);
 565        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 566        OUT_BATCH(1); /* General state base address */
 567        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 568                  1); /* Surface state base address */
 569        OUT_BATCH(1); /* Indirect object base address */
 570        OUT_BATCH(1); /* Instruction base address */
 571        OUT_BATCH(1); /* General state upper bound */
 572        OUT_BATCH(1); /* Indirect object upper bound */
 573        OUT_BATCH(1); /* Instruction access upper bound */
 574        ADVANCE_BATCH();
 575    } else {
 576        BEGIN_BATCH(6);
 577        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 578        OUT_BATCH(1); /* General state base address */
 579        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 580                  1); /* Surface state base address */
 581        OUT_BATCH(1); /* Indirect object base address */
 582        OUT_BATCH(1); /* General state upper bound */
 583        OUT_BATCH(1); /* Indirect object upper bound */
 584        ADVANCE_BATCH();
 585    }
 586 }
 587
 588 const struct brw_tracked_state brw_state_base_address = {
 589    .dirty = {
 590       .mesa = 0,
 591       .brw = BRW_NEW_BATCH,
 592       .cache = 0,
 593    },
 594    .emit = upload_state_base_address
 595 };