2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_regions.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
42 /* Constant single cliprect for framebuffer object or DRI2 drawing */
43 static void upload_drawing_rect(struct brw_context
*brw
)
45 struct intel_context
*intel
= &brw
->intel
;
46 struct gl_context
*ctx
= &intel
->ctx
;
49 OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965
);
50 OUT_BATCH(0); /* xmin, ymin */
51 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
52 ((ctx
->DrawBuffer
->Height
- 1) << 16));
57 const struct brw_tracked_state brw_drawing_rect
= {
60 .brw
= BRW_NEW_CONTEXT
,
63 .emit
= upload_drawing_rect
67 * Upload the binding table pointers, which point each stage's array of surface
70 * The binding table pointers are relative to the surface state base address,
71 * which points at the batchbuffer containing the streamed batch state.
73 static void upload_binding_table_pointers(struct brw_context
*brw
)
75 struct intel_context
*intel
= &brw
->intel
;
78 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 | (6 - 2));
79 OUT_BATCH(brw
->vs
.bind_bo_offset
);
80 OUT_BATCH(0); /* gs */
81 OUT_BATCH(0); /* clip */
82 OUT_BATCH(0); /* sf */
83 OUT_BATCH(brw
->wm
.bind_bo_offset
);
87 const struct brw_tracked_state brw_binding_table_pointers
= {
91 | BRW_NEW_VS_BINDING_TABLE
92 | BRW_NEW_GS_BINDING_TABLE
93 | BRW_NEW_PS_BINDING_TABLE
,
96 .emit
= upload_binding_table_pointers
,
100 * Upload the binding table pointers, which point each stage's array of surface
103 * The binding table pointers are relative to the surface state base address,
104 * which points at the batchbuffer containing the streamed batch state.
106 static void upload_gen6_binding_table_pointers(struct brw_context
*brw
)
108 struct intel_context
*intel
= &brw
->intel
;
111 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
112 GEN6_BINDING_TABLE_MODIFY_VS
|
113 GEN6_BINDING_TABLE_MODIFY_GS
|
114 GEN6_BINDING_TABLE_MODIFY_PS
|
116 OUT_BATCH(brw
->vs
.bind_bo_offset
); /* vs */
117 OUT_BATCH(0); /* gs */
118 OUT_BATCH(brw
->wm
.bind_bo_offset
); /* wm/ps */
122 const struct brw_tracked_state gen6_binding_table_pointers
= {
126 | BRW_NEW_VS_BINDING_TABLE
127 | BRW_NEW_GS_BINDING_TABLE
128 | BRW_NEW_PS_BINDING_TABLE
,
131 .emit
= upload_gen6_binding_table_pointers
,
135 * Upload pointers to the per-stage state.
137 * The state pointers in this packet are all relative to the general state
138 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
140 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
142 struct intel_context
*intel
= &brw
->intel
;
144 if (intel
->gen
== 5) {
145 /* Need to flush before changing clip max threads for errata. */
152 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
153 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
154 brw
->vs
.state_offset
);
155 if (brw
->gs
.prog_active
)
156 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
157 brw
->gs
.state_offset
| 1);
160 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
161 brw
->clip
.state_offset
| 1);
162 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
163 brw
->sf
.state_offset
);
164 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
165 brw
->wm
.state_offset
);
166 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
167 brw
->cc
.state_offset
);
170 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
173 static void upload_psp_urb_cbs(struct brw_context
*brw
)
175 upload_pipelined_state_pointers(brw
);
176 brw_upload_urb_fence(brw
);
177 brw_upload_cs_urb_state(brw
);
180 const struct brw_tracked_state brw_psp_urb_cbs
= {
183 .brw
= BRW_NEW_URB_FENCE
| BRW_NEW_BATCH
,
184 .cache
= (CACHE_NEW_VS_UNIT
|
187 CACHE_NEW_CLIP_UNIT
|
192 .emit
= upload_psp_urb_cbs
,
195 static void prepare_depthbuffer(struct brw_context
*brw
)
197 struct intel_context
*intel
= &brw
->intel
;
198 struct gl_context
*ctx
= &intel
->ctx
;
199 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
200 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
201 struct intel_renderbuffer
*srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
204 brw_add_validated_bo(brw
, drb
->region
->buffer
);
205 if (drb
&& drb
->hiz_region
)
206 brw_add_validated_bo(brw
, drb
->hiz_region
->buffer
);
208 brw_add_validated_bo(brw
, srb
->region
->buffer
);
211 static void emit_depthbuffer(struct brw_context
*brw
)
213 struct intel_context
*intel
= &brw
->intel
;
214 struct gl_context
*ctx
= &intel
->ctx
;
215 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
217 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
218 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
219 struct intel_region
*hiz_region
= depth_irb
? depth_irb
->hiz_region
: NULL
;
223 * If either depth or stencil buffer has packed depth/stencil format,
224 * then don't use separate stencil. Emit only a depth buffer.
226 if (depth_irb
&& depth_irb
->Base
.Format
== MESA_FORMAT_S8_Z24
) {
228 } else if (!depth_irb
&& stencil_irb
229 && stencil_irb
->Base
.Format
== MESA_FORMAT_S8_Z24
) {
230 depth_irb
= stencil_irb
;
236 else if (intel
->is_g4x
|| intel
->gen
== 5)
241 if (!depth_irb
&& !stencil_irb
) {
243 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
244 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
245 (BRW_SURFACE_NULL
<< 29));
250 if (intel
->is_g4x
|| intel
->gen
>= 5)
258 } else if (!depth_irb
&& stencil_irb
) {
260 * There exists a separate stencil buffer but no depth buffer.
262 * The stencil buffer inherits most of its fields from
263 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
266 * Since the stencil buffer has quirky pitch requirements, its region
267 * was allocated with half height and double cpp. So we need
268 * a multiplier of 2 to obtain the surface's real height.
270 * Enable the hiz bit because it and the separate stencil bit must have
271 * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
272 * 1.21 "Separate Stencil Enable":
273 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
274 * Enable must also be enabled.
276 * [DevGT]: This field must be set to the same value (enabled or
277 * disabled) as Hierarchical Depth Buffer Enable
279 assert(intel
->has_separate_stencil
);
280 assert(stencil_irb
->Base
.Format
== MESA_FORMAT_S8
);
283 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
284 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
285 (1 << 21) | /* separate stencil enable */
286 (1 << 22) | /* hiz enable */
287 (BRW_TILEWALK_YMAJOR
<< 26) |
288 (BRW_SURFACE_2D
<< 29));
290 OUT_BATCH(((stencil_irb
->region
->width
- 1) << 6) |
291 (2 * stencil_irb
->region
->height
- 1) << 19);
301 struct intel_region
*region
= depth_irb
->region
;
303 uint32_t tile_x
, tile_y
, offset
;
305 /* If using separate stencil, hiz must be enabled. */
306 assert(!stencil_irb
|| hiz_region
);
308 switch (region
->cpp
) {
310 format
= BRW_DEPTHFORMAT_D16_UNORM
;
313 if (intel
->depth_buffer_is_float
)
314 format
= BRW_DEPTHFORMAT_D32_FLOAT
;
316 format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
318 format
= BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
325 offset
= intel_renderbuffer_tile_offsets(depth_irb
, &tile_x
, &tile_y
);
327 assert(intel
->gen
< 6 || region
->tiling
== I915_TILING_Y
);
328 assert(!hiz_region
|| region
->tiling
== I915_TILING_Y
);
331 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
332 OUT_BATCH(((region
->pitch
* region
->cpp
) - 1) |
334 ((hiz_region
? 1 : 0) << 21) | /* separate stencil enable */
335 ((hiz_region
? 1 : 0) << 22) | /* hiz enable */
336 (BRW_TILEWALK_YMAJOR
<< 26) |
337 ((region
->tiling
!= I915_TILING_NONE
) << 27) |
338 (BRW_SURFACE_2D
<< 29));
339 OUT_RELOC(region
->buffer
,
340 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
342 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1) |
343 ((region
->width
- 1) << 6) |
344 ((region
->height
- 1) << 19));
347 if (intel
->is_g4x
|| intel
->gen
>= 5)
348 OUT_BATCH(tile_x
| (tile_y
<< 16));
350 assert(tile_x
== 0 && tile_y
== 0);
358 if (hiz_region
|| stencil_irb
) {
360 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
361 * stencil enable' and 'hiz enable' bits were set. Therefore we must
362 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
363 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
364 * failure to do so causes hangs on gen5 and a stall on gen6.
367 /* Emit hiz buffer. */
370 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
371 OUT_BATCH(hiz_region
->pitch
* hiz_region
->cpp
- 1);
372 OUT_RELOC(hiz_region
->buffer
,
373 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
378 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
384 /* Emit stencil buffer. */
387 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
388 OUT_BATCH(stencil_irb
->region
->pitch
* stencil_irb
->region
->cpp
- 1);
389 OUT_RELOC(stencil_irb
->region
->buffer
,
390 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
395 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
403 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
404 * params must be emitted.
406 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
407 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
408 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
410 if (intel
->gen
>= 6 || hiz_region
) {
412 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 | (2 - 2));
418 const struct brw_tracked_state brw_depthbuffer
= {
420 .mesa
= _NEW_BUFFERS
,
421 .brw
= BRW_NEW_BATCH
,
424 .prepare
= prepare_depthbuffer
,
425 .emit
= emit_depthbuffer
,
430 /***********************************************************************
431 * Polygon stipple packet
434 static void upload_polygon_stipple(struct brw_context
*brw
)
436 struct intel_context
*intel
= &brw
->intel
;
437 struct gl_context
*ctx
= &brw
->intel
.ctx
;
440 if (!ctx
->Polygon
.StippleFlag
)
444 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
446 /* Polygon stipple is provided in OpenGL order, i.e. bottom
447 * row first. If we're rendering to a window (i.e. the
448 * default frame buffer object, 0), then we need to invert
449 * it to match our pixel layout. But if we're rendering
450 * to a FBO (i.e. any named frame buffer object), we *don't*
451 * need to invert - we already match the layout.
453 if (ctx
->DrawBuffer
->Name
== 0) {
454 for (i
= 0; i
< 32; i
++)
455 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
458 for (i
= 0; i
< 32; i
++)
459 OUT_BATCH(ctx
->PolygonStipple
[i
]);
464 const struct brw_tracked_state brw_polygon_stipple
= {
466 .mesa
= _NEW_POLYGONSTIPPLE
,
467 .brw
= BRW_NEW_CONTEXT
,
470 .emit
= upload_polygon_stipple
474 /***********************************************************************
475 * Polygon stipple offset packet
478 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
480 struct intel_context
*intel
= &brw
->intel
;
481 struct gl_context
*ctx
= &brw
->intel
.ctx
;
483 if (!ctx
->Polygon
.StippleFlag
)
487 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
489 /* If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
490 * we have to invert the Y axis in order to match the OpenGL
491 * pixel coordinate system, and our offset must be matched
492 * to the window position. If we're drawing to a FBO
493 * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
494 * system works just fine, and there's no window system to
497 if (brw
->intel
.ctx
.DrawBuffer
->Name
== 0)
498 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
504 #define _NEW_WINDOW_POS 0x40000000
506 const struct brw_tracked_state brw_polygon_stipple_offset
= {
508 .mesa
= _NEW_WINDOW_POS
| _NEW_POLYGONSTIPPLE
,
509 .brw
= BRW_NEW_CONTEXT
,
512 .emit
= upload_polygon_stipple_offset
515 /**********************************************************************
518 static void upload_aa_line_parameters(struct brw_context
*brw
)
520 struct intel_context
*intel
= &brw
->intel
;
521 struct gl_context
*ctx
= &brw
->intel
.ctx
;
523 if (!ctx
->Line
.SmoothFlag
|| !brw
->has_aa_line_parameters
)
526 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
527 /* use legacy aa line coverage computation */
533 const struct brw_tracked_state brw_aa_line_parameters
= {
536 .brw
= BRW_NEW_CONTEXT
,
539 .emit
= upload_aa_line_parameters
542 /***********************************************************************
543 * Line stipple packet
546 static void upload_line_stipple(struct brw_context
*brw
)
548 struct intel_context
*intel
= &brw
->intel
;
549 struct gl_context
*ctx
= &brw
->intel
.ctx
;
553 if (!ctx
->Line
.StippleFlag
)
557 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
558 OUT_BATCH(ctx
->Line
.StipplePattern
);
559 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
560 tmpi
= tmp
* (1<<13);
561 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
565 const struct brw_tracked_state brw_line_stipple
= {
568 .brw
= BRW_NEW_CONTEXT
,
571 .emit
= upload_line_stipple
575 /***********************************************************************
576 * Misc invarient state packets
579 static void upload_invarient_state( struct brw_context
*brw
)
581 struct intel_context
*intel
= &brw
->intel
;
584 /* 0x61040000 Pipeline Select */
585 /* PipelineSelect : 0 */
586 struct brw_pipeline_select ps
;
588 memset(&ps
, 0, sizeof(ps
));
589 ps
.header
.opcode
= brw
->CMD_PIPELINE_SELECT
;
590 ps
.header
.pipeline_select
= 0;
591 BRW_BATCH_STRUCT(brw
, &ps
);
594 if (intel
->gen
< 6) {
595 struct brw_global_depth_offset_clamp gdo
;
596 memset(&gdo
, 0, sizeof(gdo
));
598 /* Disable depth offset clamping.
600 gdo
.header
.opcode
= _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
;
601 gdo
.header
.length
= sizeof(gdo
)/4 - 2;
602 gdo
.depth_offset_clamp
= 0.0;
604 BRW_BATCH_STRUCT(brw
, &gdo
);
607 if (intel
->gen
>= 6) {
609 int len
= intel
->gen
>= 7 ? 4 : 3;
612 OUT_BATCH(_3DSTATE_MULTISAMPLE
<< 16 | (len
- 2));
613 OUT_BATCH(MS_PIXEL_LOCATION_CENTER
|
615 OUT_BATCH(0); /* positions for 4/8-sample */
621 OUT_BATCH(_3DSTATE_SAMPLE_MASK
<< 16 | (2 - 2));
625 if (intel
->gen
< 7) {
626 for (i
= 0; i
< 4; i
++) {
628 OUT_BATCH(_3DSTATE_GS_SVB_INDEX
<< 16 | (4 - 2));
629 OUT_BATCH(i
<< SVB_INDEX_SHIFT
);
631 OUT_BATCH(0xffffffff);
637 /* 0x61020000 State Instruction Pointer */
639 struct brw_system_instruction_pointer sip
;
640 memset(&sip
, 0, sizeof(sip
));
642 sip
.header
.opcode
= CMD_STATE_INSN_POINTER
;
643 sip
.header
.length
= 0;
645 sip
.bits0
.system_instruction_pointer
= 0;
646 BRW_BATCH_STRUCT(brw
, &sip
);
651 struct brw_vf_statistics vfs
;
652 memset(&vfs
, 0, sizeof(vfs
));
654 vfs
.opcode
= brw
->CMD_VF_STATISTICS
;
655 if (unlikely(INTEL_DEBUG
& DEBUG_STATS
))
656 vfs
.statistics_enable
= 1;
658 BRW_BATCH_STRUCT(brw
, &vfs
);
662 const struct brw_tracked_state brw_invarient_state
= {
665 .brw
= BRW_NEW_CONTEXT
,
668 .emit
= upload_invarient_state
672 * Define the base addresses which some state is referenced from.
674 * This allows us to avoid having to emit relocations for the objects,
675 * and is actually required for binding table pointers on gen6.
677 * Surface state base address covers binding table pointers and
678 * surface state objects, but not the surfaces that the surface state
681 static void upload_state_base_address( struct brw_context
*brw
)
683 struct intel_context
*intel
= &brw
->intel
;
685 if (intel
->gen
>= 6) {
687 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
688 /* General state base address: stateless DP read/write requests */
690 /* Surface state base address:
691 * BINDING_TABLE_STATE
694 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
695 /* Dynamic state base address:
697 * SAMPLER_BORDER_COLOR_STATE
698 * CLIP, SF, WM/CC viewport state
700 * DEPTH_STENCIL_STATE
702 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
703 * Disable is clear, which we rely on)
705 OUT_RELOC(intel
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
706 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
708 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
709 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
710 1); /* Instruction base address: shader kernels (incl. SIP) */
712 OUT_BATCH(1); /* General state upper bound */
713 OUT_BATCH(1); /* Dynamic state upper bound */
714 OUT_BATCH(1); /* Indirect object upper bound */
715 OUT_BATCH(1); /* Instruction access upper bound */
717 } else if (intel
->gen
== 5) {
719 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
720 OUT_BATCH(1); /* General state base address */
721 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
722 1); /* Surface state base address */
723 OUT_BATCH(1); /* Indirect object base address */
724 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
725 1); /* Instruction base address */
726 OUT_BATCH(1); /* General state upper bound */
727 OUT_BATCH(1); /* Indirect object upper bound */
728 OUT_BATCH(1); /* Instruction access upper bound */
732 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
733 OUT_BATCH(1); /* General state base address */
734 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
735 1); /* Surface state base address */
736 OUT_BATCH(1); /* Indirect object base address */
737 OUT_BATCH(1); /* General state upper bound */
738 OUT_BATCH(1); /* Indirect object upper bound */
743 const struct brw_tracked_state brw_state_base_address
= {
746 .brw
= (BRW_NEW_BATCH
|
747 BRW_NEW_PROGRAM_CACHE
),
750 .emit
= upload_state_base_address