2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
42 #include "main/fbobject.h"
43 #include "main/glformats.h"
45 /* Constant single cliprect for framebuffer object or DRI2 drawing */
46 static void upload_drawing_rect(struct brw_context
*brw
)
48 struct gl_context
*ctx
= &brw
->ctx
;
51 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
52 OUT_BATCH(0); /* xmin, ymin */
53 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
54 ((ctx
->DrawBuffer
->Height
- 1) << 16));
59 const struct brw_tracked_state brw_drawing_rect
= {
62 .brw
= BRW_NEW_CONTEXT
,
64 .emit
= upload_drawing_rect
68 * Upload pointers to the per-stage state.
70 * The state pointers in this packet are all relative to the general state
71 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
73 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
76 /* Need to flush before changing clip max threads for errata. */
83 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
84 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
85 brw
->vs
.base
.state_offset
);
86 if (brw
->ff_gs
.prog_active
)
87 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
88 brw
->ff_gs
.state_offset
| 1);
91 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
92 brw
->clip
.state_offset
| 1);
93 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
94 brw
->sf
.state_offset
);
95 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
96 brw
->wm
.base
.state_offset
);
97 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
98 brw
->cc
.state_offset
);
101 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
104 static void upload_psp_urb_cbs(struct brw_context
*brw
)
106 upload_pipelined_state_pointers(brw
);
107 brw_upload_urb_fence(brw
);
108 brw_upload_cs_urb_state(brw
);
111 const struct brw_tracked_state brw_psp_urb_cbs
= {
114 .brw
= BRW_NEW_BATCH
|
115 BRW_NEW_FF_GS_PROG_DATA
|
116 BRW_NEW_GEN4_UNIT_STATE
|
117 BRW_NEW_STATE_BASE_ADDRESS
|
120 .emit
= upload_psp_urb_cbs
,
124 brw_depthbuffer_format(struct brw_context
*brw
)
126 struct gl_context
*ctx
= &brw
->ctx
;
127 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
128 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
129 struct intel_renderbuffer
*srb
;
132 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
133 !srb
->mt
->stencil_mt
&&
134 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
135 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
140 return BRW_DEPTHFORMAT_D32_FLOAT
;
142 return brw_depth_format(brw
, drb
->mt
->format
);
146 * Returns the mask of how many bits of x and y must be handled through the
147 * depthbuffer's draw offset x and y fields.
149 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
150 * between the depth, hiz, and stencil buffers. Because it can be hard to get
151 * all 3 to agree on this value, we want to do as much drawing offset
152 * adjustment as possible by moving the base offset of the 3 buffers, which is
153 * restricted to tile boundaries.
155 * For each buffer, the remainder must be applied through the x/y draw offset.
156 * This returns the worst-case mask of the low bits that have to go into the
157 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
158 * mask, then we're in trouble.
161 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
162 uint32_t depth_level
,
163 uint32_t depth_layer
,
164 struct intel_mipmap_tree
*stencil_mt
,
165 uint32_t *out_tile_mask_x
,
166 uint32_t *out_tile_mask_y
)
168 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
171 intel_miptree_get_tile_masks(depth_mt
, &tile_mask_x
, &tile_mask_y
, false);
173 if (intel_miptree_level_has_hiz(depth_mt
, depth_level
)) {
174 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
175 intel_miptree_get_tile_masks(depth_mt
->hiz_buf
->mt
,
176 &hiz_tile_mask_x
, &hiz_tile_mask_y
,
179 /* Each HiZ row represents 2 rows of pixels */
180 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
182 tile_mask_x
|= hiz_tile_mask_x
;
183 tile_mask_y
|= hiz_tile_mask_y
;
188 if (stencil_mt
->stencil_mt
)
189 stencil_mt
= stencil_mt
->stencil_mt
;
191 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
192 /* Separate stencil buffer uses 64x64 tiles. */
196 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
197 intel_miptree_get_tile_masks(stencil_mt
,
198 &stencil_tile_mask_x
,
199 &stencil_tile_mask_y
, false);
201 tile_mask_x
|= stencil_tile_mask_x
;
202 tile_mask_y
|= stencil_tile_mask_y
;
206 *out_tile_mask_x
= tile_mask_x
;
207 *out_tile_mask_y
= tile_mask_y
;
210 static struct intel_mipmap_tree
*
211 get_stencil_miptree(struct intel_renderbuffer
*irb
)
215 if (irb
->mt
->stencil_mt
)
216 return irb
->mt
->stencil_mt
;
221 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
222 GLbitfield clear_mask
)
224 struct gl_context
*ctx
= &brw
->ctx
;
225 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
226 bool rebase_depth
= false;
227 bool rebase_stencil
= false;
228 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
229 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
230 struct intel_mipmap_tree
*depth_mt
= NULL
;
231 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
232 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
233 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
234 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
235 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
238 depth_mt
= depth_irb
->mt
;
240 /* Initialize brw->depthstencil to 'nop' workaround state.
242 brw
->depthstencil
.tile_x
= 0;
243 brw
->depthstencil
.tile_y
= 0;
244 brw
->depthstencil
.depth_offset
= 0;
245 brw
->depthstencil
.stencil_offset
= 0;
246 brw
->depthstencil
.hiz_offset
= 0;
247 brw
->depthstencil
.depth_mt
= NULL
;
248 brw
->depthstencil
.stencil_mt
= NULL
;
250 brw
->depthstencil
.depth_mt
= depth_mt
;
252 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
254 /* Gen6+ doesn't require the workarounds, since we always program the
255 * surface state at the start of the whole surface.
260 /* Check if depth buffer is in depth/stencil format. If so, then it's only
261 * safe to invalidate it if we're also clearing stencil, and both depth_irb
262 * and stencil_irb point to the same miptree.
264 * Note: it's not sufficient to check for the case where
265 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
266 * because this fails to catch depth/stencil buffers on hardware that uses
267 * separate stencil. To catch that case, we check whether
268 * depth_mt->stencil_mt is non-NULL.
270 if (depth_irb
&& invalidate_depth
&&
271 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
272 depth_mt
->stencil_mt
)) {
273 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
274 && depth_irb
->mt
== stencil_irb
->mt
;
277 uint32_t tile_mask_x
, tile_mask_y
;
278 brw_get_depthstencil_tile_masks(depth_mt
,
279 depth_mt
? depth_irb
->mt_level
: 0,
280 depth_mt
? depth_irb
->mt_layer
: 0,
282 &tile_mask_x
, &tile_mask_y
);
285 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
286 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
288 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
289 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
290 * Coordinate Offset X/Y":
292 * "The 3 LSBs of both offsets must be zero to ensure correct
295 if (tile_x
& 7 || tile_y
& 7)
298 /* We didn't even have intra-tile offsets before g45. */
299 if (!brw
->has_surface_tile_offset
) {
300 if (tile_x
|| tile_y
)
305 perf_debug("HW workaround: blitting depth level %d to a temporary "
306 "to fix alignment (depth tile offset %d,%d)\n",
307 depth_irb
->mt_level
, tile_x
, tile_y
);
308 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
309 /* In the case of stencil_irb being the same packed depth/stencil
310 * texture but not the same rb, make it point at our rebased mt, too.
313 stencil_irb
!= depth_irb
&&
314 stencil_irb
->mt
== depth_mt
) {
315 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
316 intel_renderbuffer_set_draw_offset(stencil_irb
);
319 stencil_mt
= get_stencil_miptree(stencil_irb
);
321 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
322 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
326 stencil_mt
= get_stencil_miptree(stencil_irb
);
327 intel_miptree_get_image_offset(stencil_mt
,
328 stencil_irb
->mt_level
,
329 stencil_irb
->mt_layer
,
330 &stencil_draw_x
, &stencil_draw_y
);
331 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
332 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
334 /* If stencil doesn't match depth, then we'll need to rebase stencil
335 * as well. (if we hadn't decided to rebase stencil before, the
336 * post-stencil depth test will also rebase depth to try to match it
339 if (tile_x
!= stencil_tile_x
||
340 tile_y
!= stencil_tile_y
) {
341 rebase_stencil
= true;
346 /* If we have (just) stencil, check it for ignored low bits as well */
348 intel_miptree_get_image_offset(stencil_mt
,
349 stencil_irb
->mt_level
,
350 stencil_irb
->mt_layer
,
351 &stencil_draw_x
, &stencil_draw_y
);
352 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
353 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
355 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
356 rebase_stencil
= true;
358 if (!brw
->has_surface_tile_offset
) {
359 if (stencil_tile_x
|| stencil_tile_y
)
360 rebase_stencil
= true;
364 if (rebase_stencil
) {
365 perf_debug("HW workaround: blitting stencil level %d to a temporary "
366 "to fix alignment (stencil tile offset %d,%d)\n",
367 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
369 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
370 stencil_mt
= get_stencil_miptree(stencil_irb
);
372 intel_miptree_get_image_offset(stencil_mt
,
373 stencil_irb
->mt_level
,
374 stencil_irb
->mt_layer
,
375 &stencil_draw_x
, &stencil_draw_y
);
376 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
377 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
379 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
380 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
381 intel_renderbuffer_set_draw_offset(depth_irb
);
382 } else if (depth_irb
&& !rebase_depth
) {
383 if (tile_x
!= stencil_tile_x
||
384 tile_y
!= stencil_tile_y
) {
385 perf_debug("HW workaround: blitting depth level %d to a temporary "
386 "to match stencil level %d alignment (depth tile offset "
387 "%d,%d, stencil offset %d,%d)\n",
389 stencil_irb
->mt_level
,
391 stencil_tile_x
, stencil_tile_y
);
393 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
395 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
396 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
398 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
399 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
400 intel_renderbuffer_set_draw_offset(stencil_irb
);
403 WARN_ONCE(stencil_tile_x
!= tile_x
||
404 stencil_tile_y
!= tile_y
,
405 "Rebased stencil tile offset (%d,%d) doesn't match depth "
406 "tile offset (%d,%d).\n",
407 stencil_tile_x
, stencil_tile_y
,
414 tile_x
= stencil_tile_x
;
415 tile_y
= stencil_tile_y
;
418 /* While we just tried to get everything aligned, we may have failed to do
419 * so in the case of rendering to array or 3D textures, where nonzero faces
420 * will still have an offset post-rebase. At least give an informative
423 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
424 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
425 "Truncating offset, bad rendering may occur.\n");
429 /* Now, after rebasing, save off the new dephtstencil state so the hardware
430 * packets can just dereference that without re-calculating tile offsets.
432 brw
->depthstencil
.tile_x
= tile_x
;
433 brw
->depthstencil
.tile_y
= tile_y
;
435 depth_mt
= depth_irb
->mt
;
436 brw
->depthstencil
.depth_mt
= depth_mt
;
437 brw
->depthstencil
.depth_offset
=
438 intel_miptree_get_aligned_offset(depth_mt
,
439 depth_irb
->draw_x
& ~tile_mask_x
,
440 depth_irb
->draw_y
& ~tile_mask_y
,
442 if (intel_renderbuffer_has_hiz(depth_irb
)) {
443 brw
->depthstencil
.hiz_offset
=
444 intel_miptree_get_aligned_offset(depth_mt
,
445 depth_irb
->draw_x
& ~tile_mask_x
,
446 (depth_irb
->draw_y
& ~tile_mask_y
) / 2,
451 stencil_mt
= get_stencil_miptree(stencil_irb
);
453 brw
->depthstencil
.stencil_mt
= stencil_mt
;
454 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
455 /* Note: we can't compute the stencil offset using
456 * intel_region_get_aligned_offset(), because stencil_region claims
457 * that the region is untiled even though it's W tiled.
459 brw
->depthstencil
.stencil_offset
=
460 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
461 (stencil_draw_x
& ~tile_mask_x
) * 64;
467 brw_emit_depthbuffer(struct brw_context
*brw
)
469 struct gl_context
*ctx
= &brw
->ctx
;
470 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
472 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
473 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
474 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
475 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
476 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
477 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
478 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
479 bool separate_stencil
= false;
480 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
481 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
482 uint32_t depth_offset
= 0;
483 uint32_t width
= 1, height
= 1;
486 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
488 /* Gen7 supports only separate stencil */
489 assert(separate_stencil
|| brw
->gen
< 7);
492 /* If there's a packed depth/stencil bound to stencil only, we need to
493 * emit the packed depth/stencil buffer packet.
495 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
496 depth_irb
= stencil_irb
;
497 depth_mt
= stencil_mt
;
500 if (depth_irb
&& depth_mt
) {
501 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
502 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
503 * depthstencil format.
505 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
506 * set to the same value. Gens after 7 implicitly always set
507 * Separate_Stencil_Enable; software cannot disable it.
509 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
510 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
513 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
514 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
516 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
517 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
519 depthbuffer_format
= brw_depthbuffer_format(brw
);
520 depth_surface_type
= BRW_SURFACE_2D
;
521 depth_offset
= brw
->depthstencil
.depth_offset
;
522 width
= depth_irb
->Base
.Base
.Width
;
523 height
= depth_irb
->Base
.Base
.Height
;
524 } else if (separate_stencil
) {
526 * There exists a separate stencil buffer but no depth buffer.
528 * The stencil buffer inherits most of its fields from
529 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
532 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
533 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
534 * [DevGT+]: This field must be set to TRUE.
536 assert(brw
->has_separate_stencil
);
538 depth_surface_type
= BRW_SURFACE_2D
;
539 width
= stencil_irb
->Base
.Base
.Width
;
540 height
= stencil_irb
->Base
.Base
.Height
;
544 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
546 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
548 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
549 depthbuffer_format
, depth_surface_type
,
550 stencil_mt
, hiz
, separate_stencil
,
551 width
, height
, tile_x
, tile_y
);
555 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
556 struct intel_mipmap_tree
*depth_mt
,
557 uint32_t depth_offset
, uint32_t depthbuffer_format
,
558 uint32_t depth_surface_type
,
559 struct intel_mipmap_tree
*stencil_mt
,
560 bool hiz
, bool separate_stencil
,
561 uint32_t width
, uint32_t height
,
562 uint32_t tile_x
, uint32_t tile_y
)
564 /* Enable the hiz bit if we're doing separate stencil, because it and the
565 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
566 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
567 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
568 * Enable must also be enabled.
570 * [DevGT]: This field must be set to the same value (enabled or
571 * disabled) as Hierarchical Depth Buffer Enable
573 bool enable_hiz_ss
= hiz
|| separate_stencil
;
576 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
577 * non-pipelined state that will need the PIPE_CONTROL workaround.
580 intel_emit_depth_stall_flushes(brw
);
586 else if (brw
->is_g4x
|| brw
->gen
== 5)
592 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
593 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
594 (depthbuffer_format
<< 18) |
595 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
596 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
597 (BRW_TILEWALK_YMAJOR
<< 26) |
598 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
600 (depth_surface_type
<< 29));
603 OUT_RELOC(depth_mt
->bo
,
604 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
610 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
611 ((height
+ tile_y
- 1) << 19));
614 if (brw
->is_g4x
|| brw
->gen
>= 5)
615 OUT_BATCH(tile_x
| (tile_y
<< 16));
617 assert(tile_x
== 0 && tile_y
== 0);
624 if (hiz
|| separate_stencil
) {
626 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
627 * stencil enable' and 'hiz enable' bits were set. Therefore we must
628 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
629 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
630 * failure to do so causes hangs on gen5 and a stall on gen6.
633 /* Emit hiz buffer. */
635 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_buf
->mt
;
637 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
638 OUT_BATCH(hiz_mt
->pitch
- 1);
639 OUT_RELOC(hiz_mt
->bo
,
640 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
641 brw
->depthstencil
.hiz_offset
);
645 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
651 /* Emit stencil buffer. */
652 if (separate_stencil
) {
654 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
655 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
656 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
657 * The pitch must be set to 2x the value computed based on width, as
658 * the stencil buffer is stored with two rows interleaved.
660 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
661 OUT_RELOC(stencil_mt
->bo
,
662 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
663 brw
->depthstencil
.stencil_offset
);
667 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
675 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
676 * params must be emitted.
678 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
679 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
680 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
682 if (brw
->gen
>= 6 || hiz
) {
684 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
685 GEN5_DEPTH_CLEAR_VALID
|
687 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
692 const struct brw_tracked_state brw_depthbuffer
= {
694 .mesa
= _NEW_BUFFERS
,
695 .brw
= BRW_NEW_BATCH
,
697 .emit
= brw_emit_depthbuffer
,
702 /***********************************************************************
703 * Polygon stipple packet
706 static void upload_polygon_stipple(struct brw_context
*brw
)
708 struct gl_context
*ctx
= &brw
->ctx
;
712 if (!ctx
->Polygon
.StippleFlag
)
716 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
718 /* Polygon stipple is provided in OpenGL order, i.e. bottom
719 * row first. If we're rendering to a window (i.e. the
720 * default frame buffer object, 0), then we need to invert
721 * it to match our pixel layout. But if we're rendering
722 * to a FBO (i.e. any named frame buffer object), we *don't*
723 * need to invert - we already match the layout.
725 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
726 for (i
= 0; i
< 32; i
++)
727 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
730 for (i
= 0; i
< 32; i
++)
731 OUT_BATCH(ctx
->PolygonStipple
[i
]);
736 const struct brw_tracked_state brw_polygon_stipple
= {
738 .mesa
= _NEW_POLYGON
|
740 .brw
= BRW_NEW_CONTEXT
,
742 .emit
= upload_polygon_stipple
746 /***********************************************************************
747 * Polygon stipple offset packet
750 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
752 struct gl_context
*ctx
= &brw
->ctx
;
755 if (!ctx
->Polygon
.StippleFlag
)
759 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
763 * If we're drawing to a system window we have to invert the Y axis
764 * in order to match the OpenGL pixel coordinate system, and our
765 * offset must be matched to the window position. If we're drawing
766 * to a user-created FBO then our native pixel coordinate system
767 * works just fine, and there's no window system to worry about.
769 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
770 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
776 const struct brw_tracked_state brw_polygon_stipple_offset
= {
778 .mesa
= _NEW_BUFFERS
|
780 .brw
= BRW_NEW_CONTEXT
,
782 .emit
= upload_polygon_stipple_offset
785 /**********************************************************************
788 static void upload_aa_line_parameters(struct brw_context
*brw
)
790 struct gl_context
*ctx
= &brw
->ctx
;
792 if (!ctx
->Line
.SmoothFlag
)
795 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
796 if (brw
->gen
== 4 && !brw
->is_g4x
)
800 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
801 /* use legacy aa line coverage computation */
807 const struct brw_tracked_state brw_aa_line_parameters
= {
810 .brw
= BRW_NEW_CONTEXT
,
812 .emit
= upload_aa_line_parameters
815 /***********************************************************************
816 * Line stipple packet
819 static void upload_line_stipple(struct brw_context
*brw
)
821 struct gl_context
*ctx
= &brw
->ctx
;
825 if (!ctx
->Line
.StippleFlag
)
829 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
830 OUT_BATCH(ctx
->Line
.StipplePattern
);
834 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
835 tmpi
= tmp
* (1<<16);
836 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
840 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
841 tmpi
= tmp
* (1<<13);
842 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
848 const struct brw_tracked_state brw_line_stipple
= {
851 .brw
= BRW_NEW_CONTEXT
,
853 .emit
= upload_line_stipple
857 /***********************************************************************
858 * Misc invariant state packets
862 brw_upload_invariant_state(struct brw_context
*brw
)
864 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
866 /* Select the 3D pipeline (as opposed to media) */
867 const uint32_t _3DSTATE_PIPELINE_SELECT
=
868 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
870 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 | (brw
->gen
>= 9 ? (3 << 8) : 0));
874 /* Disable depth offset clamping. */
876 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
883 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
889 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
894 const uint32_t _3DSTATE_VF_STATISTICS
=
895 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
897 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 | 1);
901 const struct brw_tracked_state brw_invariant_state
= {
904 .brw
= BRW_NEW_CONTEXT
,
906 .emit
= brw_upload_invariant_state
910 * Define the base addresses which some state is referenced from.
912 * This allows us to avoid having to emit relocations for the objects,
913 * and is actually required for binding table pointers on gen6.
915 * Surface state base address covers binding table pointers and
916 * surface state objects, but not the surfaces that the surface state
919 static void upload_state_base_address( struct brw_context
*brw
)
921 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
922 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
923 * programmed prior to STATE_BASE_ADDRESS.
925 * However, given that the instruction SBA (general state base
926 * address) on this chipset is always set to 0 across X and GL,
927 * maybe this isn't required for us in particular.
931 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
934 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
935 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
936 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
937 1); /* General State Base Address Modify Enable */
938 /* Surface state base address:
939 * BINDING_TABLE_STATE
942 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
943 /* Dynamic state base address:
945 * SAMPLER_BORDER_COLOR_STATE
946 * CLIP, SF, WM/CC viewport state
948 * DEPTH_STENCIL_STATE
950 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
951 * Disable is clear, which we rely on)
953 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
954 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
956 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
957 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
958 1); /* Instruction base address: shader kernels (incl. SIP) */
960 OUT_BATCH(1); /* General state upper bound */
961 /* Dynamic state upper bound. Although the documentation says that
962 * programming it to zero will cause it to be ignored, that is a lie.
963 * If this isn't programmed to a real bound, the sampler border color
964 * pointer is rejected, causing border color to mysteriously fail.
966 OUT_BATCH(0xfffff001);
967 OUT_BATCH(1); /* Indirect object upper bound */
968 OUT_BATCH(1); /* Instruction access upper bound */
970 } else if (brw
->gen
== 5) {
972 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
973 OUT_BATCH(1); /* General state base address */
974 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
975 1); /* Surface state base address */
976 OUT_BATCH(1); /* Indirect object base address */
977 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
978 1); /* Instruction base address */
979 OUT_BATCH(0xfffff001); /* General state upper bound */
980 OUT_BATCH(1); /* Indirect object upper bound */
981 OUT_BATCH(1); /* Instruction access upper bound */
985 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
986 OUT_BATCH(1); /* General state base address */
987 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
988 1); /* Surface state base address */
989 OUT_BATCH(1); /* Indirect object base address */
990 OUT_BATCH(1); /* General state upper bound */
991 OUT_BATCH(1); /* Indirect object upper bound */
995 /* According to section 3.6.1 of VOL1 of the 965 PRM,
996 * STATE_BASE_ADDRESS updates require a reissue of:
998 * 3DSTATE_PIPELINE_POINTERS
999 * 3DSTATE_BINDING_TABLE_POINTERS
1000 * MEDIA_STATE_POINTERS
1002 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1003 * 1 part 1 says that the folowing packets must be reissued:
1005 * 3DSTATE_CC_POINTERS
1006 * 3DSTATE_BINDING_TABLE_POINTERS
1007 * 3DSTATE_SAMPLER_STATE_POINTERS
1008 * 3DSTATE_VIEWPORT_STATE_POINTERS
1009 * MEDIA_STATE_POINTERS
1011 * Those are always reissued following SBA updates anyway (new
1012 * batch time), except in the case of the program cache BO
1013 * changing. Having a separate state flag makes the sequence more
1017 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
1020 const struct brw_tracked_state brw_state_base_address
= {
1023 .brw
= BRW_NEW_BATCH
|
1024 BRW_NEW_PROGRAM_CACHE
,
1026 .emit
= upload_state_base_address