src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "intel_mipmap_tree.h"
  37
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40 #include "brw_defines.h"
  41 #include "compiler/brw_eu_defines.h"
  42
  43 #include "main/framebuffer.h"
  44 #include "main/fbobject.h"
  45 #include "main/format_utils.h"
  46 #include "main/glformats.h"
  47
  48 /**
  49  * Upload pointers to the per-stage state.
  50  *
  51  * The state pointers in this packet are all relative to the general state
  52  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
  53  */
  54 static void
  55 upload_pipelined_state_pointers(struct brw_context *brw)
  56 {
  57    if (brw->gen == 5) {
  58       /* Need to flush before changing clip max threads for errata. */
  59       BEGIN_BATCH(1);
  60       OUT_BATCH(MI_FLUSH);
  61       ADVANCE_BATCH();
  62    }
  63
  64    BEGIN_BATCH(7);
  65    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
  66    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  67              brw->vs.base.state_offset);
  68    if (brw->ff_gs.prog_active)
  69       OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  70                 brw->ff_gs.state_offset | 1);
  71    else
  72       OUT_BATCH(0);
  73    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  74              brw->clip.state_offset | 1);
  75    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  76              brw->sf.state_offset);
  77    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  78              brw->wm.base.state_offset);
  79    OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
  80              brw->cc.state_offset);
  81    ADVANCE_BATCH();
  82
  83    brw->ctx.NewDriverState |= BRW_NEW_PSP;
  84 }
  85
  86 static void
  87 upload_psp_urb_cbs(struct brw_context *brw)
  88 {
  89    upload_pipelined_state_pointers(brw);
  90    brw_upload_urb_fence(brw);
  91    brw_upload_cs_urb_state(brw);
  92 }
  93
  94 const struct brw_tracked_state brw_psp_urb_cbs = {
  95    .dirty = {
  96       .mesa = 0,
  97       .brw = BRW_NEW_BATCH |
  98              BRW_NEW_BLORP |
  99              BRW_NEW_FF_GS_PROG_DATA |
 100              BRW_NEW_GEN4_UNIT_STATE |
 101              BRW_NEW_STATE_BASE_ADDRESS |
 102              BRW_NEW_URB_FENCE,
 103    },
 104    .emit = upload_psp_urb_cbs,
 105 };
 106
 107 uint32_t
 108 brw_depthbuffer_format(struct brw_context *brw)
 109 {
 110    struct gl_context *ctx = &brw->ctx;
 111    struct gl_framebuffer *fb = ctx->DrawBuffer;
 112    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 113    struct intel_renderbuffer *srb;
 114
 115    if (!drb &&
 116        (srb = intel_get_renderbuffer(fb, BUFFER_STENCIL)) &&
 117        !srb->mt->stencil_mt &&
 118        (intel_rb_format(srb) == MESA_FORMAT_Z24_UNORM_S8_UINT ||
 119         intel_rb_format(srb) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT)) {
 120       drb = srb;
 121    }
 122
 123    if (!drb)
 124       return BRW_DEPTHFORMAT_D32_FLOAT;
 125
 126    return brw_depth_format(brw, drb->mt->format);
 127 }
 128
 129 static struct intel_mipmap_tree *
 130 get_stencil_miptree(struct intel_renderbuffer *irb)
 131 {
 132    if (!irb)
 133       return NULL;
 134    if (irb->mt->stencil_mt)
 135       return irb->mt->stencil_mt;
 136    return intel_renderbuffer_get_mt(irb);
 137 }
 138
 139 static bool
 140 rebase_depth_stencil(struct brw_context *brw, struct intel_renderbuffer *irb,
 141                      bool invalidate)
 142 {
 143    struct gl_context *ctx = &brw->ctx;
 144    uint32_t tile_mask_x = 0, tile_mask_y = 0;
 145
 146    intel_get_tile_masks(irb->mt->tiling, irb->mt->cpp,
 147                         &tile_mask_x, &tile_mask_y);
 148    assert(!intel_miptree_level_has_hiz(irb->mt, irb->mt_level));
 149
 150    uint32_t tile_x = irb->draw_x & tile_mask_x;
 151    uint32_t tile_y = irb->draw_y & tile_mask_y;
 152
 153    /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 154     * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 155     * Coordinate Offset X/Y":
 156     *
 157     *   "The 3 LSBs of both offsets must be zero to ensure correct
 158     *   alignment"
 159     */
 160    bool rebase = tile_x & 7 || tile_y & 7;
 161
 162    /* We didn't even have intra-tile offsets before g45. */
 163    rebase |= (!brw->has_surface_tile_offset && (tile_x || tile_y));
 164
 165    if (rebase) {
 166       perf_debug("HW workaround: blitting depth level %d to a temporary "
 167                  "to fix alignment (depth tile offset %d,%d)\n",
 168                  irb->mt_level, tile_x, tile_y);
 169       intel_renderbuffer_move_to_temp(brw, irb, invalidate);
 170
 171       /* Get the new offset. */
 172       tile_x = irb->draw_x & tile_mask_x;
 173       tile_y = irb->draw_y & tile_mask_y;
 174    }
 175
 176    /* While we just tried to get everything aligned, we may have failed to do
 177     * so in the case of rendering to array or 3D textures, where nonzero faces
 178     * will still have an offset post-rebase.  At least give an informative
 179     * warning.
 180     */
 181    WARN_ONCE((tile_x & 7) || (tile_y & 7),
 182              "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
 183              "Truncating offset (%u:%u), bad rendering may occur.\n",
 184              tile_x, tile_y);
 185    tile_x &= ~7;
 186    tile_y &= ~7;
 187
 188    brw->depthstencil.tile_x = tile_x;
 189    brw->depthstencil.tile_y = tile_y;
 190    brw->depthstencil.depth_offset = intel_miptree_get_aligned_offset(
 191                                        irb->mt,
 192                                        irb->draw_x & ~tile_mask_x,
 193                                        irb->draw_y & ~tile_mask_y);
 194
 195    return rebase;
 196 }
 197
 198 void
 199 brw_workaround_depthstencil_alignment(struct brw_context *brw,
 200                                       GLbitfield clear_mask)
 201 {
 202    struct gl_context *ctx = &brw->ctx;
 203    struct gl_framebuffer *fb = ctx->DrawBuffer;
 204    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 205    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 206    struct intel_mipmap_tree *depth_mt = NULL;
 207    bool invalidate_depth = clear_mask & BUFFER_BIT_DEPTH;
 208    bool invalidate_stencil = clear_mask & BUFFER_BIT_STENCIL;
 209
 210    if (depth_irb)
 211       depth_mt = depth_irb->mt;
 212
 213    /* Initialize brw->depthstencil to 'nop' workaround state.
 214     */
 215    brw->depthstencil.tile_x = 0;
 216    brw->depthstencil.tile_y = 0;
 217    brw->depthstencil.depth_offset = 0;
 218
 219    /* Gen6+ doesn't require the workarounds, since we always program the
 220     * surface state at the start of the whole surface.
 221     */
 222    if (brw->gen >= 6)
 223       return;
 224
 225    /* Check if depth buffer is in depth/stencil format.  If so, then it's only
 226     * safe to invalidate it if we're also clearing stencil.
 227     */
 228    if (depth_irb && invalidate_depth &&
 229       _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL)
 230       invalidate_depth = invalidate_stencil && stencil_irb;
 231
 232    if (depth_irb) {
 233       if (rebase_depth_stencil(brw, depth_irb, invalidate_depth)) {
 234          /* In the case of stencil_irb being the same packed depth/stencil
 235           * texture but not the same rb, make it point at our rebased mt, too.
 236           */
 237          if (stencil_irb &&
 238              stencil_irb != depth_irb &&
 239              stencil_irb->mt == depth_mt) {
 240             intel_miptree_reference(&stencil_irb->mt, depth_irb->mt);
 241             intel_renderbuffer_set_draw_offset(stencil_irb);
 242          }
 243       }
 244
 245       if (stencil_irb) {
 246          assert(stencil_irb->mt == depth_irb->mt);
 247          assert(stencil_irb->mt_level == depth_irb->mt_level);
 248          assert(stencil_irb->mt_layer == depth_irb->mt_layer);
 249       }
 250    }
 251
 252    /* If there is no depth attachment, consider if stencil needs rebase. */
 253    if (!depth_irb && stencil_irb)
 254        rebase_depth_stencil(brw, stencil_irb, invalidate_stencil);
 255 }
 256
 257 void
 258 brw_emit_depthbuffer(struct brw_context *brw)
 259 {
 260    struct gl_context *ctx = &brw->ctx;
 261    struct gl_framebuffer *fb = ctx->DrawBuffer;
 262    /* _NEW_BUFFERS */
 263    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 264    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 265    struct intel_mipmap_tree *depth_mt = intel_renderbuffer_get_mt(depth_irb);
 266    struct intel_mipmap_tree *stencil_mt = get_stencil_miptree(stencil_irb);
 267    uint32_t tile_x = brw->depthstencil.tile_x;
 268    uint32_t tile_y = brw->depthstencil.tile_y;
 269    bool hiz = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
 270    bool separate_stencil = false;
 271    uint32_t depth_surface_type = BRW_SURFACE_NULL;
 272    uint32_t depthbuffer_format = BRW_DEPTHFORMAT_D32_FLOAT;
 273    uint32_t depth_offset = 0;
 274    uint32_t width = 1, height = 1;
 275
 276    if (stencil_mt) {
 277       separate_stencil = stencil_mt->format == MESA_FORMAT_S_UINT8;
 278
 279       /* Gen7 supports only separate stencil */
 280       assert(separate_stencil || brw->gen < 7);
 281    }
 282
 283    /* If there's a packed depth/stencil bound to stencil only, we need to
 284     * emit the packed depth/stencil buffer packet.
 285     */
 286    if (!depth_irb && stencil_irb && !separate_stencil) {
 287       depth_irb = stencil_irb;
 288       depth_mt = stencil_mt;
 289    }
 290
 291    if (depth_irb && depth_mt) {
 292       /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
 293        * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
 294        * depthstencil format.
 295        *
 296        * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
 297        * set to the same value. Gens after 7 implicitly always set
 298        * Separate_Stencil_Enable; software cannot disable it.
 299        */
 300       if ((brw->gen < 7 && hiz) || brw->gen >= 7) {
 301          assert(!_mesa_is_format_packed_depth_stencil(depth_mt->format));
 302       }
 303
 304       /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
 305       assert(brw->gen >= 7 || !separate_stencil || hiz);
 306
 307       assert(brw->gen < 6 || depth_mt->tiling == I915_TILING_Y);
 308       assert(!hiz || depth_mt->tiling == I915_TILING_Y);
 309
 310       depthbuffer_format = brw_depthbuffer_format(brw);
 311       depth_surface_type = BRW_SURFACE_2D;
 312       depth_offset = brw->depthstencil.depth_offset;
 313       width = depth_irb->Base.Base.Width;
 314       height = depth_irb->Base.Base.Height;
 315    } else if (separate_stencil) {
 316       /*
 317        * There exists a separate stencil buffer but no depth buffer.
 318        *
 319        * The stencil buffer inherits most of its fields from
 320        * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
 321        * height.
 322        *
 323        * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
 324        * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
 325        *     [DevGT+]: This field must be set to TRUE.
 326        */
 327       assert(brw->has_separate_stencil);
 328
 329       depth_surface_type = BRW_SURFACE_2D;
 330       width = stencil_irb->Base.Base.Width;
 331       height = stencil_irb->Base.Base.Height;
 332    }
 333
 334    if (depth_mt)
 335       brw_render_cache_set_check_flush(brw, depth_mt->bo);
 336    if (stencil_mt)
 337       brw_render_cache_set_check_flush(brw, stencil_mt->bo);
 338
 339    brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
 340                                     depthbuffer_format, depth_surface_type,
 341                                     stencil_mt, hiz, separate_stencil,
 342                                     width, height, tile_x, tile_y);
 343 }
 344
 345 uint32_t
 346 brw_convert_depth_value(mesa_format format, float value)
 347 {
 348    switch (format) {
 349    case MESA_FORMAT_Z_FLOAT32:
 350       return float_as_int(value);
 351    case MESA_FORMAT_Z_UNORM16:
 352       return value * ((1u << 16) - 1);
 353    case MESA_FORMAT_Z24_UNORM_X8_UINT:
 354       return value * ((1u << 24) - 1);
 355    default:
 356       unreachable("Invalid depth format");
 357    }
 358 }
 359
 360 void
 361 brw_emit_depth_stencil_hiz(struct brw_context *brw,
 362                            struct intel_mipmap_tree *depth_mt,
 363                            uint32_t depth_offset, uint32_t depthbuffer_format,
 364                            uint32_t depth_surface_type,
 365                            struct intel_mipmap_tree *stencil_mt,
 366                            bool hiz, bool separate_stencil,
 367                            uint32_t width, uint32_t height,
 368                            uint32_t tile_x, uint32_t tile_y)
 369 {
 370    (void)hiz;
 371    (void)separate_stencil;
 372    (void)stencil_mt;
 373
 374    assert(!hiz);
 375    assert(!separate_stencil);
 376
 377    const unsigned len = (brw->is_g4x || brw->gen == 5) ? 6 : 5;
 378
 379    BEGIN_BATCH(len);
 380    OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 381    OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
 382              (depthbuffer_format << 18) |
 383              (BRW_TILEWALK_YMAJOR << 26) |
 384              ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1)
 385               << 27) |
 386              (depth_surface_type << 29));
 387
 388    if (depth_mt) {
 389       OUT_RELOC(depth_mt->bo,
 390                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 391                 depth_offset);
 392    } else {
 393       OUT_BATCH(0);
 394    }
 395
 396    OUT_BATCH(((width + tile_x - 1) << 6) |
 397              ((height + tile_y - 1) << 19));
 398    OUT_BATCH(0);
 399
 400    if (brw->is_g4x || brw->gen >= 5)
 401       OUT_BATCH(tile_x | (tile_y << 16));
 402    else
 403       assert(tile_x == 0 && tile_y == 0);
 404
 405    if (brw->gen >= 6)
 406       OUT_BATCH(0);
 407
 408    ADVANCE_BATCH();
 409 }
 410
 411 const struct brw_tracked_state brw_depthbuffer = {
 412    .dirty = {
 413       .mesa = _NEW_BUFFERS,
 414       .brw = BRW_NEW_BATCH |
 415              BRW_NEW_BLORP,
 416    },
 417    .emit = brw_emit_depthbuffer,
 418 };
 419
 420 void
 421 brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
 422 {
 423    const bool is_965 = brw->gen == 4 && !brw->is_g4x;
 424    const uint32_t _3DSTATE_PIPELINE_SELECT =
 425       is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
 426
 427    if (brw->gen >= 8 && brw->gen < 10) {
 428       /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
 429        *
 430        *   Software must clear the COLOR_CALC_STATE Valid field in
 431        *   3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
 432        *   with Pipeline Select set to GPGPU.
 433        *
 434        * The internal hardware docs recommend the same workaround for Gen9
 435        * hardware too.
 436        */
 437       if (pipeline == BRW_COMPUTE_PIPELINE) {
 438          BEGIN_BATCH(2);
 439          OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
 440          OUT_BATCH(0);
 441          ADVANCE_BATCH();
 442
 443          brw->ctx.NewDriverState |= BRW_NEW_CC_STATE;
 444       }
 445    }
 446
 447    if (brw->gen >= 6) {
 448       /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
 449        * PIPELINE_SELECT [DevBWR+]":
 450        *
 451        *   Project: DEVSNB+
 452        *
 453        *   Software must ensure all the write caches are flushed through a
 454        *   stalling PIPE_CONTROL command followed by another PIPE_CONTROL
 455        *   command to invalidate read only caches prior to programming
 456        *   MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
 457        */
 458       const unsigned dc_flush =
 459          brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
 460
 461       brw_emit_pipe_control_flush(brw,
 462                                   PIPE_CONTROL_RENDER_TARGET_FLUSH |
 463                                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 464                                   dc_flush |
 465                                   PIPE_CONTROL_NO_WRITE |
 466                                   PIPE_CONTROL_CS_STALL);
 467
 468       brw_emit_pipe_control_flush(brw,
 469                                   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 470                                   PIPE_CONTROL_CONST_CACHE_INVALIDATE |
 471                                   PIPE_CONTROL_STATE_CACHE_INVALIDATE |
 472                                   PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 473                                   PIPE_CONTROL_NO_WRITE);
 474
 475    } else {
 476       /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
 477        * PIPELINE_SELECT [DevBWR+]":
 478        *
 479        *   Project: PRE-DEVSNB
 480        *
 481        *   Software must ensure the current pipeline is flushed via an
 482        *   MI_FLUSH or PIPE_CONTROL prior to the execution of PIPELINE_SELECT.
 483        */
 484       BEGIN_BATCH(1);
 485       OUT_BATCH(MI_FLUSH);
 486       ADVANCE_BATCH();
 487    }
 488
 489    /* Select the pipeline */
 490    BEGIN_BATCH(1);
 491    OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 |
 492              (brw->gen >= 9 ? (3 << 8) : 0) |
 493              (pipeline == BRW_COMPUTE_PIPELINE ? 2 : 0));
 494    ADVANCE_BATCH();
 495
 496    if (brw->gen == 7 && !brw->is_haswell &&
 497        pipeline == BRW_RENDER_PIPELINE) {
 498       /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
 499        * PIPELINE_SELECT [DevBWR+]":
 500        *
 501        *   Project: DEVIVB, DEVHSW:GT3:A0
 502        *
 503        *   Software must send a pipe_control with a CS stall and a post sync
 504        *   operation and then a dummy DRAW after every MI_SET_CONTEXT and
 505        *   after any PIPELINE_SELECT that is enabling 3D mode.
 506        */
 507       gen7_emit_cs_stall_flush(brw);
 508
 509       BEGIN_BATCH(7);
 510       OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 511       OUT_BATCH(_3DPRIM_POINTLIST);
 512       OUT_BATCH(0);
 513       OUT_BATCH(0);
 514       OUT_BATCH(0);
 515       OUT_BATCH(0);
 516       OUT_BATCH(0);
 517       ADVANCE_BATCH();
 518    }
 519 }
 520
 521 /**
 522  * Misc invariant state packets
 523  */
 524 void
 525 brw_upload_invariant_state(struct brw_context *brw)
 526 {
 527    const bool is_965 = brw->gen == 4 && !brw->is_g4x;
 528
 529    brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE);
 530    brw->last_pipeline = BRW_RENDER_PIPELINE;
 531
 532    if (brw->gen >= 8) {
 533       BEGIN_BATCH(3);
 534       OUT_BATCH(CMD_STATE_SIP << 16 | (3 - 2));
 535       OUT_BATCH(0);
 536       OUT_BATCH(0);
 537       ADVANCE_BATCH();
 538    } else {
 539       BEGIN_BATCH(2);
 540       OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2));
 541       OUT_BATCH(0);
 542       ADVANCE_BATCH();
 543    }
 544
 545    /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
 546    if (!is_965) {
 547       BEGIN_BATCH(3);
 548       OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
 549       /* use legacy aa line coverage computation */
 550       OUT_BATCH(0);
 551       OUT_BATCH(0);
 552       ADVANCE_BATCH();
 553    }
 554
 555    const uint32_t _3DSTATE_VF_STATISTICS =
 556       is_965 ? GEN4_3DSTATE_VF_STATISTICS : GM45_3DSTATE_VF_STATISTICS;
 557    BEGIN_BATCH(1);
 558    OUT_BATCH(_3DSTATE_VF_STATISTICS << 16 | 1);
 559    ADVANCE_BATCH();
 560 }
 561
 562 const struct brw_tracked_state brw_invariant_state = {
 563    .dirty = {
 564       .mesa = 0,
 565       .brw = BRW_NEW_BLORP |
 566              BRW_NEW_CONTEXT,
 567    },
 568    .emit = brw_upload_invariant_state
 569 };
 570
 571 /**
 572  * Define the base addresses which some state is referenced from.
 573  *
 574  * This allows us to avoid having to emit relocations for the objects,
 575  * and is actually required for binding table pointers on gen6.
 576  *
 577  * Surface state base address covers binding table pointers and
 578  * surface state objects, but not the surfaces that the surface state
 579  * objects point to.
 580  */
 581 void
 582 brw_upload_state_base_address(struct brw_context *brw)
 583 {
 584    if (brw->batch.state_base_address_emitted)
 585       return;
 586
 587    /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
 588     * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
 589     * programmed prior to STATE_BASE_ADDRESS.
 590     *
 591     * However, given that the instruction SBA (general state base
 592     * address) on this chipset is always set to 0 across X and GL,
 593     * maybe this isn't required for us in particular.
 594     */
 595
 596    if (brw->gen >= 6) {
 597       const unsigned dc_flush =
 598          brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0;
 599
 600       /* Emit a render target cache flush.
 601        *
 602        * This isn't documented anywhere in the PRM.  However, it seems to be
 603        * necessary prior to changing the surface state base adress.  We've
 604        * seen issues in Vulkan where we get GPU hangs when using multi-level
 605        * command buffers which clear depth, reset state base address, and then
 606        * go render stuff.
 607        *
 608        * Normally, in GL, we would trust the kernel to do sufficient stalls
 609        * and flushes prior to executing our batch.  However, it doesn't seem
 610        * as if the kernel's flushing is always sufficient and we don't want to
 611        * rely on it.
 612        *
 613        * We make this an end-of-pipe sync instead of a normal flush because we
 614        * do not know the current status of the GPU.  On Haswell at least,
 615        * having a fast-clear operation in flight at the same time as a normal
 616        * rendering operation can cause hangs.  Since the kernel's flushing is
 617        * insufficient, we need to ensure that any rendering operations from
 618        * other processes are definitely complete before we try to do our own
 619        * rendering.  It's a bit of a big hammer but it appears to work.
 620        */
 621       brw_emit_end_of_pipe_sync(brw,
 622                                 PIPE_CONTROL_RENDER_TARGET_FLUSH |
 623                                 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 624                                 dc_flush);
 625    }
 626
 627    if (brw->gen >= 8) {
 628       uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
 629       int pkt_len = brw->gen >= 9 ? 19 : 16;
 630
 631       BEGIN_BATCH(pkt_len);
 632       OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
 633       /* General state base address: stateless DP read/write requests */
 634       OUT_BATCH(mocs_wb << 4 | 1);
 635       OUT_BATCH(0);
 636       OUT_BATCH(mocs_wb << 16);
 637       /* Surface state base address: */
 638       OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 639                   mocs_wb << 4 | 1);
 640       /* Dynamic state base address: */
 641       OUT_RELOC64(brw->batch.bo,
 642                   I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
 643                   mocs_wb << 4 | 1);
 644       /* Indirect object base address: MEDIA_OBJECT data */
 645       OUT_BATCH(mocs_wb << 4 | 1);
 646       OUT_BATCH(0);
 647       /* Instruction base address: shader kernels (incl. SIP) */
 648       OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 649                   mocs_wb << 4 | 1);
 650
 651       /* General state buffer size */
 652       OUT_BATCH(0xfffff001);
 653       /* Dynamic state buffer size */
 654       OUT_BATCH(ALIGN(brw->batch.bo->size, 4096) | 1);
 655       /* Indirect object upper bound */
 656       OUT_BATCH(0xfffff001);
 657       /* Instruction access upper bound */
 658       OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
 659       if (brw->gen >= 9) {
 660          OUT_BATCH(1);
 661          OUT_BATCH(0);
 662          OUT_BATCH(0);
 663       }
 664       ADVANCE_BATCH();
 665    } else if (brw->gen >= 6) {
 666       uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
 667
 668        BEGIN_BATCH(10);
 669        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
 670        OUT_BATCH(mocs << 8 | /* General State Memory Object Control State */
 671                  mocs << 4 | /* Stateless Data Port Access Memory Object Control State */
 672                  1); /* General State Base Address Modify Enable */
 673        /* Surface state base address:
 674         * BINDING_TABLE_STATE
 675         * SURFACE_STATE
 676         */
 677        OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
 678         /* Dynamic state base address:
 679          * SAMPLER_STATE
 680          * SAMPLER_BORDER_COLOR_STATE
 681          * CLIP, SF, WM/CC viewport state
 682          * COLOR_CALC_STATE
 683          * DEPTH_STENCIL_STATE
 684          * BLEND_STATE
 685          * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
 686          * Disable is clear, which we rely on)
 687          */
 688        OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
 689                                    I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
 690
 691        OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
 692        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 693                  1); /* Instruction base address: shader kernels (incl. SIP) */
 694
 695        OUT_BATCH(1); /* General state upper bound */
 696        /* Dynamic state upper bound.  Although the documentation says that
 697         * programming it to zero will cause it to be ignored, that is a lie.
 698         * If this isn't programmed to a real bound, the sampler border color
 699         * pointer is rejected, causing border color to mysteriously fail.
 700         */
 701        OUT_BATCH(0xfffff001);
 702        OUT_BATCH(1); /* Indirect object upper bound */
 703        OUT_BATCH(1); /* Instruction access upper bound */
 704        ADVANCE_BATCH();
 705    } else if (brw->gen == 5) {
 706        BEGIN_BATCH(8);
 707        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 708        OUT_BATCH(1); /* General state base address */
 709        OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 710                  1); /* Surface state base address */
 711        OUT_BATCH(1); /* Indirect object base address */
 712        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 713                  1); /* Instruction base address */
 714        OUT_BATCH(0xfffff001); /* General state upper bound */
 715        OUT_BATCH(1); /* Indirect object upper bound */
 716        OUT_BATCH(1); /* Instruction access upper bound */
 717        ADVANCE_BATCH();
 718    } else {
 719        BEGIN_BATCH(6);
 720        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 721        OUT_BATCH(1); /* General state base address */
 722        OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 723                  1); /* Surface state base address */
 724        OUT_BATCH(1); /* Indirect object base address */
 725        OUT_BATCH(1); /* General state upper bound */
 726        OUT_BATCH(1); /* Indirect object upper bound */
 727        ADVANCE_BATCH();
 728    }
 729
 730    if (brw->gen >= 6) {
 731       brw_emit_pipe_control_flush(brw,
 732                                   PIPE_CONTROL_INSTRUCTION_INVALIDATE |
 733                                   PIPE_CONTROL_STATE_CACHE_INVALIDATE |
 734                                   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 735    }
 736
 737    /* According to section 3.6.1 of VOL1 of the 965 PRM,
 738     * STATE_BASE_ADDRESS updates require a reissue of:
 739     *
 740     * 3DSTATE_PIPELINE_POINTERS
 741     * 3DSTATE_BINDING_TABLE_POINTERS
 742     * MEDIA_STATE_POINTERS
 743     *
 744     * and this continues through Ironlake.  The Sandy Bridge PRM, vol
 745     * 1 part 1 says that the folowing packets must be reissued:
 746     *
 747     * 3DSTATE_CC_POINTERS
 748     * 3DSTATE_BINDING_TABLE_POINTERS
 749     * 3DSTATE_SAMPLER_STATE_POINTERS
 750     * 3DSTATE_VIEWPORT_STATE_POINTERS
 751     * MEDIA_STATE_POINTERS
 752     *
 753     * Those are always reissued following SBA updates anyway (new
 754     * batch time), except in the case of the program cache BO
 755     * changing.  Having a separate state flag makes the sequence more
 756     * obvious.
 757     */
 758
 759    brw->ctx.NewDriverState |= BRW_NEW_STATE_BASE_ADDRESS;
 760    brw->batch.state_base_address_emitted = true;
 761 }