2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_regions.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
42 /* Constant single cliprect for framebuffer object or DRI2 drawing */
43 static void upload_drawing_rect(struct brw_context
*brw
)
45 struct intel_context
*intel
= &brw
->intel
;
46 struct gl_context
*ctx
= &intel
->ctx
;
49 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
50 OUT_BATCH(0); /* xmin, ymin */
51 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
52 ((ctx
->DrawBuffer
->Height
- 1) << 16));
57 const struct brw_tracked_state brw_drawing_rect
= {
60 .brw
= BRW_NEW_CONTEXT
,
63 .emit
= upload_drawing_rect
67 * Upload the binding table pointers, which point each stage's array of surface
70 * The binding table pointers are relative to the surface state base address,
71 * which points at the batchbuffer containing the streamed batch state.
73 static void upload_binding_table_pointers(struct brw_context
*brw
)
75 struct intel_context
*intel
= &brw
->intel
;
78 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 | (6 - 2));
79 OUT_BATCH(brw
->vs
.bind_bo_offset
);
80 OUT_BATCH(0); /* gs */
81 OUT_BATCH(0); /* clip */
82 OUT_BATCH(0); /* sf */
83 OUT_BATCH(brw
->wm
.bind_bo_offset
);
87 const struct brw_tracked_state brw_binding_table_pointers
= {
90 .brw
= (BRW_NEW_BATCH
|
91 BRW_NEW_STATE_BASE_ADDRESS
|
92 BRW_NEW_VS_BINDING_TABLE
|
93 BRW_NEW_GS_BINDING_TABLE
|
94 BRW_NEW_PS_BINDING_TABLE
),
97 .emit
= upload_binding_table_pointers
,
101 * Upload the binding table pointers, which point each stage's array of surface
104 * The binding table pointers are relative to the surface state base address,
105 * which points at the batchbuffer containing the streamed batch state.
107 static void upload_gen6_binding_table_pointers(struct brw_context
*brw
)
109 struct intel_context
*intel
= &brw
->intel
;
112 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
113 GEN6_BINDING_TABLE_MODIFY_VS
|
114 GEN6_BINDING_TABLE_MODIFY_GS
|
115 GEN6_BINDING_TABLE_MODIFY_PS
|
117 OUT_BATCH(brw
->vs
.bind_bo_offset
); /* vs */
118 OUT_BATCH(0); /* gs */
119 OUT_BATCH(brw
->wm
.bind_bo_offset
); /* wm/ps */
123 const struct brw_tracked_state gen6_binding_table_pointers
= {
126 .brw
= (BRW_NEW_BATCH
|
127 BRW_NEW_STATE_BASE_ADDRESS
|
128 BRW_NEW_VS_BINDING_TABLE
|
129 BRW_NEW_GS_BINDING_TABLE
|
130 BRW_NEW_PS_BINDING_TABLE
),
133 .emit
= upload_gen6_binding_table_pointers
,
137 * Upload pointers to the per-stage state.
139 * The state pointers in this packet are all relative to the general state
140 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
142 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
144 struct intel_context
*intel
= &brw
->intel
;
146 if (intel
->gen
== 5) {
147 /* Need to flush before changing clip max threads for errata. */
154 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
155 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
156 brw
->vs
.state_offset
);
157 if (brw
->gs
.prog_active
)
158 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
159 brw
->gs
.state_offset
| 1);
162 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
163 brw
->clip
.state_offset
| 1);
164 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
165 brw
->sf
.state_offset
);
166 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
167 brw
->wm
.state_offset
);
168 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
169 brw
->cc
.state_offset
);
172 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
175 static void upload_psp_urb_cbs(struct brw_context
*brw
)
177 upload_pipelined_state_pointers(brw
);
178 brw_upload_urb_fence(brw
);
179 brw_upload_cs_urb_state(brw
);
182 const struct brw_tracked_state brw_psp_urb_cbs
= {
185 .brw
= (BRW_NEW_URB_FENCE
|
187 BRW_NEW_STATE_BASE_ADDRESS
),
188 .cache
= (CACHE_NEW_VS_UNIT
|
191 CACHE_NEW_CLIP_UNIT
|
196 .emit
= upload_psp_urb_cbs
,
199 static void emit_depthbuffer(struct brw_context
*brw
)
201 struct intel_context
*intel
= &brw
->intel
;
202 struct gl_context
*ctx
= &intel
->ctx
;
203 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
205 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
206 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
207 struct intel_region
*hiz_region
= depth_irb
? depth_irb
->hiz_region
: NULL
;
210 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
211 * non-pipelined state that will need the PIPE_CONTROL workaround.
213 if (intel
->gen
== 6) {
214 intel_emit_post_sync_nonzero_flush(intel
);
215 intel_emit_depth_stall_flushes(intel
);
219 * If either depth or stencil buffer has packed depth/stencil format,
220 * then don't use separate stencil. Emit only a depth buffer.
222 if (depth_irb
&& depth_irb
->Base
.Format
== MESA_FORMAT_S8_Z24
) {
224 } else if (!depth_irb
&& stencil_irb
225 && stencil_irb
->Base
.Format
== MESA_FORMAT_S8_Z24
) {
226 depth_irb
= stencil_irb
;
232 else if (intel
->is_g4x
|| intel
->gen
== 5)
237 if (!depth_irb
&& !stencil_irb
) {
239 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
240 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
241 (BRW_SURFACE_NULL
<< 29));
246 if (intel
->is_g4x
|| intel
->gen
>= 5)
254 } else if (!depth_irb
&& stencil_irb
) {
256 * There exists a separate stencil buffer but no depth buffer.
258 * The stencil buffer inherits most of its fields from
259 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
262 * Since the stencil buffer has quirky pitch requirements, its region
263 * was allocated with half height and double cpp. So we need
264 * a multiplier of 2 to obtain the surface's real height.
266 * Enable the hiz bit because it and the separate stencil bit must have
267 * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
268 * 1.21 "Separate Stencil Enable":
269 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
270 * Enable must also be enabled.
272 * [DevGT]: This field must be set to the same value (enabled or
273 * disabled) as Hierarchical Depth Buffer Enable
275 assert(intel
->has_separate_stencil
);
276 assert(stencil_irb
->Base
.Format
== MESA_FORMAT_S8
);
279 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
280 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
281 (1 << 21) | /* separate stencil enable */
282 (1 << 22) | /* hiz enable */
283 (BRW_TILEWALK_YMAJOR
<< 26) |
284 (BRW_SURFACE_2D
<< 29));
286 OUT_BATCH(((stencil_irb
->region
->width
- 1) << 6) |
287 (2 * stencil_irb
->region
->height
- 1) << 19);
297 struct intel_region
*region
= depth_irb
->region
;
299 uint32_t tile_x
, tile_y
, offset
;
301 /* If using separate stencil, hiz must be enabled. */
302 assert(!stencil_irb
|| hiz_region
);
304 switch (region
->cpp
) {
306 format
= BRW_DEPTHFORMAT_D16_UNORM
;
309 if (intel
->depth_buffer_is_float
)
310 format
= BRW_DEPTHFORMAT_D32_FLOAT
;
312 format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
314 format
= BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
321 offset
= intel_renderbuffer_tile_offsets(depth_irb
, &tile_x
, &tile_y
);
323 assert(intel
->gen
< 6 || region
->tiling
== I915_TILING_Y
);
324 assert(!hiz_region
|| region
->tiling
== I915_TILING_Y
);
327 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
328 OUT_BATCH(((region
->pitch
* region
->cpp
) - 1) |
330 ((hiz_region
? 1 : 0) << 21) | /* separate stencil enable */
331 ((hiz_region
? 1 : 0) << 22) | /* hiz enable */
332 (BRW_TILEWALK_YMAJOR
<< 26) |
333 ((region
->tiling
!= I915_TILING_NONE
) << 27) |
334 (BRW_SURFACE_2D
<< 29));
335 OUT_RELOC(region
->bo
,
336 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
338 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1) |
339 ((region
->width
- 1) << 6) |
340 ((region
->height
- 1) << 19));
343 if (intel
->is_g4x
|| intel
->gen
>= 5)
344 OUT_BATCH(tile_x
| (tile_y
<< 16));
346 assert(tile_x
== 0 && tile_y
== 0);
354 if (hiz_region
|| stencil_irb
) {
356 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
357 * stencil enable' and 'hiz enable' bits were set. Therefore we must
358 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
359 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
360 * failure to do so causes hangs on gen5 and a stall on gen6.
363 /* Emit hiz buffer. */
366 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
367 OUT_BATCH(hiz_region
->pitch
* hiz_region
->cpp
- 1);
368 OUT_RELOC(hiz_region
->bo
,
369 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
374 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
380 /* Emit stencil buffer. */
383 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
384 OUT_BATCH(stencil_irb
->region
->pitch
* stencil_irb
->region
->cpp
- 1);
385 OUT_RELOC(stencil_irb
->region
->bo
,
386 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
391 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
399 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
400 * params must be emitted.
402 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
403 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
404 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
406 if (intel
->gen
>= 6 || hiz_region
) {
408 intel_emit_post_sync_nonzero_flush(intel
);
411 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 | (2 - 2));
417 const struct brw_tracked_state brw_depthbuffer
= {
419 .mesa
= _NEW_BUFFERS
,
420 .brw
= BRW_NEW_BATCH
,
423 .emit
= emit_depthbuffer
,
428 /***********************************************************************
429 * Polygon stipple packet
432 static void upload_polygon_stipple(struct brw_context
*brw
)
434 struct intel_context
*intel
= &brw
->intel
;
435 struct gl_context
*ctx
= &brw
->intel
.ctx
;
439 if (!ctx
->Polygon
.StippleFlag
)
443 intel_emit_post_sync_nonzero_flush(intel
);
446 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
448 /* Polygon stipple is provided in OpenGL order, i.e. bottom
449 * row first. If we're rendering to a window (i.e. the
450 * default frame buffer object, 0), then we need to invert
451 * it to match our pixel layout. But if we're rendering
452 * to a FBO (i.e. any named frame buffer object), we *don't*
453 * need to invert - we already match the layout.
455 if (ctx
->DrawBuffer
->Name
== 0) {
456 for (i
= 0; i
< 32; i
++)
457 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
460 for (i
= 0; i
< 32; i
++)
461 OUT_BATCH(ctx
->PolygonStipple
[i
]);
466 const struct brw_tracked_state brw_polygon_stipple
= {
468 .mesa
= (_NEW_POLYGONSTIPPLE
|
470 .brw
= BRW_NEW_CONTEXT
,
473 .emit
= upload_polygon_stipple
477 /***********************************************************************
478 * Polygon stipple offset packet
481 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
483 struct intel_context
*intel
= &brw
->intel
;
484 struct gl_context
*ctx
= &brw
->intel
.ctx
;
487 if (!ctx
->Polygon
.StippleFlag
)
491 intel_emit_post_sync_nonzero_flush(intel
);
494 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
498 * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
499 * we have to invert the Y axis in order to match the OpenGL
500 * pixel coordinate system, and our offset must be matched
501 * to the window position. If we're drawing to a FBO
502 * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
503 * system works just fine, and there's no window system to
506 if (brw
->intel
.ctx
.DrawBuffer
->Name
== 0)
507 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
513 const struct brw_tracked_state brw_polygon_stipple_offset
= {
515 .mesa
= (_NEW_BUFFERS
|
517 .brw
= BRW_NEW_CONTEXT
,
520 .emit
= upload_polygon_stipple_offset
523 /**********************************************************************
526 static void upload_aa_line_parameters(struct brw_context
*brw
)
528 struct intel_context
*intel
= &brw
->intel
;
529 struct gl_context
*ctx
= &brw
->intel
.ctx
;
531 if (!ctx
->Line
.SmoothFlag
|| !brw
->has_aa_line_parameters
)
535 intel_emit_post_sync_nonzero_flush(intel
);
537 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
538 /* use legacy aa line coverage computation */
544 const struct brw_tracked_state brw_aa_line_parameters
= {
547 .brw
= BRW_NEW_CONTEXT
,
550 .emit
= upload_aa_line_parameters
553 /***********************************************************************
554 * Line stipple packet
557 static void upload_line_stipple(struct brw_context
*brw
)
559 struct intel_context
*intel
= &brw
->intel
;
560 struct gl_context
*ctx
= &brw
->intel
.ctx
;
564 if (!ctx
->Line
.StippleFlag
)
568 intel_emit_post_sync_nonzero_flush(intel
);
571 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
572 OUT_BATCH(ctx
->Line
.StipplePattern
);
573 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
574 tmpi
= tmp
* (1<<13);
575 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
579 const struct brw_tracked_state brw_line_stipple
= {
582 .brw
= BRW_NEW_CONTEXT
,
585 .emit
= upload_line_stipple
589 /***********************************************************************
590 * Misc invarient state packets
593 static void upload_invarient_state( struct brw_context
*brw
)
595 struct intel_context
*intel
= &brw
->intel
;
597 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
599 intel_emit_post_sync_nonzero_flush(intel
);
601 /* Select the 3D pipeline (as opposed to media) */
603 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16 | 0);
606 if (intel
->gen
< 6) {
607 /* Disable depth offset clamping. */
609 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
614 if (intel
->gen
>= 6) {
616 int len
= intel
->gen
>= 7 ? 4 : 3;
619 OUT_BATCH(_3DSTATE_MULTISAMPLE
<< 16 | (len
- 2));
620 OUT_BATCH(MS_PIXEL_LOCATION_CENTER
|
622 OUT_BATCH(0); /* positions for 4/8-sample */
628 OUT_BATCH(_3DSTATE_SAMPLE_MASK
<< 16 | (2 - 2));
632 if (intel
->gen
< 7) {
633 for (i
= 0; i
< 4; i
++) {
635 OUT_BATCH(_3DSTATE_GS_SVB_INDEX
<< 16 | (4 - 2));
636 OUT_BATCH(i
<< SVB_INDEX_SHIFT
);
638 OUT_BATCH(0xffffffff);
645 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
650 OUT_BATCH(brw
->CMD_VF_STATISTICS
<< 16 |
651 (unlikely(INTEL_DEBUG
& DEBUG_STATS
) ? 1 : 0));
655 const struct brw_tracked_state brw_invarient_state
= {
658 .brw
= BRW_NEW_CONTEXT
,
661 .emit
= upload_invarient_state
665 * Define the base addresses which some state is referenced from.
667 * This allows us to avoid having to emit relocations for the objects,
668 * and is actually required for binding table pointers on gen6.
670 * Surface state base address covers binding table pointers and
671 * surface state objects, but not the surfaces that the surface state
674 static void upload_state_base_address( struct brw_context
*brw
)
676 struct intel_context
*intel
= &brw
->intel
;
678 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
679 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
680 * programmed prior to STATE_BASE_ADDRESS.
682 * However, given that the instruction SBA (general state base
683 * address) on this chipset is always set to 0 across X and GL,
684 * maybe this isn't required for us in particular.
687 if (intel
->gen
>= 6) {
689 intel_emit_post_sync_nonzero_flush(intel
);
692 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
693 /* General state base address: stateless DP read/write requests */
695 /* Surface state base address:
696 * BINDING_TABLE_STATE
699 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
700 /* Dynamic state base address:
702 * SAMPLER_BORDER_COLOR_STATE
703 * CLIP, SF, WM/CC viewport state
705 * DEPTH_STENCIL_STATE
707 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
708 * Disable is clear, which we rely on)
710 OUT_RELOC(intel
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
711 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
713 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
714 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
715 1); /* Instruction base address: shader kernels (incl. SIP) */
717 OUT_BATCH(1); /* General state upper bound */
718 OUT_BATCH(1); /* Dynamic state upper bound */
719 OUT_BATCH(1); /* Indirect object upper bound */
720 OUT_BATCH(1); /* Instruction access upper bound */
722 } else if (intel
->gen
== 5) {
724 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
725 OUT_BATCH(1); /* General state base address */
726 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
727 1); /* Surface state base address */
728 OUT_BATCH(1); /* Indirect object base address */
729 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
730 1); /* Instruction base address */
731 OUT_BATCH(1); /* General state upper bound */
732 OUT_BATCH(1); /* Indirect object upper bound */
733 OUT_BATCH(1); /* Instruction access upper bound */
737 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
738 OUT_BATCH(1); /* General state base address */
739 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
740 1); /* Surface state base address */
741 OUT_BATCH(1); /* Indirect object base address */
742 OUT_BATCH(1); /* General state upper bound */
743 OUT_BATCH(1); /* Indirect object upper bound */
747 /* According to section 3.6.1 of VOL1 of the 965 PRM,
748 * STATE_BASE_ADDRESS updates require a reissue of:
750 * 3DSTATE_PIPELINE_POINTERS
751 * 3DSTATE_BINDING_TABLE_POINTERS
752 * MEDIA_STATE_POINTERS
754 * and this continues through Ironlake. The Sandy Bridge PRM, vol
755 * 1 part 1 says that the folowing packets must be reissued:
757 * 3DSTATE_CC_POINTERS
758 * 3DSTATE_BINDING_TABLE_POINTERS
759 * 3DSTATE_SAMPLER_STATE_POINTERS
760 * 3DSTATE_VIEWPORT_STATE_POINTERS
761 * MEDIA_STATE_POINTERS
763 * Those are always reissued following SBA updates anyway (new
764 * batch time), except in the case of the program cache BO
765 * changing. Having a separate state flag makes the sequence more
769 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
772 const struct brw_tracked_state brw_state_base_address
= {
775 .brw
= (BRW_NEW_BATCH
|
776 BRW_NEW_PROGRAM_CACHE
),
779 .emit
= upload_state_base_address