src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "intel_regions.h"
  37
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40 #include "brw_defines.h"
  41
  42 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  43 static void upload_drawing_rect(struct brw_context *brw)
  44 {
  45    struct intel_context *intel = &brw->intel;
  46    struct gl_context *ctx = &intel->ctx;
  47
  48    BEGIN_BATCH(4);
  49    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
  50    OUT_BATCH(0); /* xmin, ymin */
  51    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  52             ((ctx->DrawBuffer->Height - 1) << 16));
  53    OUT_BATCH(0);
  54    ADVANCE_BATCH();
  55 }
  56
  57 const struct brw_tracked_state brw_drawing_rect = {
  58    .dirty = {
  59       .mesa = _NEW_BUFFERS,
  60       .brw = BRW_NEW_CONTEXT,
  61       .cache = 0
  62    },
  63    .emit = upload_drawing_rect
  64 };
  65
  66 /**
  67  * Upload the binding table pointers, which point each stage's array of surface
  68  * state pointers.
  69  *
  70  * The binding table pointers are relative to the surface state base address,
  71  * which points at the batchbuffer containing the streamed batch state.
  72  */
  73 static void upload_binding_table_pointers(struct brw_context *brw)
  74 {
  75    struct intel_context *intel = &brw->intel;
  76
  77    BEGIN_BATCH(6);
  78    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
  79    OUT_BATCH(brw->vs.bind_bo_offset);
  80    OUT_BATCH(0); /* gs */
  81    OUT_BATCH(0); /* clip */
  82    OUT_BATCH(0); /* sf */
  83    OUT_BATCH(brw->wm.bind_bo_offset);
  84    ADVANCE_BATCH();
  85 }
  86
  87 const struct brw_tracked_state brw_binding_table_pointers = {
  88    .dirty = {
  89       .mesa = 0,
  90       .brw = (BRW_NEW_BATCH |
  91               BRW_NEW_STATE_BASE_ADDRESS |
  92               BRW_NEW_VS_BINDING_TABLE |
  93               BRW_NEW_GS_BINDING_TABLE |
  94               BRW_NEW_PS_BINDING_TABLE),
  95       .cache = 0,
  96    },
  97    .emit = upload_binding_table_pointers,
  98 };
  99
 100 /**
 101  * Upload the binding table pointers, which point each stage's array of surface
 102  * state pointers.
 103  *
 104  * The binding table pointers are relative to the surface state base address,
 105  * which points at the batchbuffer containing the streamed batch state.
 106  */
 107 static void upload_gen6_binding_table_pointers(struct brw_context *brw)
 108 {
 109    struct intel_context *intel = &brw->intel;
 110
 111    BEGIN_BATCH(4);
 112    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 113              GEN6_BINDING_TABLE_MODIFY_VS |
 114              GEN6_BINDING_TABLE_MODIFY_GS |
 115              GEN6_BINDING_TABLE_MODIFY_PS |
 116              (4 - 2));
 117    OUT_BATCH(brw->vs.bind_bo_offset); /* vs */
 118    OUT_BATCH(0); /* gs */
 119    OUT_BATCH(brw->wm.bind_bo_offset); /* wm/ps */
 120    ADVANCE_BATCH();
 121 }
 122
 123 const struct brw_tracked_state gen6_binding_table_pointers = {
 124    .dirty = {
 125       .mesa = 0,
 126       .brw = (BRW_NEW_BATCH |
 127               BRW_NEW_STATE_BASE_ADDRESS |
 128               BRW_NEW_VS_BINDING_TABLE |
 129               BRW_NEW_GS_BINDING_TABLE |
 130               BRW_NEW_PS_BINDING_TABLE),
 131       .cache = 0,
 132    },
 133    .emit = upload_gen6_binding_table_pointers,
 134 };
 135
 136 /**
 137  * Upload pointers to the per-stage state.
 138  *
 139  * The state pointers in this packet are all relative to the general state
 140  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 141  */
 142 static void upload_pipelined_state_pointers(struct brw_context *brw )
 143 {
 144    struct intel_context *intel = &brw->intel;
 145
 146    if (intel->gen == 5) {
 147       /* Need to flush before changing clip max threads for errata. */
 148       BEGIN_BATCH(1);
 149       OUT_BATCH(MI_FLUSH);
 150       ADVANCE_BATCH();
 151    }
 152
 153    BEGIN_BATCH(7);
 154    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
 155    OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 156              brw->vs.state_offset);
 157    if (brw->gs.prog_active)
 158       OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 159                 brw->gs.state_offset | 1);
 160    else
 161       OUT_BATCH(0);
 162    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 163              brw->clip.state_offset | 1);
 164    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 165              brw->sf.state_offset);
 166    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 167              brw->wm.state_offset);
 168    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 169              brw->cc.state_offset);
 170    ADVANCE_BATCH();
 171
 172    brw->state.dirty.brw |= BRW_NEW_PSP;
 173 }
 174
 175 static void upload_psp_urb_cbs(struct brw_context *brw )
 176 {
 177    upload_pipelined_state_pointers(brw);
 178    brw_upload_urb_fence(brw);
 179    brw_upload_cs_urb_state(brw);
 180 }
 181
 182 const struct brw_tracked_state brw_psp_urb_cbs = {
 183    .dirty = {
 184       .mesa = 0,
 185       .brw = (BRW_NEW_URB_FENCE |
 186               BRW_NEW_BATCH |
 187               BRW_NEW_STATE_BASE_ADDRESS),
 188       .cache = (CACHE_NEW_VS_UNIT |
 189                 CACHE_NEW_GS_UNIT |
 190                 CACHE_NEW_GS_PROG |
 191                 CACHE_NEW_CLIP_UNIT |
 192                 CACHE_NEW_SF_UNIT |
 193                 CACHE_NEW_WM_UNIT |
 194                 CACHE_NEW_CC_UNIT)
 195    },
 196    .emit = upload_psp_urb_cbs,
 197 };
 198
 199 static void emit_depthbuffer(struct brw_context *brw)
 200 {
 201    struct intel_context *intel = &brw->intel;
 202    struct gl_context *ctx = &intel->ctx;
 203    struct gl_framebuffer *fb = ctx->DrawBuffer;
 204    /* _NEW_BUFFERS */
 205    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 206    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 207    struct intel_region *hiz_region = depth_irb ? depth_irb->hiz_region : NULL;
 208    unsigned int len;
 209
 210    /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
 211     * non-pipelined state that will need the PIPE_CONTROL workaround.
 212     */
 213    if (intel->gen == 6) {
 214       intel_emit_post_sync_nonzero_flush(intel);
 215       intel_emit_depth_stall_flushes(intel);
 216    }
 217
 218    /*
 219     * If either depth or stencil buffer has packed depth/stencil format,
 220     * then don't use separate stencil. Emit only a depth buffer.
 221     */
 222    if (depth_irb && depth_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 223       stencil_irb = NULL;
 224    } else if (!depth_irb && stencil_irb
 225               && stencil_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 226       depth_irb = stencil_irb;
 227       stencil_irb = NULL;
 228    }
 229
 230    if (intel->gen >= 6)
 231       len = 7;
 232    else if (intel->is_g4x || intel->gen == 5)
 233       len = 6;
 234    else
 235       len = 5;
 236
 237    if (!depth_irb && !stencil_irb) {
 238       BEGIN_BATCH(len);
 239       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 240       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 241                 (BRW_SURFACE_NULL << 29));
 242       OUT_BATCH(0);
 243       OUT_BATCH(0);
 244       OUT_BATCH(0);
 245
 246       if (intel->is_g4x || intel->gen >= 5)
 247          OUT_BATCH(0);
 248
 249       if (intel->gen >= 6)
 250          OUT_BATCH(0);
 251
 252       ADVANCE_BATCH();
 253
 254    } else if (!depth_irb && stencil_irb) {
 255       /*
 256        * There exists a separate stencil buffer but no depth buffer.
 257        *
 258        * The stencil buffer inherits most of its fields from
 259        * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
 260        * height.
 261        *
 262        * Since the stencil buffer has quirky pitch requirements, its region
 263        * was allocated with half height and double cpp. So we need
 264        * a multiplier of 2 to obtain the surface's real height.
 265        *
 266        * Enable the hiz bit because it and the separate stencil bit must have
 267        * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
 268        * 1.21 "Separate Stencil Enable":
 269        *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
 270        *     Enable must also be enabled.
 271        *
 272        *     [DevGT]: This field must be set to the same value (enabled or
 273        *     disabled) as Hierarchical Depth Buffer Enable
 274        */
 275       assert(intel->has_separate_stencil);
 276       assert(stencil_irb->Base.Format == MESA_FORMAT_S8);
 277
 278       BEGIN_BATCH(len);
 279       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 280       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 281                 (1 << 21) | /* separate stencil enable */
 282                 (1 << 22) | /* hiz enable */
 283                 (BRW_TILEWALK_YMAJOR << 26) |
 284                 (BRW_SURFACE_2D << 29));
 285       OUT_BATCH(0);
 286       OUT_BATCH(((stencil_irb->region->width - 1) << 6) |
 287                  (2 * stencil_irb->region->height - 1) << 19);
 288       OUT_BATCH(0);
 289       OUT_BATCH(0);
 290
 291       if (intel->gen >= 6)
 292          OUT_BATCH(0);
 293
 294       ADVANCE_BATCH();
 295
 296    } else {
 297       struct intel_region *region = depth_irb->region;
 298       unsigned int format;
 299       uint32_t tile_x, tile_y, offset;
 300
 301       /* If using separate stencil, hiz must be enabled. */
 302       assert(!stencil_irb || hiz_region);
 303
 304       switch (region->cpp) {
 305       case 2:
 306          format = BRW_DEPTHFORMAT_D16_UNORM;
 307          break;
 308       case 4:
 309          if (intel->depth_buffer_is_float)
 310             format = BRW_DEPTHFORMAT_D32_FLOAT;
 311          else if (hiz_region)
 312             format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 313          else
 314             format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 315          break;
 316       default:
 317          assert(0);
 318          return;
 319       }
 320
 321       offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y);
 322
 323       assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
 324       assert(!hiz_region || region->tiling == I915_TILING_Y);
 325
 326       BEGIN_BATCH(len);
 327       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 328       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 329                 (format << 18) |
 330                 ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */
 331                 ((hiz_region ? 1 : 0) << 22) | /* hiz enable */
 332                 (BRW_TILEWALK_YMAJOR << 26) |
 333                 ((region->tiling != I915_TILING_NONE) << 27) |
 334                 (BRW_SURFACE_2D << 29));
 335       OUT_RELOC(region->bo,
 336                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 337                 offset);
 338       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 339                 ((region->width - 1) << 6) |
 340                 ((region->height - 1) << 19));
 341       OUT_BATCH(0);
 342
 343       if (intel->is_g4x || intel->gen >= 5)
 344          OUT_BATCH(tile_x | (tile_y << 16));
 345       else
 346          assert(tile_x == 0 && tile_y == 0);
 347
 348       if (intel->gen >= 6)
 349          OUT_BATCH(0);
 350
 351       ADVANCE_BATCH();
 352    }
 353
 354    if (hiz_region || stencil_irb) {
 355       /*
 356        * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
 357        * stencil enable' and 'hiz enable' bits were set. Therefore we must
 358        * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
 359        * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
 360        * failure to do so causes hangs on gen5 and a stall on gen6.
 361        */
 362
 363       /* Emit hiz buffer. */
 364       if (hiz_region) {
 365          BEGIN_BATCH(3);
 366          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 367          OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 368          OUT_RELOC(hiz_region->bo,
 369                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 370                    0);
 371          ADVANCE_BATCH();
 372       } else {
 373          BEGIN_BATCH(3);
 374          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 375          OUT_BATCH(0);
 376          OUT_BATCH(0);
 377          ADVANCE_BATCH();
 378       }
 379
 380       /* Emit stencil buffer. */
 381       if (stencil_irb) {
 382          BEGIN_BATCH(3);
 383          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 384          OUT_BATCH(stencil_irb->region->pitch * stencil_irb->region->cpp - 1);
 385          OUT_RELOC(stencil_irb->region->bo,
 386                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 387                    0);
 388          ADVANCE_BATCH();
 389       } else {
 390          BEGIN_BATCH(3);
 391          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 392          OUT_BATCH(0);
 393          OUT_BATCH(0);
 394          ADVANCE_BATCH();
 395       }
 396    }
 397
 398    /*
 399     * On Gen >= 6, emit clear params for safety. If using hiz, then clear
 400     * params must be emitted.
 401     *
 402     * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
 403     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
 404     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 405     */
 406    if (intel->gen >= 6 || hiz_region) {
 407       if (intel->gen == 6)
 408          intel_emit_post_sync_nonzero_flush(intel);
 409
 410       BEGIN_BATCH(2);
 411       OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
 412       OUT_BATCH(0);
 413       ADVANCE_BATCH();
 414    }
 415 }
 416
 417 const struct brw_tracked_state brw_depthbuffer = {
 418    .dirty = {
 419       .mesa = _NEW_BUFFERS,
 420       .brw = BRW_NEW_BATCH,
 421       .cache = 0,
 422    },
 423    .emit = emit_depthbuffer,
 424 };
 425
 426
 427
 428 /***********************************************************************
 429  * Polygon stipple packet
 430  */
 431
 432 static void upload_polygon_stipple(struct brw_context *brw)
 433 {
 434    struct intel_context *intel = &brw->intel;
 435    struct gl_context *ctx = &brw->intel.ctx;
 436    GLuint i;
 437
 438    /* _NEW_POLYGON */
 439    if (!ctx->Polygon.StippleFlag)
 440       return;
 441
 442    if (intel->gen == 6)
 443       intel_emit_post_sync_nonzero_flush(intel);
 444
 445    BEGIN_BATCH(33);
 446    OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
 447
 448    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 449     * row first.  If we're rendering to a window (i.e. the
 450     * default frame buffer object, 0), then we need to invert
 451     * it to match our pixel layout.  But if we're rendering
 452     * to a FBO (i.e. any named frame buffer object), we *don't*
 453     * need to invert - we already match the layout.
 454     */
 455    if (ctx->DrawBuffer->Name == 0) {
 456       for (i = 0; i < 32; i++)
 457           OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
 458    }
 459    else {
 460       for (i = 0; i < 32; i++)
 461          OUT_BATCH(ctx->PolygonStipple[i]);
 462    }
 463    CACHED_BATCH();
 464 }
 465
 466 const struct brw_tracked_state brw_polygon_stipple = {
 467    .dirty = {
 468       .mesa = (_NEW_POLYGONSTIPPLE |
 469                _NEW_POLYGON),
 470       .brw = BRW_NEW_CONTEXT,
 471       .cache = 0
 472    },
 473    .emit = upload_polygon_stipple
 474 };
 475
 476
 477 /***********************************************************************
 478  * Polygon stipple offset packet
 479  */
 480
 481 static void upload_polygon_stipple_offset(struct brw_context *brw)
 482 {
 483    struct intel_context *intel = &brw->intel;
 484    struct gl_context *ctx = &brw->intel.ctx;
 485
 486    /* _NEW_POLYGON */
 487    if (!ctx->Polygon.StippleFlag)
 488       return;
 489
 490    if (intel->gen == 6)
 491       intel_emit_post_sync_nonzero_flush(intel);
 492
 493    BEGIN_BATCH(2);
 494    OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
 495
 496    /* _NEW_BUFFERS
 497     *
 498     * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 499     * we have to invert the Y axis in order to match the OpenGL
 500     * pixel coordinate system, and our offset must be matched
 501     * to the window position.  If we're drawing to a FBO
 502     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 503     * system works just fine, and there's no window system to
 504     * worry about.
 505     */
 506    if (brw->intel.ctx.DrawBuffer->Name == 0)
 507       OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
 508    else
 509       OUT_BATCH(0);
 510    CACHED_BATCH();
 511 }
 512
 513 const struct brw_tracked_state brw_polygon_stipple_offset = {
 514    .dirty = {
 515       .mesa = (_NEW_BUFFERS |
 516                _NEW_POLYGON),
 517       .brw = BRW_NEW_CONTEXT,
 518       .cache = 0
 519    },
 520    .emit = upload_polygon_stipple_offset
 521 };
 522
 523 /**********************************************************************
 524  * AA Line parameters
 525  */
 526 static void upload_aa_line_parameters(struct brw_context *brw)
 527 {
 528    struct intel_context *intel = &brw->intel;
 529    struct gl_context *ctx = &brw->intel.ctx;
 530
 531    if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
 532       return;
 533
 534    if (intel->gen == 6)
 535       intel_emit_post_sync_nonzero_flush(intel);
 536
 537    OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
 538    /* use legacy aa line coverage computation */
 539    OUT_BATCH(0);
 540    OUT_BATCH(0);
 541    CACHED_BATCH();
 542 }
 543
 544 const struct brw_tracked_state brw_aa_line_parameters = {
 545    .dirty = {
 546       .mesa = _NEW_LINE,
 547       .brw = BRW_NEW_CONTEXT,
 548       .cache = 0
 549    },
 550    .emit = upload_aa_line_parameters
 551 };
 552
 553 /***********************************************************************
 554  * Line stipple packet
 555  */
 556
 557 static void upload_line_stipple(struct brw_context *brw)
 558 {
 559    struct intel_context *intel = &brw->intel;
 560    struct gl_context *ctx = &brw->intel.ctx;
 561    GLfloat tmp;
 562    GLint tmpi;
 563
 564    if (!ctx->Line.StippleFlag)
 565       return;
 566
 567    if (intel->gen == 6)
 568       intel_emit_post_sync_nonzero_flush(intel);
 569
 570    BEGIN_BATCH(3);
 571    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
 572    OUT_BATCH(ctx->Line.StipplePattern);
 573    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 574    tmpi = tmp * (1<<13);
 575    OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
 576    CACHED_BATCH();
 577 }
 578
 579 const struct brw_tracked_state brw_line_stipple = {
 580    .dirty = {
 581       .mesa = _NEW_LINE,
 582       .brw = BRW_NEW_CONTEXT,
 583       .cache = 0
 584    },
 585    .emit = upload_line_stipple
 586 };
 587
 588
 589 /***********************************************************************
 590  * Misc invarient state packets
 591  */
 592
 593 static void upload_invarient_state( struct brw_context *brw )
 594 {
 595    struct intel_context *intel = &brw->intel;
 596
 597    /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
 598    if (intel->gen == 6)
 599       intel_emit_post_sync_nonzero_flush(intel);
 600
 601    /* Select the 3D pipeline (as opposed to media) */
 602    BEGIN_BATCH(1);
 603    OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0);
 604    ADVANCE_BATCH();
 605
 606    if (intel->gen < 6) {
 607       /* Disable depth offset clamping. */
 608       BEGIN_BATCH(2);
 609       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
 610       OUT_BATCH_F(0.0);
 611       ADVANCE_BATCH();
 612    }
 613
 614    if (intel->gen >= 6) {
 615       int i;
 616       int len = intel->gen >= 7 ? 4 : 3;
 617
 618       BEGIN_BATCH(len);
 619       OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
 620       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
 621                 MS_NUMSAMPLES_1);
 622       OUT_BATCH(0); /* positions for 4/8-sample */
 623       if (intel->gen >= 7)
 624          OUT_BATCH(0);
 625       ADVANCE_BATCH();
 626
 627       BEGIN_BATCH(2);
 628       OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
 629       OUT_BATCH(1);
 630       ADVANCE_BATCH();
 631
 632       if (intel->gen < 7) {
 633          for (i = 0; i < 4; i++) {
 634             BEGIN_BATCH(4);
 635             OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
 636             OUT_BATCH(i << SVB_INDEX_SHIFT);
 637             OUT_BATCH(0);
 638             OUT_BATCH(0xffffffff);
 639             ADVANCE_BATCH();
 640          }
 641       }
 642    }
 643
 644    BEGIN_BATCH(2);
 645    OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2));
 646    OUT_BATCH(0);
 647    ADVANCE_BATCH();
 648
 649    BEGIN_BATCH(1);
 650    OUT_BATCH(brw->CMD_VF_STATISTICS << 16 |
 651              (unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0));
 652    ADVANCE_BATCH();
 653 }
 654
 655 const struct brw_tracked_state brw_invarient_state = {
 656    .dirty = {
 657       .mesa = 0,
 658       .brw = BRW_NEW_CONTEXT,
 659       .cache = 0
 660    },
 661    .emit = upload_invarient_state
 662 };
 663
 664 /**
 665  * Define the base addresses which some state is referenced from.
 666  *
 667  * This allows us to avoid having to emit relocations for the objects,
 668  * and is actually required for binding table pointers on gen6.
 669  *
 670  * Surface state base address covers binding table pointers and
 671  * surface state objects, but not the surfaces that the surface state
 672  * objects point to.
 673  */
 674 static void upload_state_base_address( struct brw_context *brw )
 675 {
 676    struct intel_context *intel = &brw->intel;
 677
 678    /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
 679     * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
 680     * programmed prior to STATE_BASE_ADDRESS.
 681     *
 682     * However, given that the instruction SBA (general state base
 683     * address) on this chipset is always set to 0 across X and GL,
 684     * maybe this isn't required for us in particular.
 685     */
 686
 687    if (intel->gen >= 6) {
 688       if (intel->gen == 6)
 689          intel_emit_post_sync_nonzero_flush(intel);
 690
 691        BEGIN_BATCH(10);
 692        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
 693        /* General state base address: stateless DP read/write requests */
 694        OUT_BATCH(1);
 695        /* Surface state base address:
 696         * BINDING_TABLE_STATE
 697         * SURFACE_STATE
 698         */
 699        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
 700         /* Dynamic state base address:
 701          * SAMPLER_STATE
 702          * SAMPLER_BORDER_COLOR_STATE
 703          * CLIP, SF, WM/CC viewport state
 704          * COLOR_CALC_STATE
 705          * DEPTH_STENCIL_STATE
 706          * BLEND_STATE
 707          * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
 708          * Disable is clear, which we rely on)
 709          */
 710        OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
 711                                    I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
 712
 713        OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
 714        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 715                  1); /* Instruction base address: shader kernels (incl. SIP) */
 716
 717        OUT_BATCH(1); /* General state upper bound */
 718        OUT_BATCH(1); /* Dynamic state upper bound */
 719        OUT_BATCH(1); /* Indirect object upper bound */
 720        OUT_BATCH(1); /* Instruction access upper bound */
 721        ADVANCE_BATCH();
 722    } else if (intel->gen == 5) {
 723        BEGIN_BATCH(8);
 724        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 725        OUT_BATCH(1); /* General state base address */
 726        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 727                  1); /* Surface state base address */
 728        OUT_BATCH(1); /* Indirect object base address */
 729        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 730                  1); /* Instruction base address */
 731        OUT_BATCH(1); /* General state upper bound */
 732        OUT_BATCH(1); /* Indirect object upper bound */
 733        OUT_BATCH(1); /* Instruction access upper bound */
 734        ADVANCE_BATCH();
 735    } else {
 736        BEGIN_BATCH(6);
 737        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 738        OUT_BATCH(1); /* General state base address */
 739        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 740                  1); /* Surface state base address */
 741        OUT_BATCH(1); /* Indirect object base address */
 742        OUT_BATCH(1); /* General state upper bound */
 743        OUT_BATCH(1); /* Indirect object upper bound */
 744        ADVANCE_BATCH();
 745    }
 746
 747    /* According to section 3.6.1 of VOL1 of the 965 PRM,
 748     * STATE_BASE_ADDRESS updates require a reissue of:
 749     *
 750     * 3DSTATE_PIPELINE_POINTERS
 751     * 3DSTATE_BINDING_TABLE_POINTERS
 752     * MEDIA_STATE_POINTERS
 753     *
 754     * and this continues through Ironlake.  The Sandy Bridge PRM, vol
 755     * 1 part 1 says that the folowing packets must be reissued:
 756     *
 757     * 3DSTATE_CC_POINTERS
 758     * 3DSTATE_BINDING_TABLE_POINTERS
 759     * 3DSTATE_SAMPLER_STATE_POINTERS
 760     * 3DSTATE_VIEWPORT_STATE_POINTERS
 761     * MEDIA_STATE_POINTERS
 762     *
 763     * Those are always reissued following SBA updates anyway (new
 764     * batch time), except in the case of the program cache BO
 765     * changing.  Having a separate state flag makes the sequence more
 766     * obvious.
 767     */
 768
 769    brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
 770 }
 771
 772 const struct brw_tracked_state brw_state_base_address = {
 773    .dirty = {
 774       .mesa = 0,
 775       .brw = (BRW_NEW_BATCH |
 776               BRW_NEW_PROGRAM_CACHE),
 777       .cache = 0,
 778    },
 779    .emit = upload_state_base_address
 780 };