2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_regions.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
39 #include "brw_defines.h"
45 /***********************************************************************
49 static void upload_blend_constant_color(struct brw_context
*brw
)
51 GLcontext
*ctx
= &brw
->intel
.ctx
;
52 struct brw_blend_constant_color bcc
;
54 memset(&bcc
, 0, sizeof(bcc
));
55 bcc
.header
.opcode
= CMD_BLEND_CONSTANT_COLOR
;
56 bcc
.header
.length
= sizeof(bcc
)/4-2;
57 bcc
.blend_constant_color
[0] = ctx
->Color
.BlendColor
[0];
58 bcc
.blend_constant_color
[1] = ctx
->Color
.BlendColor
[1];
59 bcc
.blend_constant_color
[2] = ctx
->Color
.BlendColor
[2];
60 bcc
.blend_constant_color
[3] = ctx
->Color
.BlendColor
[3];
62 BRW_CACHED_BATCH_STRUCT(brw
, &bcc
);
66 const struct brw_tracked_state brw_blend_constant_color
= {
72 .emit
= upload_blend_constant_color
75 /* Constant single cliprect for framebuffer object or DRI2 drawing */
76 static void upload_drawing_rect(struct brw_context
*brw
)
78 struct intel_context
*intel
= &brw
->intel
;
79 GLcontext
*ctx
= &intel
->ctx
;
81 if (!intel
->constant_cliprect
)
84 BEGIN_BATCH(4, NO_LOOP_CLIPRECTS
);
85 OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965
);
86 OUT_BATCH(0); /* xmin, ymin */
87 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
88 ((ctx
->DrawBuffer
->Height
- 1) << 16));
93 const struct brw_tracked_state brw_drawing_rect
= {
99 .emit
= upload_drawing_rect
102 static void prepare_binding_table_pointers(struct brw_context
*brw
)
104 brw_add_validated_bo(brw
, brw
->wm
.bind_bo
);
108 * Upload the binding table pointers, which point each stage's array of surface
111 * The binding table pointers are relative to the surface state base address,
114 static void upload_binding_table_pointers(struct brw_context
*brw
)
116 struct intel_context
*intel
= &brw
->intel
;
118 BEGIN_BATCH(6, IGNORE_CLIPRECTS
);
119 OUT_BATCH(CMD_BINDING_TABLE_PTRS
<< 16 | (6 - 2));
120 OUT_BATCH(0); /* vs */
121 OUT_BATCH(0); /* gs */
122 OUT_BATCH(0); /* clip */
123 OUT_BATCH(0); /* sf */
124 OUT_RELOC(brw
->wm
.bind_bo
,
125 I915_GEM_DOMAIN_SAMPLER
, 0,
130 const struct brw_tracked_state brw_binding_table_pointers
= {
133 .brw
= BRW_NEW_BATCH
,
134 .cache
= CACHE_NEW_SURF_BIND
,
136 .prepare
= prepare_binding_table_pointers
,
137 .emit
= upload_binding_table_pointers
,
142 * Upload pointers to the per-stage state.
144 * The state pointers in this packet are all relative to the general state
145 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
147 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
149 struct intel_context
*intel
= &brw
->intel
;
151 BEGIN_BATCH(7, IGNORE_CLIPRECTS
);
152 OUT_BATCH(CMD_PIPELINED_STATE_POINTERS
<< 16 | (7 - 2));
153 OUT_RELOC(brw
->vs
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
154 if (brw
->gs
.prog_active
)
155 OUT_RELOC(brw
->gs
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 1);
158 OUT_RELOC(brw
->clip
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 1);
159 OUT_RELOC(brw
->sf
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
160 OUT_RELOC(brw
->wm
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
161 OUT_RELOC(brw
->cc
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
164 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
168 static void prepare_psp_urb_cbs(struct brw_context
*brw
)
170 brw_add_validated_bo(brw
, brw
->vs
.state_bo
);
171 brw_add_validated_bo(brw
, brw
->gs
.state_bo
);
172 brw_add_validated_bo(brw
, brw
->clip
.state_bo
);
173 brw_add_validated_bo(brw
, brw
->wm
.state_bo
);
174 brw_add_validated_bo(brw
, brw
->cc
.state_bo
);
177 static void upload_psp_urb_cbs(struct brw_context
*brw
)
179 upload_pipelined_state_pointers(brw
);
180 brw_upload_urb_fence(brw
);
181 brw_upload_constant_buffer_state(brw
);
184 const struct brw_tracked_state brw_psp_urb_cbs
= {
187 .brw
= BRW_NEW_URB_FENCE
| BRW_NEW_BATCH
,
188 .cache
= (CACHE_NEW_VS_UNIT
|
191 CACHE_NEW_CLIP_UNIT
|
196 .prepare
= prepare_psp_urb_cbs
,
197 .emit
= upload_psp_urb_cbs
,
200 static void prepare_depthbuffer(struct brw_context
*brw
)
202 struct intel_region
*region
= brw
->state
.depth_region
;
205 brw_add_validated_bo(brw
, region
->buffer
);
208 static void emit_depthbuffer(struct brw_context
*brw
)
210 struct intel_context
*intel
= &brw
->intel
;
211 struct intel_region
*region
= brw
->state
.depth_region
;
212 unsigned int len
= BRW_IS_G4X(brw
) ? 6 : 5;
214 if (region
== NULL
) {
215 BEGIN_BATCH(len
, IGNORE_CLIPRECTS
);
216 OUT_BATCH(CMD_DEPTH_BUFFER
<< 16 | (len
- 2));
217 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
218 (BRW_SURFACE_NULL
<< 29));
230 switch (region
->cpp
) {
232 format
= BRW_DEPTHFORMAT_D16_UNORM
;
235 if (intel
->depth_buffer_is_float
)
236 format
= BRW_DEPTHFORMAT_D32_FLOAT
;
238 format
= BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
245 BEGIN_BATCH(len
, IGNORE_CLIPRECTS
);
246 OUT_BATCH(CMD_DEPTH_BUFFER
<< 16 | (len
- 2));
247 OUT_BATCH(((region
->pitch
* region
->cpp
) - 1) |
249 (BRW_TILEWALK_YMAJOR
<< 26) |
250 ((region
->tiling
!= I915_TILING_NONE
) << 27) |
251 (BRW_SURFACE_2D
<< 29));
252 OUT_RELOC(region
->buffer
,
253 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
255 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1) |
256 ((region
->pitch
- 1) << 6) |
257 ((region
->height
- 1) << 19));
267 const struct brw_tracked_state brw_depthbuffer
= {
270 .brw
= BRW_NEW_DEPTH_BUFFER
| BRW_NEW_BATCH
,
273 .prepare
= prepare_depthbuffer
,
274 .emit
= emit_depthbuffer
,
279 /***********************************************************************
280 * Polygon stipple packet
283 static void upload_polygon_stipple(struct brw_context
*brw
)
285 GLcontext
*ctx
= &brw
->intel
.ctx
;
286 struct brw_polygon_stipple bps
;
289 memset(&bps
, 0, sizeof(bps
));
290 bps
.header
.opcode
= CMD_POLY_STIPPLE_PATTERN
;
291 bps
.header
.length
= sizeof(bps
)/4-2;
293 for (i
= 0; i
< 32; i
++)
294 bps
.stipple
[i
] = ctx
->PolygonStipple
[31 - i
]; /* invert */
296 BRW_CACHED_BATCH_STRUCT(brw
, &bps
);
299 const struct brw_tracked_state brw_polygon_stipple
= {
301 .mesa
= _NEW_POLYGONSTIPPLE
,
305 .emit
= upload_polygon_stipple
309 /***********************************************************************
310 * Polygon stipple offset packet
313 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
315 __DRIdrawablePrivate
*dPriv
= brw
->intel
.driDrawable
;
316 struct brw_polygon_stipple_offset bpso
;
318 memset(&bpso
, 0, sizeof(bpso
));
319 bpso
.header
.opcode
= CMD_POLY_STIPPLE_OFFSET
;
320 bpso
.header
.length
= sizeof(bpso
)/4-2;
322 bpso
.bits0
.x_offset
= (32 - (dPriv
->x
& 31)) & 31;
323 bpso
.bits0
.y_offset
= (32 - ((dPriv
->y
+ dPriv
->h
) & 31)) & 31;
325 BRW_CACHED_BATCH_STRUCT(brw
, &bpso
);
328 #define _NEW_WINDOW_POS 0x40000000
330 const struct brw_tracked_state brw_polygon_stipple_offset
= {
332 .mesa
= _NEW_WINDOW_POS
,
336 .emit
= upload_polygon_stipple_offset
339 /**********************************************************************
342 static void upload_aa_line_parameters(struct brw_context
*brw
)
344 struct brw_aa_line_parameters balp
;
346 if (!BRW_IS_G4X(brw
))
349 /* use legacy aa line coverage computation */
350 memset(&balp
, 0, sizeof(balp
));
351 balp
.header
.opcode
= CMD_AA_LINE_PARAMETERS
;
352 balp
.header
.length
= sizeof(balp
) / 4 - 2;
354 BRW_CACHED_BATCH_STRUCT(brw
, &balp
);
357 const struct brw_tracked_state brw_aa_line_parameters
= {
360 .brw
= BRW_NEW_CONTEXT
,
363 .emit
= upload_aa_line_parameters
366 /***********************************************************************
367 * Line stipple packet
370 static void upload_line_stipple(struct brw_context
*brw
)
372 GLcontext
*ctx
= &brw
->intel
.ctx
;
373 struct brw_line_stipple bls
;
377 memset(&bls
, 0, sizeof(bls
));
378 bls
.header
.opcode
= CMD_LINE_STIPPLE_PATTERN
;
379 bls
.header
.length
= sizeof(bls
)/4 - 2;
381 bls
.bits0
.pattern
= ctx
->Line
.StipplePattern
;
382 bls
.bits1
.repeat_count
= ctx
->Line
.StippleFactor
;
384 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
385 tmpi
= tmp
* (1<<13);
388 bls
.bits1
.inverse_repeat_count
= tmpi
;
390 BRW_CACHED_BATCH_STRUCT(brw
, &bls
);
393 const struct brw_tracked_state brw_line_stipple
= {
399 .emit
= upload_line_stipple
403 /***********************************************************************
404 * Misc invarient state packets
407 static void upload_invarient_state( struct brw_context
*brw
)
410 /* 0x61040000 Pipeline Select */
411 /* PipelineSelect : 0 */
412 struct brw_pipeline_select ps
;
414 memset(&ps
, 0, sizeof(ps
));
415 ps
.header
.opcode
= CMD_PIPELINE_SELECT(brw
);
416 ps
.header
.pipeline_select
= 0;
417 BRW_BATCH_STRUCT(brw
, &ps
);
421 struct brw_global_depth_offset_clamp gdo
;
422 memset(&gdo
, 0, sizeof(gdo
));
424 /* Disable depth offset clamping.
426 gdo
.header
.opcode
= CMD_GLOBAL_DEPTH_OFFSET_CLAMP
;
427 gdo
.header
.length
= sizeof(gdo
)/4 - 2;
428 gdo
.depth_offset_clamp
= 0.0;
430 BRW_BATCH_STRUCT(brw
, &gdo
);
434 /* 0x61020000 State Instruction Pointer */
436 struct brw_system_instruction_pointer sip
;
437 memset(&sip
, 0, sizeof(sip
));
439 sip
.header
.opcode
= CMD_STATE_INSN_POINTER
;
440 sip
.header
.length
= 0;
442 sip
.bits0
.system_instruction_pointer
= 0;
443 BRW_BATCH_STRUCT(brw
, &sip
);
448 struct brw_vf_statistics vfs
;
449 memset(&vfs
, 0, sizeof(vfs
));
451 vfs
.opcode
= CMD_VF_STATISTICS(brw
);
452 if (INTEL_DEBUG
& DEBUG_STATS
)
453 vfs
.statistics_enable
= 1;
455 BRW_BATCH_STRUCT(brw
, &vfs
);
459 const struct brw_tracked_state brw_invarient_state
= {
462 .brw
= BRW_NEW_CONTEXT
,
465 .emit
= upload_invarient_state
469 * Define the base addresses which some state is referenced from.
471 * This allows us to avoid having to emit relocations in many places for
472 * cached state, and instead emit pointers inside of large, mostly-static
473 * state pools. This comes at the expense of memory, and more expensive cache
476 static void upload_state_base_address( struct brw_context
*brw
)
478 struct intel_context
*intel
= &brw
->intel
;
480 /* Output the structure (brw_state_base_address) directly to the
481 * batchbuffer, so we can emit relocations inline.
483 BEGIN_BATCH(6, IGNORE_CLIPRECTS
);
484 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
485 OUT_BATCH(1); /* General state base address */
486 OUT_BATCH(1); /* Surface state base address */
487 OUT_BATCH(1); /* Indirect object base address */
488 OUT_BATCH(1); /* General state upper bound */
489 OUT_BATCH(1); /* Indirect object upper bound */
493 const struct brw_tracked_state brw_state_base_address
= {
496 .brw
= BRW_NEW_CONTEXT
,
499 .emit
= upload_state_base_address