2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
37 #include "intel_regions.h"
39 #include "brw_context.h"
40 #include "brw_state.h"
41 #include "brw_defines.h"
43 #include "main/fbobject.h"
44 #include "main/glformats.h"
46 /* Constant single cliprect for framebuffer object or DRI2 drawing */
47 static void upload_drawing_rect(struct brw_context
*brw
)
49 struct gl_context
*ctx
= &brw
->ctx
;
52 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
53 OUT_BATCH(0); /* xmin, ymin */
54 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
55 ((ctx
->DrawBuffer
->Height
- 1) << 16));
60 const struct brw_tracked_state brw_drawing_rect
= {
63 .brw
= BRW_NEW_CONTEXT
,
66 .emit
= upload_drawing_rect
70 * Upload the binding table pointers, which point each stage's array of surface
73 * The binding table pointers are relative to the surface state base address,
74 * which points at the batchbuffer containing the streamed batch state.
76 static void upload_binding_table_pointers(struct brw_context
*brw
)
79 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 | (6 - 2));
80 OUT_BATCH(brw
->vs
.bind_bo_offset
);
81 OUT_BATCH(0); /* gs */
82 OUT_BATCH(0); /* clip */
83 OUT_BATCH(0); /* sf */
84 OUT_BATCH(brw
->wm
.bind_bo_offset
);
88 const struct brw_tracked_state brw_binding_table_pointers
= {
91 .brw
= (BRW_NEW_BATCH
|
92 BRW_NEW_STATE_BASE_ADDRESS
|
93 BRW_NEW_VS_BINDING_TABLE
|
94 BRW_NEW_GS_BINDING_TABLE
|
95 BRW_NEW_PS_BINDING_TABLE
),
98 .emit
= upload_binding_table_pointers
,
102 * Upload the binding table pointers, which point each stage's array of surface
105 * The binding table pointers are relative to the surface state base address,
106 * which points at the batchbuffer containing the streamed batch state.
108 static void upload_gen6_binding_table_pointers(struct brw_context
*brw
)
111 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
112 GEN6_BINDING_TABLE_MODIFY_VS
|
113 GEN6_BINDING_TABLE_MODIFY_GS
|
114 GEN6_BINDING_TABLE_MODIFY_PS
|
116 OUT_BATCH(brw
->vs
.bind_bo_offset
); /* vs */
117 OUT_BATCH(brw
->gs
.bind_bo_offset
); /* gs */
118 OUT_BATCH(brw
->wm
.bind_bo_offset
); /* wm/ps */
122 const struct brw_tracked_state gen6_binding_table_pointers
= {
125 .brw
= (BRW_NEW_BATCH
|
126 BRW_NEW_STATE_BASE_ADDRESS
|
127 BRW_NEW_VS_BINDING_TABLE
|
128 BRW_NEW_GS_BINDING_TABLE
|
129 BRW_NEW_PS_BINDING_TABLE
),
132 .emit
= upload_gen6_binding_table_pointers
,
136 * Upload pointers to the per-stage state.
138 * The state pointers in this packet are all relative to the general state
139 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
141 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
144 /* Need to flush before changing clip max threads for errata. */
151 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
152 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
153 brw
->vs
.state_offset
);
154 if (brw
->gs
.prog_active
)
155 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
156 brw
->gs
.state_offset
| 1);
159 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
160 brw
->clip
.state_offset
| 1);
161 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
162 brw
->sf
.state_offset
);
163 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
164 brw
->wm
.state_offset
);
165 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
166 brw
->cc
.state_offset
);
169 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
172 static void upload_psp_urb_cbs(struct brw_context
*brw
)
174 upload_pipelined_state_pointers(brw
);
175 brw_upload_urb_fence(brw
);
176 brw_upload_cs_urb_state(brw
);
179 const struct brw_tracked_state brw_psp_urb_cbs
= {
182 .brw
= (BRW_NEW_URB_FENCE
|
184 BRW_NEW_STATE_BASE_ADDRESS
),
185 .cache
= (CACHE_NEW_VS_UNIT
|
188 CACHE_NEW_CLIP_UNIT
|
193 .emit
= upload_psp_urb_cbs
,
197 brw_depthbuffer_format(struct brw_context
*brw
)
199 struct gl_context
*ctx
= &brw
->ctx
;
200 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
201 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
202 struct intel_renderbuffer
*srb
;
205 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
206 !srb
->mt
->stencil_mt
&&
207 (intel_rb_format(srb
) == MESA_FORMAT_S8_Z24
||
208 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_X24S8
)) {
213 return BRW_DEPTHFORMAT_D32_FLOAT
;
215 switch (drb
->mt
->format
) {
216 case MESA_FORMAT_Z16
:
217 return BRW_DEPTHFORMAT_D16_UNORM
;
218 case MESA_FORMAT_Z32_FLOAT
:
219 return BRW_DEPTHFORMAT_D32_FLOAT
;
220 case MESA_FORMAT_X8_Z24
:
222 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
224 /* Use D24_UNORM_S8, not D24_UNORM_X8.
226 * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
227 * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
228 * 3DSTATE_DEPTH_BUFFER.Surface_Format).
230 * However, on Gen5, D24_UNORM_X8 may be used only if separate
231 * stencil is enabled, and we never enable it. From the Ironlake PRM,
232 * same section as above, Bit 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Buffer_Enable:
233 * If this field is disabled, the Surface Format of the depth
234 * buffer cannot be D24_UNORM_X8_UINT.
236 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
238 case MESA_FORMAT_S8_Z24
:
239 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
240 case MESA_FORMAT_Z32_FLOAT_X24S8
:
241 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT
;
243 _mesa_problem(ctx
, "Unexpected depth format %s\n",
244 _mesa_get_format_name(intel_rb_format(drb
)));
245 return BRW_DEPTHFORMAT_D16_UNORM
;
250 * Returns the mask of how many bits of x and y must be handled through the
251 * depthbuffer's draw offset x and y fields.
253 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
254 * between the depth, hiz, and stencil buffers. Because it can be hard to get
255 * all 3 to agree on this value, we want to do as much drawing offset
256 * adjustment as possible by moving the base offset of the 3 buffers, which is
257 * restricted to tile boundaries.
259 * For each buffer, the remainder must be applied through the x/y draw offset.
260 * This returns the worst-case mask of the low bits that have to go into the
261 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
262 * mask, then we're in trouble.
265 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
266 uint32_t depth_level
,
267 uint32_t depth_layer
,
268 struct intel_mipmap_tree
*stencil_mt
,
269 uint32_t *out_tile_mask_x
,
270 uint32_t *out_tile_mask_y
)
272 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
275 intel_region_get_tile_masks(depth_mt
->region
,
276 &tile_mask_x
, &tile_mask_y
, false);
278 if (intel_miptree_slice_has_hiz(depth_mt
, depth_level
, depth_layer
)) {
279 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
280 intel_region_get_tile_masks(depth_mt
->hiz_mt
->region
,
281 &hiz_tile_mask_x
, &hiz_tile_mask_y
, false);
283 /* Each HiZ row represents 2 rows of pixels */
284 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
286 tile_mask_x
|= hiz_tile_mask_x
;
287 tile_mask_y
|= hiz_tile_mask_y
;
292 if (stencil_mt
->stencil_mt
)
293 stencil_mt
= stencil_mt
->stencil_mt
;
295 if (stencil_mt
->format
== MESA_FORMAT_S8
) {
296 /* Separate stencil buffer uses 64x64 tiles. */
300 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
301 intel_region_get_tile_masks(stencil_mt
->region
,
302 &stencil_tile_mask_x
,
303 &stencil_tile_mask_y
, false);
305 tile_mask_x
|= stencil_tile_mask_x
;
306 tile_mask_y
|= stencil_tile_mask_y
;
310 *out_tile_mask_x
= tile_mask_x
;
311 *out_tile_mask_y
= tile_mask_y
;
314 static struct intel_mipmap_tree
*
315 get_stencil_miptree(struct intel_renderbuffer
*irb
)
319 if (irb
->mt
->stencil_mt
)
320 return irb
->mt
->stencil_mt
;
325 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
326 GLbitfield clear_mask
)
328 struct gl_context
*ctx
= &brw
->ctx
;
329 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
330 bool rebase_depth
= false;
331 bool rebase_stencil
= false;
332 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
333 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
334 struct intel_mipmap_tree
*depth_mt
= NULL
;
335 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
336 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
337 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
338 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
339 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
342 depth_mt
= depth_irb
->mt
;
344 /* Initialize brw->depthstencil to 'nop' workaround state.
346 brw
->depthstencil
.tile_x
= 0;
347 brw
->depthstencil
.tile_y
= 0;
348 brw
->depthstencil
.depth_offset
= 0;
349 brw
->depthstencil
.stencil_offset
= 0;
350 brw
->depthstencil
.hiz_offset
= 0;
351 brw
->depthstencil
.depth_mt
= NULL
;
352 brw
->depthstencil
.stencil_mt
= NULL
;
354 brw
->depthstencil
.depth_mt
= depth_mt
;
356 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
358 /* Check if depth buffer is in depth/stencil format. If so, then it's only
359 * safe to invalidate it if we're also clearing stencil, and both depth_irb
360 * and stencil_irb point to the same miptree.
362 * Note: it's not sufficient to check for the case where
363 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
364 * because this fails to catch depth/stencil buffers on hardware that uses
365 * separate stencil. To catch that case, we check whether
366 * depth_mt->stencil_mt is non-NULL.
368 if (depth_irb
&& invalidate_depth
&&
369 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
370 depth_mt
->stencil_mt
)) {
371 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
372 && depth_irb
->mt
== stencil_irb
->mt
;
375 uint32_t tile_mask_x
, tile_mask_y
;
376 brw_get_depthstencil_tile_masks(depth_mt
,
377 depth_mt
? depth_irb
->mt_level
: 0,
378 depth_mt
? depth_irb
->mt_layer
: 0,
380 &tile_mask_x
, &tile_mask_y
);
383 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
384 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
386 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
387 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
388 * Coordinate Offset X/Y":
390 * "The 3 LSBs of both offsets must be zero to ensure correct
393 if (tile_x
& 7 || tile_y
& 7)
396 /* We didn't even have intra-tile offsets before g45. */
397 if (brw
->gen
== 4 && !brw
->is_g4x
) {
398 if (tile_x
|| tile_y
)
403 perf_debug("HW workaround: blitting depth level %d to a temporary "
404 "to fix alignment (depth tile offset %d,%d)\n",
405 depth_irb
->mt_level
, tile_x
, tile_y
);
406 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
407 /* In the case of stencil_irb being the same packed depth/stencil
408 * texture but not the same rb, make it point at our rebased mt, too.
411 stencil_irb
!= depth_irb
&&
412 stencil_irb
->mt
== depth_mt
) {
413 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
414 intel_renderbuffer_set_draw_offset(stencil_irb
);
417 stencil_mt
= get_stencil_miptree(stencil_irb
);
419 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
420 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
424 stencil_mt
= get_stencil_miptree(stencil_irb
);
425 intel_miptree_get_image_offset(stencil_mt
,
426 stencil_irb
->mt_level
,
427 stencil_irb
->mt_layer
,
428 &stencil_draw_x
, &stencil_draw_y
);
429 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
430 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
432 /* If stencil doesn't match depth, then we'll need to rebase stencil
433 * as well. (if we hadn't decided to rebase stencil before, the
434 * post-stencil depth test will also rebase depth to try to match it
437 if (tile_x
!= stencil_tile_x
||
438 tile_y
!= stencil_tile_y
) {
439 rebase_stencil
= true;
444 /* If we have (just) stencil, check it for ignored low bits as well */
446 intel_miptree_get_image_offset(stencil_mt
,
447 stencil_irb
->mt_level
,
448 stencil_irb
->mt_layer
,
449 &stencil_draw_x
, &stencil_draw_y
);
450 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
451 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
453 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
454 rebase_stencil
= true;
456 if (brw
->gen
== 4 && !brw
->is_g4x
) {
457 if (stencil_tile_x
|| stencil_tile_y
)
458 rebase_stencil
= true;
462 if (rebase_stencil
) {
463 perf_debug("HW workaround: blitting stencil level %d to a temporary "
464 "to fix alignment (stencil tile offset %d,%d)\n",
465 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
467 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
468 stencil_mt
= get_stencil_miptree(stencil_irb
);
470 intel_miptree_get_image_offset(stencil_mt
,
471 stencil_irb
->mt_level
,
472 stencil_irb
->mt_layer
,
473 &stencil_draw_x
, &stencil_draw_y
);
474 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
475 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
477 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
478 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
479 intel_renderbuffer_set_draw_offset(depth_irb
);
480 } else if (depth_irb
&& !rebase_depth
) {
481 if (tile_x
!= stencil_tile_x
||
482 tile_y
!= stencil_tile_y
) {
483 perf_debug("HW workaround: blitting depth level %d to a temporary "
484 "to match stencil level %d alignment (depth tile offset "
485 "%d,%d, stencil offset %d,%d)\n",
487 stencil_irb
->mt_level
,
489 stencil_tile_x
, stencil_tile_y
);
491 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
493 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
494 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
496 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
497 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
498 intel_renderbuffer_set_draw_offset(stencil_irb
);
501 WARN_ONCE(stencil_tile_x
!= tile_x
||
502 stencil_tile_y
!= tile_y
,
503 "Rebased stencil tile offset (%d,%d) doesn't match depth "
504 "tile offset (%d,%d).\n",
505 stencil_tile_x
, stencil_tile_y
,
512 tile_x
= stencil_tile_x
;
513 tile_y
= stencil_tile_y
;
516 /* While we just tried to get everything aligned, we may have failed to do
517 * so in the case of rendering to array or 3D textures, where nonzero faces
518 * will still have an offset post-rebase. At least give an informative
521 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
522 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
523 "Truncating offset, bad rendering may occur.\n");
527 /* Now, after rebasing, save off the new dephtstencil state so the hardware
528 * packets can just dereference that without re-calculating tile offsets.
530 brw
->depthstencil
.tile_x
= tile_x
;
531 brw
->depthstencil
.tile_y
= tile_y
;
533 depth_mt
= depth_irb
->mt
;
534 brw
->depthstencil
.depth_mt
= depth_mt
;
535 brw
->depthstencil
.depth_offset
=
536 intel_region_get_aligned_offset(depth_mt
->region
,
537 depth_irb
->draw_x
& ~tile_mask_x
,
538 depth_irb
->draw_y
& ~tile_mask_y
,
540 if (intel_renderbuffer_has_hiz(depth_irb
)) {
541 brw
->depthstencil
.hiz_offset
=
542 intel_region_get_aligned_offset(depth_mt
->region
,
543 depth_irb
->draw_x
& ~tile_mask_x
,
544 (depth_irb
->draw_y
& ~tile_mask_y
) /
550 stencil_mt
= get_stencil_miptree(stencil_irb
);
552 brw
->depthstencil
.stencil_mt
= stencil_mt
;
553 if (stencil_mt
->format
== MESA_FORMAT_S8
) {
554 /* Note: we can't compute the stencil offset using
555 * intel_region_get_aligned_offset(), because stencil_region claims
556 * that the region is untiled even though it's W tiled.
558 brw
->depthstencil
.stencil_offset
=
559 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->region
->pitch
+
560 (stencil_draw_x
& ~tile_mask_x
) * 64;
566 brw_emit_depthbuffer(struct brw_context
*brw
)
568 struct gl_context
*ctx
= &brw
->ctx
;
569 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
571 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
572 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
573 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
574 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
575 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
576 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
577 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
578 bool separate_stencil
= false;
579 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
580 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
581 uint32_t depth_offset
= 0;
582 uint32_t width
= 1, height
= 1;
585 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S8
;
587 /* Gen7 supports only separate stencil */
588 assert(separate_stencil
|| brw
->gen
< 7);
591 /* If there's a packed depth/stencil bound to stencil only, we need to
592 * emit the packed depth/stencil buffer packet.
594 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
595 depth_irb
= stencil_irb
;
596 depth_mt
= stencil_mt
;
599 if (depth_irb
&& depth_mt
) {
600 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
601 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
602 * depthstencil format.
604 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
605 * set to the same value. Gens after 7 implicitly always set
606 * Separate_Stencil_Enable; software cannot disable it.
608 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
609 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
612 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
613 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
615 assert(brw
->gen
< 6 || depth_mt
->region
->tiling
== I915_TILING_Y
);
616 assert(!hiz
|| depth_mt
->region
->tiling
== I915_TILING_Y
);
618 depthbuffer_format
= brw_depthbuffer_format(brw
);
619 depth_surface_type
= BRW_SURFACE_2D
;
620 depth_offset
= brw
->depthstencil
.depth_offset
;
621 width
= depth_irb
->Base
.Base
.Width
;
622 height
= depth_irb
->Base
.Base
.Height
;
623 } else if (separate_stencil
) {
625 * There exists a separate stencil buffer but no depth buffer.
627 * The stencil buffer inherits most of its fields from
628 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
631 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
632 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
633 * [DevGT+]: This field must be set to TRUE.
635 assert(brw
->has_separate_stencil
);
637 depth_surface_type
= BRW_SURFACE_2D
;
638 width
= stencil_irb
->Base
.Base
.Width
;
639 height
= stencil_irb
->Base
.Base
.Height
;
642 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
643 depthbuffer_format
, depth_surface_type
,
644 stencil_mt
, hiz
, separate_stencil
,
645 width
, height
, tile_x
, tile_y
);
649 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
650 struct intel_mipmap_tree
*depth_mt
,
651 uint32_t depth_offset
, uint32_t depthbuffer_format
,
652 uint32_t depth_surface_type
,
653 struct intel_mipmap_tree
*stencil_mt
,
654 bool hiz
, bool separate_stencil
,
655 uint32_t width
, uint32_t height
,
656 uint32_t tile_x
, uint32_t tile_y
)
658 /* Enable the hiz bit if we're doing separate stencil, because it and the
659 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
660 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
661 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
662 * Enable must also be enabled.
664 * [DevGT]: This field must be set to the same value (enabled or
665 * disabled) as Hierarchical Depth Buffer Enable
667 bool enable_hiz_ss
= hiz
|| separate_stencil
;
670 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
671 * non-pipelined state that will need the PIPE_CONTROL workaround.
674 intel_emit_post_sync_nonzero_flush(brw
);
675 intel_emit_depth_stall_flushes(brw
);
681 else if (brw
->is_g4x
|| brw
->gen
== 5)
687 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
688 OUT_BATCH((depth_mt
? depth_mt
->region
->pitch
- 1 : 0) |
689 (depthbuffer_format
<< 18) |
690 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
691 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
692 (BRW_TILEWALK_YMAJOR
<< 26) |
693 ((depth_mt
? depth_mt
->region
->tiling
!= I915_TILING_NONE
: 1)
695 (depth_surface_type
<< 29));
698 OUT_RELOC(depth_mt
->region
->bo
,
699 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
705 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
706 ((height
+ tile_y
- 1) << 19));
709 if (brw
->is_g4x
|| brw
->gen
>= 5)
710 OUT_BATCH(tile_x
| (tile_y
<< 16));
712 assert(tile_x
== 0 && tile_y
== 0);
719 if (hiz
|| separate_stencil
) {
721 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
722 * stencil enable' and 'hiz enable' bits were set. Therefore we must
723 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
724 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
725 * failure to do so causes hangs on gen5 and a stall on gen6.
728 /* Emit hiz buffer. */
730 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_mt
;
732 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
733 OUT_BATCH(hiz_mt
->region
->pitch
- 1);
734 OUT_RELOC(hiz_mt
->region
->bo
,
735 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
736 brw
->depthstencil
.hiz_offset
);
740 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
746 /* Emit stencil buffer. */
747 if (separate_stencil
) {
748 struct intel_region
*region
= stencil_mt
->region
;
751 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
752 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
753 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
754 * The pitch must be set to 2x the value computed based on width, as
755 * the stencil buffer is stored with two rows interleaved.
757 OUT_BATCH(2 * region
->pitch
- 1);
758 OUT_RELOC(region
->bo
,
759 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
760 brw
->depthstencil
.stencil_offset
);
764 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
772 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
773 * params must be emitted.
775 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
776 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
777 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
779 if (brw
->gen
>= 6 || hiz
) {
781 intel_emit_post_sync_nonzero_flush(brw
);
784 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
785 GEN5_DEPTH_CLEAR_VALID
|
787 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
792 const struct brw_tracked_state brw_depthbuffer
= {
794 .mesa
= _NEW_BUFFERS
,
795 .brw
= BRW_NEW_BATCH
,
798 .emit
= brw_emit_depthbuffer
,
803 /***********************************************************************
804 * Polygon stipple packet
807 static void upload_polygon_stipple(struct brw_context
*brw
)
809 struct gl_context
*ctx
= &brw
->ctx
;
813 if (!ctx
->Polygon
.StippleFlag
)
817 intel_emit_post_sync_nonzero_flush(brw
);
820 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
822 /* Polygon stipple is provided in OpenGL order, i.e. bottom
823 * row first. If we're rendering to a window (i.e. the
824 * default frame buffer object, 0), then we need to invert
825 * it to match our pixel layout. But if we're rendering
826 * to a FBO (i.e. any named frame buffer object), we *don't*
827 * need to invert - we already match the layout.
829 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
830 for (i
= 0; i
< 32; i
++)
831 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
834 for (i
= 0; i
< 32; i
++)
835 OUT_BATCH(ctx
->PolygonStipple
[i
]);
840 const struct brw_tracked_state brw_polygon_stipple
= {
842 .mesa
= (_NEW_POLYGONSTIPPLE
|
844 .brw
= BRW_NEW_CONTEXT
,
847 .emit
= upload_polygon_stipple
851 /***********************************************************************
852 * Polygon stipple offset packet
855 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
857 struct gl_context
*ctx
= &brw
->ctx
;
860 if (!ctx
->Polygon
.StippleFlag
)
864 intel_emit_post_sync_nonzero_flush(brw
);
867 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
871 * If we're drawing to a system window we have to invert the Y axis
872 * in order to match the OpenGL pixel coordinate system, and our
873 * offset must be matched to the window position. If we're drawing
874 * to a user-created FBO then our native pixel coordinate system
875 * works just fine, and there's no window system to worry about.
877 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
878 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
884 const struct brw_tracked_state brw_polygon_stipple_offset
= {
886 .mesa
= (_NEW_BUFFERS
|
888 .brw
= BRW_NEW_CONTEXT
,
891 .emit
= upload_polygon_stipple_offset
894 /**********************************************************************
897 static void upload_aa_line_parameters(struct brw_context
*brw
)
899 struct gl_context
*ctx
= &brw
->ctx
;
901 if (!ctx
->Line
.SmoothFlag
|| !brw
->has_aa_line_parameters
)
905 intel_emit_post_sync_nonzero_flush(brw
);
907 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
908 /* use legacy aa line coverage computation */
914 const struct brw_tracked_state brw_aa_line_parameters
= {
917 .brw
= BRW_NEW_CONTEXT
,
920 .emit
= upload_aa_line_parameters
923 /***********************************************************************
924 * Line stipple packet
927 static void upload_line_stipple(struct brw_context
*brw
)
929 struct gl_context
*ctx
= &brw
->ctx
;
933 if (!ctx
->Line
.StippleFlag
)
937 intel_emit_post_sync_nonzero_flush(brw
);
940 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
941 OUT_BATCH(ctx
->Line
.StipplePattern
);
945 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
946 tmpi
= tmp
* (1<<16);
947 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
951 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
952 tmpi
= tmp
* (1<<13);
953 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
959 const struct brw_tracked_state brw_line_stipple
= {
962 .brw
= BRW_NEW_CONTEXT
,
965 .emit
= upload_line_stipple
969 /***********************************************************************
970 * Misc invariant state packets
974 brw_upload_invariant_state(struct brw_context
*brw
)
976 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
978 intel_emit_post_sync_nonzero_flush(brw
);
980 /* Select the 3D pipeline (as opposed to media) */
982 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16 | 0);
986 /* Disable depth offset clamping. */
988 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
994 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
999 OUT_BATCH(brw
->CMD_VF_STATISTICS
<< 16 |
1000 (unlikely(INTEL_DEBUG
& DEBUG_STATS
) ? 1 : 0));
1004 const struct brw_tracked_state brw_invariant_state
= {
1007 .brw
= BRW_NEW_CONTEXT
,
1010 .emit
= brw_upload_invariant_state
1014 * Define the base addresses which some state is referenced from.
1016 * This allows us to avoid having to emit relocations for the objects,
1017 * and is actually required for binding table pointers on gen6.
1019 * Surface state base address covers binding table pointers and
1020 * surface state objects, but not the surfaces that the surface state
1023 static void upload_state_base_address( struct brw_context
*brw
)
1025 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
1026 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
1027 * programmed prior to STATE_BASE_ADDRESS.
1029 * However, given that the instruction SBA (general state base
1030 * address) on this chipset is always set to 0 across X and GL,
1031 * maybe this isn't required for us in particular.
1034 if (brw
->gen
>= 6) {
1036 intel_emit_post_sync_nonzero_flush(brw
);
1039 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
1040 /* General state base address: stateless DP read/write requests */
1042 /* Surface state base address:
1043 * BINDING_TABLE_STATE
1046 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
1047 /* Dynamic state base address:
1049 * SAMPLER_BORDER_COLOR_STATE
1050 * CLIP, SF, WM/CC viewport state
1052 * DEPTH_STENCIL_STATE
1054 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
1055 * Disable is clear, which we rely on)
1057 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
1058 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
1060 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
1061 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1062 1); /* Instruction base address: shader kernels (incl. SIP) */
1064 OUT_BATCH(1); /* General state upper bound */
1065 /* Dynamic state upper bound. Although the documentation says that
1066 * programming it to zero will cause it to be ignored, that is a lie.
1067 * If this isn't programmed to a real bound, the sampler border color
1068 * pointer is rejected, causing border color to mysteriously fail.
1070 OUT_BATCH(0xfffff001);
1071 OUT_BATCH(1); /* Indirect object upper bound */
1072 OUT_BATCH(1); /* Instruction access upper bound */
1074 } else if (brw
->gen
== 5) {
1076 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
1077 OUT_BATCH(1); /* General state base address */
1078 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1079 1); /* Surface state base address */
1080 OUT_BATCH(1); /* Indirect object base address */
1081 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1082 1); /* Instruction base address */
1083 OUT_BATCH(0xfffff001); /* General state upper bound */
1084 OUT_BATCH(1); /* Indirect object upper bound */
1085 OUT_BATCH(1); /* Instruction access upper bound */
1089 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1090 OUT_BATCH(1); /* General state base address */
1091 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1092 1); /* Surface state base address */
1093 OUT_BATCH(1); /* Indirect object base address */
1094 OUT_BATCH(1); /* General state upper bound */
1095 OUT_BATCH(1); /* Indirect object upper bound */
1099 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1100 * STATE_BASE_ADDRESS updates require a reissue of:
1102 * 3DSTATE_PIPELINE_POINTERS
1103 * 3DSTATE_BINDING_TABLE_POINTERS
1104 * MEDIA_STATE_POINTERS
1106 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1107 * 1 part 1 says that the folowing packets must be reissued:
1109 * 3DSTATE_CC_POINTERS
1110 * 3DSTATE_BINDING_TABLE_POINTERS
1111 * 3DSTATE_SAMPLER_STATE_POINTERS
1112 * 3DSTATE_VIEWPORT_STATE_POINTERS
1113 * MEDIA_STATE_POINTERS
1115 * Those are always reissued following SBA updates anyway (new
1116 * batch time), except in the case of the program cache BO
1117 * changing. Having a separate state flag makes the sequence more
1121 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
1124 const struct brw_tracked_state brw_state_base_address
= {
1127 .brw
= (BRW_NEW_BATCH
|
1128 BRW_NEW_PROGRAM_CACHE
),
1131 .emit
= upload_state_base_address