2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_regions.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
39 #include "brw_defines.h"
45 /***********************************************************************
49 static void upload_blend_constant_color(struct brw_context
*brw
)
51 struct brw_blend_constant_color bcc
;
53 memset(&bcc
, 0, sizeof(bcc
));
54 bcc
.header
.opcode
= CMD_BLEND_CONSTANT_COLOR
;
55 bcc
.header
.length
= sizeof(bcc
)/4-2;
56 bcc
.blend_constant_color
[0] = brw
->attribs
.Color
->BlendColor
[0];
57 bcc
.blend_constant_color
[1] = brw
->attribs
.Color
->BlendColor
[1];
58 bcc
.blend_constant_color
[2] = brw
->attribs
.Color
->BlendColor
[2];
59 bcc
.blend_constant_color
[3] = brw
->attribs
.Color
->BlendColor
[3];
61 BRW_CACHED_BATCH_STRUCT(brw
, &bcc
);
65 const struct brw_tracked_state brw_blend_constant_color
= {
71 .emit
= upload_blend_constant_color
75 * Upload the binding table pointers, which point each stage's array of surface
78 * The binding table pointers are relative to the surface state base address,
81 static void upload_binding_table_pointers(struct brw_context
*brw
)
83 struct intel_context
*intel
= &brw
->intel
;
85 BEGIN_BATCH(6, IGNORE_CLIPRECTS
);
86 OUT_BATCH(CMD_BINDING_TABLE_PTRS
<< 16 | (6 - 2));
87 OUT_BATCH(0); /* vs */
88 OUT_BATCH(0); /* gs */
89 OUT_BATCH(0); /* clip */
90 OUT_BATCH(0); /* sf */
91 OUT_RELOC(brw
->wm
.bind_bo
,
92 I915_GEM_DOMAIN_SAMPLER
, 0,
97 const struct brw_tracked_state brw_binding_table_pointers
= {
100 .brw
= BRW_NEW_BATCH
,
101 .cache
= CACHE_NEW_SURF_BIND
,
103 .emit
= upload_binding_table_pointers
,
108 * Upload pointers to the per-stage state.
110 * The state pointers in this packet are all relative to the general state
111 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
113 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
115 struct intel_context
*intel
= &brw
->intel
;
117 BEGIN_BATCH(7, IGNORE_CLIPRECTS
);
118 OUT_BATCH(CMD_PIPELINED_STATE_POINTERS
<< 16 | (7 - 2));
119 OUT_RELOC(brw
->vs
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
120 if (brw
->gs
.prog_active
)
121 OUT_RELOC(brw
->gs
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 1);
124 if (!brw
->metaops
.active
)
125 OUT_RELOC(brw
->clip
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 1);
128 OUT_RELOC(brw
->sf
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
129 OUT_RELOC(brw
->wm
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
130 OUT_RELOC(brw
->cc
.state_bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0, 0);
133 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
137 /* Combined into brw_psp_urb_cbs */
138 const struct brw_tracked_state brw_pipelined_state_pointers
= {
141 .brw
= BRW_NEW_METAOPS
| BRW_NEW_BATCH
,
142 .cache
= (CACHE_NEW_VS_UNIT
|
145 CACHE_NEW_CLIP_UNIT
|
150 .emit
= upload_pipelined_state_pointers
154 static void upload_psp_urb_cbs(struct brw_context
*brw
)
156 upload_pipelined_state_pointers(brw
);
157 brw_upload_urb_fence(brw
);
158 brw_upload_constant_buffer_state(brw
);
162 const struct brw_tracked_state brw_psp_urb_cbs
= {
165 .brw
= BRW_NEW_URB_FENCE
| BRW_NEW_METAOPS
| BRW_NEW_BATCH
,
166 .cache
= (CACHE_NEW_VS_UNIT
|
169 CACHE_NEW_CLIP_UNIT
|
174 .emit
= upload_psp_urb_cbs
,
178 * Upload the depthbuffer offset and format.
180 * We have to do this per state validation as we need to emit the relocation
181 * in the batch buffer.
184 static int prepare_depthbuffer(struct brw_context
*brw
)
186 struct intel_region
*region
= brw
->state
.depth_region
;
188 if (!region
|| !region
->buffer
)
190 return dri_bufmgr_check_aperture_space(region
->buffer
);
193 static void emit_depthbuffer(struct brw_context
*brw
)
195 struct intel_context
*intel
= &brw
->intel
;
196 struct intel_region
*region
= brw
->state
.depth_region
;
197 unsigned int len
= (BRW_IS_GM45(brw
) || BRW_IS_G4X(brw
)) ? sizeof(struct brw_depthbuffer_gm45_g4x
) / 4 : sizeof(struct brw_depthbuffer
) / 4;
199 if (region
== NULL
) {
200 BEGIN_BATCH(len
, IGNORE_CLIPRECTS
);
201 OUT_BATCH(CMD_DEPTH_BUFFER
<< 16 | (len
- 2));
202 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
203 (BRW_SURFACE_NULL
<< 29));
208 if (BRW_IS_GM45(brw
) || BRW_IS_G4X(brw
))
215 switch (region
->cpp
) {
217 format
= BRW_DEPTHFORMAT_D16_UNORM
;
220 if (intel
->depth_buffer_is_float
)
221 format
= BRW_DEPTHFORMAT_D32_FLOAT
;
223 format
= BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
230 BEGIN_BATCH(len
, IGNORE_CLIPRECTS
);
231 OUT_BATCH(CMD_DEPTH_BUFFER
<< 16 | (len
- 2));
232 OUT_BATCH(((region
->pitch
* region
->cpp
) - 1) |
234 (BRW_TILEWALK_YMAJOR
<< 26) |
235 ((region
->tiling
!= I915_TILING_NONE
) << 27) |
236 (BRW_SURFACE_2D
<< 29));
237 OUT_RELOC(region
->buffer
,
238 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
240 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1) |
241 ((region
->pitch
- 1) << 6) |
242 ((region
->height
- 1) << 19));
245 if (BRW_IS_GM45(brw
) || BRW_IS_G4X(brw
))
252 const struct brw_tracked_state brw_depthbuffer
= {
255 .brw
= BRW_NEW_DEPTH_BUFFER
| BRW_NEW_BATCH
,
258 .prepare
= prepare_depthbuffer
,
259 .emit
= emit_depthbuffer
,
264 /***********************************************************************
265 * Polygon stipple packet
268 static void upload_polygon_stipple(struct brw_context
*brw
)
270 struct brw_polygon_stipple bps
;
273 memset(&bps
, 0, sizeof(bps
));
274 bps
.header
.opcode
= CMD_POLY_STIPPLE_PATTERN
;
275 bps
.header
.length
= sizeof(bps
)/4-2;
277 for (i
= 0; i
< 32; i
++)
278 bps
.stipple
[i
] = brw
->attribs
.PolygonStipple
[31 - i
]; /* invert */
280 BRW_CACHED_BATCH_STRUCT(brw
, &bps
);
283 const struct brw_tracked_state brw_polygon_stipple
= {
285 .mesa
= _NEW_POLYGONSTIPPLE
,
289 .emit
= upload_polygon_stipple
293 /***********************************************************************
294 * Polygon stipple offset packet
297 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
299 __DRIdrawablePrivate
*dPriv
= brw
->intel
.driDrawable
;
300 struct brw_polygon_stipple_offset bpso
;
302 memset(&bpso
, 0, sizeof(bpso
));
303 bpso
.header
.opcode
= CMD_POLY_STIPPLE_OFFSET
;
304 bpso
.header
.length
= sizeof(bpso
)/4-2;
306 bpso
.bits0
.x_offset
= (32 - (dPriv
->x
& 31)) & 31;
307 bpso
.bits0
.y_offset
= (32 - ((dPriv
->y
+ dPriv
->h
) & 31)) & 31;
309 BRW_CACHED_BATCH_STRUCT(brw
, &bpso
);
312 #define _NEW_WINDOW_POS 0x40000000
314 const struct brw_tracked_state brw_polygon_stipple_offset
= {
316 .mesa
= _NEW_WINDOW_POS
,
320 .emit
= upload_polygon_stipple_offset
323 /**********************************************************************
326 static void upload_aa_line_parameters(struct brw_context
*brw
)
328 struct brw_aa_line_parameters balp
;
330 if (!(BRW_IS_GM45(brw
) || BRW_IS_G4X(brw
)))
333 /* use legacy aa line coverage computation */
334 memset(&balp
, 0, sizeof(balp
));
335 balp
.header
.opcode
= CMD_AA_LINE_PARAMETERS
;
336 balp
.header
.length
= sizeof(balp
) / 4 - 2;
338 BRW_CACHED_BATCH_STRUCT(brw
, &balp
);
341 const struct brw_tracked_state brw_aa_line_parameters
= {
344 .brw
= BRW_NEW_CONTEXT
,
347 .emit
= upload_aa_line_parameters
350 /***********************************************************************
351 * Line stipple packet
354 static void upload_line_stipple(struct brw_context
*brw
)
356 struct brw_line_stipple bls
;
360 memset(&bls
, 0, sizeof(bls
));
361 bls
.header
.opcode
= CMD_LINE_STIPPLE_PATTERN
;
362 bls
.header
.length
= sizeof(bls
)/4 - 2;
364 bls
.bits0
.pattern
= brw
->attribs
.Line
->StipplePattern
;
365 bls
.bits1
.repeat_count
= brw
->attribs
.Line
->StippleFactor
;
367 tmp
= 1.0 / (GLfloat
) brw
->attribs
.Line
->StippleFactor
;
368 tmpi
= tmp
* (1<<13);
371 bls
.bits1
.inverse_repeat_count
= tmpi
;
373 BRW_CACHED_BATCH_STRUCT(brw
, &bls
);
376 const struct brw_tracked_state brw_line_stipple
= {
382 .emit
= upload_line_stipple
386 /***********************************************************************
387 * Misc invarient state packets
390 static void upload_invarient_state( struct brw_context
*brw
)
393 /* 0x61040000 Pipeline Select */
394 /* PipelineSelect : 0 */
395 struct brw_pipeline_select ps
;
397 memset(&ps
, 0, sizeof(ps
));
398 ps
.header
.opcode
= CMD_PIPELINE_SELECT(brw
);
399 ps
.header
.pipeline_select
= 0;
400 BRW_BATCH_STRUCT(brw
, &ps
);
404 struct brw_global_depth_offset_clamp gdo
;
405 memset(&gdo
, 0, sizeof(gdo
));
407 /* Disable depth offset clamping.
409 gdo
.header
.opcode
= CMD_GLOBAL_DEPTH_OFFSET_CLAMP
;
410 gdo
.header
.length
= sizeof(gdo
)/4 - 2;
411 gdo
.depth_offset_clamp
= 0.0;
413 BRW_BATCH_STRUCT(brw
, &gdo
);
417 /* 0x61020000 State Instruction Pointer */
419 struct brw_system_instruction_pointer sip
;
420 memset(&sip
, 0, sizeof(sip
));
422 sip
.header
.opcode
= CMD_STATE_INSN_POINTER
;
423 sip
.header
.length
= 0;
425 sip
.bits0
.system_instruction_pointer
= 0;
426 BRW_BATCH_STRUCT(brw
, &sip
);
431 struct brw_vf_statistics vfs
;
432 memset(&vfs
, 0, sizeof(vfs
));
434 vfs
.opcode
= CMD_VF_STATISTICS(brw
);
435 if (INTEL_DEBUG
& DEBUG_STATS
)
436 vfs
.statistics_enable
= 1;
438 BRW_BATCH_STRUCT(brw
, &vfs
);
442 const struct brw_tracked_state brw_invarient_state
= {
445 .brw
= BRW_NEW_CONTEXT
,
448 .emit
= upload_invarient_state
452 * Define the base addresses which some state is referenced from.
454 * This allows us to avoid having to emit relocations in many places for
455 * cached state, and instead emit pointers inside of large, mostly-static
456 * state pools. This comes at the expense of memory, and more expensive cache
459 static void upload_state_base_address( struct brw_context
*brw
)
461 struct intel_context
*intel
= &brw
->intel
;
463 /* Output the structure (brw_state_base_address) directly to the
464 * batchbuffer, so we can emit relocations inline.
466 BEGIN_BATCH(6, IGNORE_CLIPRECTS
);
467 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
468 OUT_BATCH(1); /* General state base address */
469 OUT_BATCH(1); /* Surface state base address */
470 OUT_BATCH(1); /* Indirect object base address */
471 OUT_BATCH(1); /* General state upper bound */
472 OUT_BATCH(1); /* Indirect object upper bound */
476 const struct brw_tracked_state brw_state_base_address
= {
479 .brw
= BRW_NEW_CONTEXT
,
482 .emit
= upload_state_base_address