2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
42 #include "main/fbobject.h"
43 #include "main/glformats.h"
45 /* Constant single cliprect for framebuffer object or DRI2 drawing */
46 static void upload_drawing_rect(struct brw_context
*brw
)
48 struct gl_context
*ctx
= &brw
->ctx
;
50 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined. */
52 intel_emit_post_sync_nonzero_flush(brw
);
55 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
56 OUT_BATCH(0); /* xmin, ymin */
57 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
58 ((ctx
->DrawBuffer
->Height
- 1) << 16));
63 const struct brw_tracked_state brw_drawing_rect
= {
66 .brw
= BRW_NEW_CONTEXT
,
69 .emit
= upload_drawing_rect
73 * Upload pointers to the per-stage state.
75 * The state pointers in this packet are all relative to the general state
76 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
78 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
81 /* Need to flush before changing clip max threads for errata. */
88 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
89 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
90 brw
->vs
.base
.state_offset
);
91 if (brw
->ff_gs
.prog_active
)
92 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
93 brw
->ff_gs
.state_offset
| 1);
96 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
97 brw
->clip
.state_offset
| 1);
98 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
99 brw
->sf
.state_offset
);
100 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
101 brw
->wm
.base
.state_offset
);
102 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
103 brw
->cc
.state_offset
);
106 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
109 static void upload_psp_urb_cbs(struct brw_context
*brw
)
111 upload_pipelined_state_pointers(brw
);
112 brw_upload_urb_fence(brw
);
113 brw_upload_cs_urb_state(brw
);
116 const struct brw_tracked_state brw_psp_urb_cbs
= {
119 .brw
= BRW_NEW_BATCH
|
120 BRW_NEW_FF_GS_PROG_DATA
|
121 BRW_NEW_GEN4_UNIT_STATE
|
122 BRW_NEW_STATE_BASE_ADDRESS
|
125 .emit
= upload_psp_urb_cbs
,
129 brw_depthbuffer_format(struct brw_context
*brw
)
131 struct gl_context
*ctx
= &brw
->ctx
;
132 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
133 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
134 struct intel_renderbuffer
*srb
;
137 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
138 !srb
->mt
->stencil_mt
&&
139 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
140 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
145 return BRW_DEPTHFORMAT_D32_FLOAT
;
147 return brw_depth_format(brw
, drb
->mt
->format
);
151 * Returns the mask of how many bits of x and y must be handled through the
152 * depthbuffer's draw offset x and y fields.
154 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
155 * between the depth, hiz, and stencil buffers. Because it can be hard to get
156 * all 3 to agree on this value, we want to do as much drawing offset
157 * adjustment as possible by moving the base offset of the 3 buffers, which is
158 * restricted to tile boundaries.
160 * For each buffer, the remainder must be applied through the x/y draw offset.
161 * This returns the worst-case mask of the low bits that have to go into the
162 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
163 * mask, then we're in trouble.
166 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
167 uint32_t depth_level
,
168 uint32_t depth_layer
,
169 struct intel_mipmap_tree
*stencil_mt
,
170 uint32_t *out_tile_mask_x
,
171 uint32_t *out_tile_mask_y
)
173 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
176 intel_miptree_get_tile_masks(depth_mt
, &tile_mask_x
, &tile_mask_y
, false);
178 if (intel_miptree_level_has_hiz(depth_mt
, depth_level
)) {
179 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
180 intel_miptree_get_tile_masks(depth_mt
->hiz_mt
,
181 &hiz_tile_mask_x
, &hiz_tile_mask_y
,
184 /* Each HiZ row represents 2 rows of pixels */
185 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
187 tile_mask_x
|= hiz_tile_mask_x
;
188 tile_mask_y
|= hiz_tile_mask_y
;
193 if (stencil_mt
->stencil_mt
)
194 stencil_mt
= stencil_mt
->stencil_mt
;
196 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
197 /* Separate stencil buffer uses 64x64 tiles. */
201 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
202 intel_miptree_get_tile_masks(stencil_mt
,
203 &stencil_tile_mask_x
,
204 &stencil_tile_mask_y
, false);
206 tile_mask_x
|= stencil_tile_mask_x
;
207 tile_mask_y
|= stencil_tile_mask_y
;
211 *out_tile_mask_x
= tile_mask_x
;
212 *out_tile_mask_y
= tile_mask_y
;
215 static struct intel_mipmap_tree
*
216 get_stencil_miptree(struct intel_renderbuffer
*irb
)
220 if (irb
->mt
->stencil_mt
)
221 return irb
->mt
->stencil_mt
;
226 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
227 GLbitfield clear_mask
)
229 struct gl_context
*ctx
= &brw
->ctx
;
230 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
231 bool rebase_depth
= false;
232 bool rebase_stencil
= false;
233 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
234 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
235 struct intel_mipmap_tree
*depth_mt
= NULL
;
236 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
237 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
238 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
239 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
240 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
243 depth_mt
= depth_irb
->mt
;
245 /* Initialize brw->depthstencil to 'nop' workaround state.
247 brw
->depthstencil
.tile_x
= 0;
248 brw
->depthstencil
.tile_y
= 0;
249 brw
->depthstencil
.depth_offset
= 0;
250 brw
->depthstencil
.stencil_offset
= 0;
251 brw
->depthstencil
.hiz_offset
= 0;
252 brw
->depthstencil
.depth_mt
= NULL
;
253 brw
->depthstencil
.stencil_mt
= NULL
;
255 brw
->depthstencil
.depth_mt
= depth_mt
;
257 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
259 /* Gen6+ doesn't require the workarounds, since we always program the
260 * surface state at the start of the whole surface.
265 /* Check if depth buffer is in depth/stencil format. If so, then it's only
266 * safe to invalidate it if we're also clearing stencil, and both depth_irb
267 * and stencil_irb point to the same miptree.
269 * Note: it's not sufficient to check for the case where
270 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
271 * because this fails to catch depth/stencil buffers on hardware that uses
272 * separate stencil. To catch that case, we check whether
273 * depth_mt->stencil_mt is non-NULL.
275 if (depth_irb
&& invalidate_depth
&&
276 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
277 depth_mt
->stencil_mt
)) {
278 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
279 && depth_irb
->mt
== stencil_irb
->mt
;
282 uint32_t tile_mask_x
, tile_mask_y
;
283 brw_get_depthstencil_tile_masks(depth_mt
,
284 depth_mt
? depth_irb
->mt_level
: 0,
285 depth_mt
? depth_irb
->mt_layer
: 0,
287 &tile_mask_x
, &tile_mask_y
);
290 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
291 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
293 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
294 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
295 * Coordinate Offset X/Y":
297 * "The 3 LSBs of both offsets must be zero to ensure correct
300 if (tile_x
& 7 || tile_y
& 7)
303 /* We didn't even have intra-tile offsets before g45. */
304 if (!brw
->has_surface_tile_offset
) {
305 if (tile_x
|| tile_y
)
310 perf_debug("HW workaround: blitting depth level %d to a temporary "
311 "to fix alignment (depth tile offset %d,%d)\n",
312 depth_irb
->mt_level
, tile_x
, tile_y
);
313 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
314 /* In the case of stencil_irb being the same packed depth/stencil
315 * texture but not the same rb, make it point at our rebased mt, too.
318 stencil_irb
!= depth_irb
&&
319 stencil_irb
->mt
== depth_mt
) {
320 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
321 intel_renderbuffer_set_draw_offset(stencil_irb
);
324 stencil_mt
= get_stencil_miptree(stencil_irb
);
326 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
327 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
331 stencil_mt
= get_stencil_miptree(stencil_irb
);
332 intel_miptree_get_image_offset(stencil_mt
,
333 stencil_irb
->mt_level
,
334 stencil_irb
->mt_layer
,
335 &stencil_draw_x
, &stencil_draw_y
);
336 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
337 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
339 /* If stencil doesn't match depth, then we'll need to rebase stencil
340 * as well. (if we hadn't decided to rebase stencil before, the
341 * post-stencil depth test will also rebase depth to try to match it
344 if (tile_x
!= stencil_tile_x
||
345 tile_y
!= stencil_tile_y
) {
346 rebase_stencil
= true;
351 /* If we have (just) stencil, check it for ignored low bits as well */
353 intel_miptree_get_image_offset(stencil_mt
,
354 stencil_irb
->mt_level
,
355 stencil_irb
->mt_layer
,
356 &stencil_draw_x
, &stencil_draw_y
);
357 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
358 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
360 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
361 rebase_stencil
= true;
363 if (!brw
->has_surface_tile_offset
) {
364 if (stencil_tile_x
|| stencil_tile_y
)
365 rebase_stencil
= true;
369 if (rebase_stencil
) {
370 perf_debug("HW workaround: blitting stencil level %d to a temporary "
371 "to fix alignment (stencil tile offset %d,%d)\n",
372 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
374 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
375 stencil_mt
= get_stencil_miptree(stencil_irb
);
377 intel_miptree_get_image_offset(stencil_mt
,
378 stencil_irb
->mt_level
,
379 stencil_irb
->mt_layer
,
380 &stencil_draw_x
, &stencil_draw_y
);
381 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
382 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
384 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
385 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
386 intel_renderbuffer_set_draw_offset(depth_irb
);
387 } else if (depth_irb
&& !rebase_depth
) {
388 if (tile_x
!= stencil_tile_x
||
389 tile_y
!= stencil_tile_y
) {
390 perf_debug("HW workaround: blitting depth level %d to a temporary "
391 "to match stencil level %d alignment (depth tile offset "
392 "%d,%d, stencil offset %d,%d)\n",
394 stencil_irb
->mt_level
,
396 stencil_tile_x
, stencil_tile_y
);
398 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
400 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
401 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
403 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
404 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
405 intel_renderbuffer_set_draw_offset(stencil_irb
);
408 WARN_ONCE(stencil_tile_x
!= tile_x
||
409 stencil_tile_y
!= tile_y
,
410 "Rebased stencil tile offset (%d,%d) doesn't match depth "
411 "tile offset (%d,%d).\n",
412 stencil_tile_x
, stencil_tile_y
,
419 tile_x
= stencil_tile_x
;
420 tile_y
= stencil_tile_y
;
423 /* While we just tried to get everything aligned, we may have failed to do
424 * so in the case of rendering to array or 3D textures, where nonzero faces
425 * will still have an offset post-rebase. At least give an informative
428 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
429 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
430 "Truncating offset, bad rendering may occur.\n");
434 /* Now, after rebasing, save off the new dephtstencil state so the hardware
435 * packets can just dereference that without re-calculating tile offsets.
437 brw
->depthstencil
.tile_x
= tile_x
;
438 brw
->depthstencil
.tile_y
= tile_y
;
440 depth_mt
= depth_irb
->mt
;
441 brw
->depthstencil
.depth_mt
= depth_mt
;
442 brw
->depthstencil
.depth_offset
=
443 intel_miptree_get_aligned_offset(depth_mt
,
444 depth_irb
->draw_x
& ~tile_mask_x
,
445 depth_irb
->draw_y
& ~tile_mask_y
,
447 if (intel_renderbuffer_has_hiz(depth_irb
)) {
448 brw
->depthstencil
.hiz_offset
=
449 intel_miptree_get_aligned_offset(depth_mt
,
450 depth_irb
->draw_x
& ~tile_mask_x
,
451 (depth_irb
->draw_y
& ~tile_mask_y
) / 2,
456 stencil_mt
= get_stencil_miptree(stencil_irb
);
458 brw
->depthstencil
.stencil_mt
= stencil_mt
;
459 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
460 /* Note: we can't compute the stencil offset using
461 * intel_region_get_aligned_offset(), because stencil_region claims
462 * that the region is untiled even though it's W tiled.
464 brw
->depthstencil
.stencil_offset
=
465 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
466 (stencil_draw_x
& ~tile_mask_x
) * 64;
472 brw_emit_depthbuffer(struct brw_context
*brw
)
474 struct gl_context
*ctx
= &brw
->ctx
;
475 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
477 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
478 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
479 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
480 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
481 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
482 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
483 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
484 bool separate_stencil
= false;
485 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
486 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
487 uint32_t depth_offset
= 0;
488 uint32_t width
= 1, height
= 1;
491 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
493 /* Gen7 supports only separate stencil */
494 assert(separate_stencil
|| brw
->gen
< 7);
497 /* If there's a packed depth/stencil bound to stencil only, we need to
498 * emit the packed depth/stencil buffer packet.
500 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
501 depth_irb
= stencil_irb
;
502 depth_mt
= stencil_mt
;
505 if (depth_irb
&& depth_mt
) {
506 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
507 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
508 * depthstencil format.
510 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
511 * set to the same value. Gens after 7 implicitly always set
512 * Separate_Stencil_Enable; software cannot disable it.
514 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
515 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
518 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
519 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
521 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
522 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
524 depthbuffer_format
= brw_depthbuffer_format(brw
);
525 depth_surface_type
= BRW_SURFACE_2D
;
526 depth_offset
= brw
->depthstencil
.depth_offset
;
527 width
= depth_irb
->Base
.Base
.Width
;
528 height
= depth_irb
->Base
.Base
.Height
;
529 } else if (separate_stencil
) {
531 * There exists a separate stencil buffer but no depth buffer.
533 * The stencil buffer inherits most of its fields from
534 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
537 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
538 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
539 * [DevGT+]: This field must be set to TRUE.
541 assert(brw
->has_separate_stencil
);
543 depth_surface_type
= BRW_SURFACE_2D
;
544 width
= stencil_irb
->Base
.Base
.Width
;
545 height
= stencil_irb
->Base
.Base
.Height
;
549 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
551 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
553 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
554 depthbuffer_format
, depth_surface_type
,
555 stencil_mt
, hiz
, separate_stencil
,
556 width
, height
, tile_x
, tile_y
);
560 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
561 struct intel_mipmap_tree
*depth_mt
,
562 uint32_t depth_offset
, uint32_t depthbuffer_format
,
563 uint32_t depth_surface_type
,
564 struct intel_mipmap_tree
*stencil_mt
,
565 bool hiz
, bool separate_stencil
,
566 uint32_t width
, uint32_t height
,
567 uint32_t tile_x
, uint32_t tile_y
)
569 /* Enable the hiz bit if we're doing separate stencil, because it and the
570 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
571 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
572 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
573 * Enable must also be enabled.
575 * [DevGT]: This field must be set to the same value (enabled or
576 * disabled) as Hierarchical Depth Buffer Enable
578 bool enable_hiz_ss
= hiz
|| separate_stencil
;
581 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
582 * non-pipelined state that will need the PIPE_CONTROL workaround.
585 intel_emit_post_sync_nonzero_flush(brw
);
586 intel_emit_depth_stall_flushes(brw
);
592 else if (brw
->is_g4x
|| brw
->gen
== 5)
598 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
599 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
600 (depthbuffer_format
<< 18) |
601 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
602 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
603 (BRW_TILEWALK_YMAJOR
<< 26) |
604 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
606 (depth_surface_type
<< 29));
609 OUT_RELOC(depth_mt
->bo
,
610 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
616 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
617 ((height
+ tile_y
- 1) << 19));
620 if (brw
->is_g4x
|| brw
->gen
>= 5)
621 OUT_BATCH(tile_x
| (tile_y
<< 16));
623 assert(tile_x
== 0 && tile_y
== 0);
630 if (hiz
|| separate_stencil
) {
632 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
633 * stencil enable' and 'hiz enable' bits were set. Therefore we must
634 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
635 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
636 * failure to do so causes hangs on gen5 and a stall on gen6.
639 /* Emit hiz buffer. */
641 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_mt
;
643 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
644 OUT_BATCH(hiz_mt
->pitch
- 1);
645 OUT_RELOC(hiz_mt
->bo
,
646 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
647 brw
->depthstencil
.hiz_offset
);
651 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
657 /* Emit stencil buffer. */
658 if (separate_stencil
) {
660 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
661 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
662 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
663 * The pitch must be set to 2x the value computed based on width, as
664 * the stencil buffer is stored with two rows interleaved.
666 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
667 OUT_RELOC(stencil_mt
->bo
,
668 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
669 brw
->depthstencil
.stencil_offset
);
673 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
681 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
682 * params must be emitted.
684 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
685 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
686 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
688 if (brw
->gen
>= 6 || hiz
) {
690 intel_emit_post_sync_nonzero_flush(brw
);
693 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
694 GEN5_DEPTH_CLEAR_VALID
|
696 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
701 const struct brw_tracked_state brw_depthbuffer
= {
703 .mesa
= _NEW_BUFFERS
,
704 .brw
= BRW_NEW_BATCH
,
707 .emit
= brw_emit_depthbuffer
,
712 /***********************************************************************
713 * Polygon stipple packet
716 static void upload_polygon_stipple(struct brw_context
*brw
)
718 struct gl_context
*ctx
= &brw
->ctx
;
722 if (!ctx
->Polygon
.StippleFlag
)
726 intel_emit_post_sync_nonzero_flush(brw
);
729 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
731 /* Polygon stipple is provided in OpenGL order, i.e. bottom
732 * row first. If we're rendering to a window (i.e. the
733 * default frame buffer object, 0), then we need to invert
734 * it to match our pixel layout. But if we're rendering
735 * to a FBO (i.e. any named frame buffer object), we *don't*
736 * need to invert - we already match the layout.
738 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
739 for (i
= 0; i
< 32; i
++)
740 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
743 for (i
= 0; i
< 32; i
++)
744 OUT_BATCH(ctx
->PolygonStipple
[i
]);
749 const struct brw_tracked_state brw_polygon_stipple
= {
751 .mesa
= _NEW_POLYGON
|
753 .brw
= BRW_NEW_CONTEXT
,
756 .emit
= upload_polygon_stipple
760 /***********************************************************************
761 * Polygon stipple offset packet
764 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
766 struct gl_context
*ctx
= &brw
->ctx
;
769 if (!ctx
->Polygon
.StippleFlag
)
773 intel_emit_post_sync_nonzero_flush(brw
);
776 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
780 * If we're drawing to a system window we have to invert the Y axis
781 * in order to match the OpenGL pixel coordinate system, and our
782 * offset must be matched to the window position. If we're drawing
783 * to a user-created FBO then our native pixel coordinate system
784 * works just fine, and there's no window system to worry about.
786 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
787 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
793 const struct brw_tracked_state brw_polygon_stipple_offset
= {
795 .mesa
= _NEW_BUFFERS
|
797 .brw
= BRW_NEW_CONTEXT
,
800 .emit
= upload_polygon_stipple_offset
803 /**********************************************************************
806 static void upload_aa_line_parameters(struct brw_context
*brw
)
808 struct gl_context
*ctx
= &brw
->ctx
;
810 if (!ctx
->Line
.SmoothFlag
)
813 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
814 if (brw
->gen
== 4 && !brw
->is_g4x
)
818 intel_emit_post_sync_nonzero_flush(brw
);
821 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
822 /* use legacy aa line coverage computation */
828 const struct brw_tracked_state brw_aa_line_parameters
= {
831 .brw
= BRW_NEW_CONTEXT
,
834 .emit
= upload_aa_line_parameters
837 /***********************************************************************
838 * Line stipple packet
841 static void upload_line_stipple(struct brw_context
*brw
)
843 struct gl_context
*ctx
= &brw
->ctx
;
847 if (!ctx
->Line
.StippleFlag
)
851 intel_emit_post_sync_nonzero_flush(brw
);
854 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
855 OUT_BATCH(ctx
->Line
.StipplePattern
);
859 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
860 tmpi
= tmp
* (1<<16);
861 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
865 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
866 tmpi
= tmp
* (1<<13);
867 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
873 const struct brw_tracked_state brw_line_stipple
= {
876 .brw
= BRW_NEW_CONTEXT
,
879 .emit
= upload_line_stipple
883 /***********************************************************************
884 * Misc invariant state packets
888 brw_upload_invariant_state(struct brw_context
*brw
)
890 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
892 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
894 intel_emit_post_sync_nonzero_flush(brw
);
896 /* Select the 3D pipeline (as opposed to media) */
897 const uint32_t _3DSTATE_PIPELINE_SELECT
=
898 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
900 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 | (brw
->gen
>= 9 ? (3 << 8) : 0));
904 /* Disable depth offset clamping. */
906 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
913 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
919 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
924 const uint32_t _3DSTATE_VF_STATISTICS
=
925 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
927 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 | 1);
931 const struct brw_tracked_state brw_invariant_state
= {
934 .brw
= BRW_NEW_CONTEXT
,
937 .emit
= brw_upload_invariant_state
941 * Define the base addresses which some state is referenced from.
943 * This allows us to avoid having to emit relocations for the objects,
944 * and is actually required for binding table pointers on gen6.
946 * Surface state base address covers binding table pointers and
947 * surface state objects, but not the surfaces that the surface state
950 static void upload_state_base_address( struct brw_context
*brw
)
952 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
953 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
954 * programmed prior to STATE_BASE_ADDRESS.
956 * However, given that the instruction SBA (general state base
957 * address) on this chipset is always set to 0 across X and GL,
958 * maybe this isn't required for us in particular.
962 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
965 intel_emit_post_sync_nonzero_flush(brw
);
968 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
969 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
970 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
971 1); /* General State Base Address Modify Enable */
972 /* Surface state base address:
973 * BINDING_TABLE_STATE
976 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
977 /* Dynamic state base address:
979 * SAMPLER_BORDER_COLOR_STATE
980 * CLIP, SF, WM/CC viewport state
982 * DEPTH_STENCIL_STATE
984 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
985 * Disable is clear, which we rely on)
987 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
988 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
990 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
991 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
992 1); /* Instruction base address: shader kernels (incl. SIP) */
994 OUT_BATCH(1); /* General state upper bound */
995 /* Dynamic state upper bound. Although the documentation says that
996 * programming it to zero will cause it to be ignored, that is a lie.
997 * If this isn't programmed to a real bound, the sampler border color
998 * pointer is rejected, causing border color to mysteriously fail.
1000 OUT_BATCH(0xfffff001);
1001 OUT_BATCH(1); /* Indirect object upper bound */
1002 OUT_BATCH(1); /* Instruction access upper bound */
1004 } else if (brw
->gen
== 5) {
1006 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
1007 OUT_BATCH(1); /* General state base address */
1008 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1009 1); /* Surface state base address */
1010 OUT_BATCH(1); /* Indirect object base address */
1011 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1012 1); /* Instruction base address */
1013 OUT_BATCH(0xfffff001); /* General state upper bound */
1014 OUT_BATCH(1); /* Indirect object upper bound */
1015 OUT_BATCH(1); /* Instruction access upper bound */
1019 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1020 OUT_BATCH(1); /* General state base address */
1021 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1022 1); /* Surface state base address */
1023 OUT_BATCH(1); /* Indirect object base address */
1024 OUT_BATCH(1); /* General state upper bound */
1025 OUT_BATCH(1); /* Indirect object upper bound */
1029 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1030 * STATE_BASE_ADDRESS updates require a reissue of:
1032 * 3DSTATE_PIPELINE_POINTERS
1033 * 3DSTATE_BINDING_TABLE_POINTERS
1034 * MEDIA_STATE_POINTERS
1036 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1037 * 1 part 1 says that the folowing packets must be reissued:
1039 * 3DSTATE_CC_POINTERS
1040 * 3DSTATE_BINDING_TABLE_POINTERS
1041 * 3DSTATE_SAMPLER_STATE_POINTERS
1042 * 3DSTATE_VIEWPORT_STATE_POINTERS
1043 * MEDIA_STATE_POINTERS
1045 * Those are always reissued following SBA updates anyway (new
1046 * batch time), except in the case of the program cache BO
1047 * changing. Having a separate state flag makes the sequence more
1051 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
1054 const struct brw_tracked_state brw_state_base_address
= {
1057 .brw
= BRW_NEW_BATCH
|
1058 BRW_NEW_PROGRAM_CACHE
,
1061 .emit
= upload_state_base_address