2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
42 #include "main/fbobject.h"
43 #include "main/glformats.h"
45 /* Constant single cliprect for framebuffer object or DRI2 drawing */
46 static void upload_drawing_rect(struct brw_context
*brw
)
48 struct gl_context
*ctx
= &brw
->ctx
;
50 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined. */
52 intel_emit_post_sync_nonzero_flush(brw
);
55 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
56 OUT_BATCH(0); /* xmin, ymin */
57 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
58 ((ctx
->DrawBuffer
->Height
- 1) << 16));
63 const struct brw_tracked_state brw_drawing_rect
= {
66 .brw
= BRW_NEW_CONTEXT
,
68 .emit
= upload_drawing_rect
72 * Upload pointers to the per-stage state.
74 * The state pointers in this packet are all relative to the general state
75 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
77 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
80 /* Need to flush before changing clip max threads for errata. */
87 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
88 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
89 brw
->vs
.base
.state_offset
);
90 if (brw
->ff_gs
.prog_active
)
91 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
92 brw
->ff_gs
.state_offset
| 1);
95 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
96 brw
->clip
.state_offset
| 1);
97 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
98 brw
->sf
.state_offset
);
99 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
100 brw
->wm
.base
.state_offset
);
101 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
102 brw
->cc
.state_offset
);
105 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
108 static void upload_psp_urb_cbs(struct brw_context
*brw
)
110 upload_pipelined_state_pointers(brw
);
111 brw_upload_urb_fence(brw
);
112 brw_upload_cs_urb_state(brw
);
115 const struct brw_tracked_state brw_psp_urb_cbs
= {
118 .brw
= BRW_NEW_BATCH
|
119 BRW_NEW_FF_GS_PROG_DATA
|
120 BRW_NEW_GEN4_UNIT_STATE
|
121 BRW_NEW_STATE_BASE_ADDRESS
|
124 .emit
= upload_psp_urb_cbs
,
128 brw_depthbuffer_format(struct brw_context
*brw
)
130 struct gl_context
*ctx
= &brw
->ctx
;
131 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
132 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
133 struct intel_renderbuffer
*srb
;
136 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
137 !srb
->mt
->stencil_mt
&&
138 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
139 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
144 return BRW_DEPTHFORMAT_D32_FLOAT
;
146 return brw_depth_format(brw
, drb
->mt
->format
);
150 * Returns the mask of how many bits of x and y must be handled through the
151 * depthbuffer's draw offset x and y fields.
153 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
154 * between the depth, hiz, and stencil buffers. Because it can be hard to get
155 * all 3 to agree on this value, we want to do as much drawing offset
156 * adjustment as possible by moving the base offset of the 3 buffers, which is
157 * restricted to tile boundaries.
159 * For each buffer, the remainder must be applied through the x/y draw offset.
160 * This returns the worst-case mask of the low bits that have to go into the
161 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
162 * mask, then we're in trouble.
165 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
166 uint32_t depth_level
,
167 uint32_t depth_layer
,
168 struct intel_mipmap_tree
*stencil_mt
,
169 uint32_t *out_tile_mask_x
,
170 uint32_t *out_tile_mask_y
)
172 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
175 intel_miptree_get_tile_masks(depth_mt
, &tile_mask_x
, &tile_mask_y
, false);
177 if (intel_miptree_level_has_hiz(depth_mt
, depth_level
)) {
178 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
179 intel_miptree_get_tile_masks(depth_mt
->hiz_mt
,
180 &hiz_tile_mask_x
, &hiz_tile_mask_y
,
183 /* Each HiZ row represents 2 rows of pixels */
184 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
186 tile_mask_x
|= hiz_tile_mask_x
;
187 tile_mask_y
|= hiz_tile_mask_y
;
192 if (stencil_mt
->stencil_mt
)
193 stencil_mt
= stencil_mt
->stencil_mt
;
195 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
196 /* Separate stencil buffer uses 64x64 tiles. */
200 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
201 intel_miptree_get_tile_masks(stencil_mt
,
202 &stencil_tile_mask_x
,
203 &stencil_tile_mask_y
, false);
205 tile_mask_x
|= stencil_tile_mask_x
;
206 tile_mask_y
|= stencil_tile_mask_y
;
210 *out_tile_mask_x
= tile_mask_x
;
211 *out_tile_mask_y
= tile_mask_y
;
214 static struct intel_mipmap_tree
*
215 get_stencil_miptree(struct intel_renderbuffer
*irb
)
219 if (irb
->mt
->stencil_mt
)
220 return irb
->mt
->stencil_mt
;
225 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
226 GLbitfield clear_mask
)
228 struct gl_context
*ctx
= &brw
->ctx
;
229 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
230 bool rebase_depth
= false;
231 bool rebase_stencil
= false;
232 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
233 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
234 struct intel_mipmap_tree
*depth_mt
= NULL
;
235 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
236 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
237 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
238 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
239 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
242 depth_mt
= depth_irb
->mt
;
244 /* Initialize brw->depthstencil to 'nop' workaround state.
246 brw
->depthstencil
.tile_x
= 0;
247 brw
->depthstencil
.tile_y
= 0;
248 brw
->depthstencil
.depth_offset
= 0;
249 brw
->depthstencil
.stencil_offset
= 0;
250 brw
->depthstencil
.hiz_offset
= 0;
251 brw
->depthstencil
.depth_mt
= NULL
;
252 brw
->depthstencil
.stencil_mt
= NULL
;
254 brw
->depthstencil
.depth_mt
= depth_mt
;
256 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
258 /* Gen6+ doesn't require the workarounds, since we always program the
259 * surface state at the start of the whole surface.
264 /* Check if depth buffer is in depth/stencil format. If so, then it's only
265 * safe to invalidate it if we're also clearing stencil, and both depth_irb
266 * and stencil_irb point to the same miptree.
268 * Note: it's not sufficient to check for the case where
269 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
270 * because this fails to catch depth/stencil buffers on hardware that uses
271 * separate stencil. To catch that case, we check whether
272 * depth_mt->stencil_mt is non-NULL.
274 if (depth_irb
&& invalidate_depth
&&
275 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
276 depth_mt
->stencil_mt
)) {
277 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
278 && depth_irb
->mt
== stencil_irb
->mt
;
281 uint32_t tile_mask_x
, tile_mask_y
;
282 brw_get_depthstencil_tile_masks(depth_mt
,
283 depth_mt
? depth_irb
->mt_level
: 0,
284 depth_mt
? depth_irb
->mt_layer
: 0,
286 &tile_mask_x
, &tile_mask_y
);
289 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
290 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
292 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
293 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
294 * Coordinate Offset X/Y":
296 * "The 3 LSBs of both offsets must be zero to ensure correct
299 if (tile_x
& 7 || tile_y
& 7)
302 /* We didn't even have intra-tile offsets before g45. */
303 if (!brw
->has_surface_tile_offset
) {
304 if (tile_x
|| tile_y
)
309 perf_debug("HW workaround: blitting depth level %d to a temporary "
310 "to fix alignment (depth tile offset %d,%d)\n",
311 depth_irb
->mt_level
, tile_x
, tile_y
);
312 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
313 /* In the case of stencil_irb being the same packed depth/stencil
314 * texture but not the same rb, make it point at our rebased mt, too.
317 stencil_irb
!= depth_irb
&&
318 stencil_irb
->mt
== depth_mt
) {
319 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
320 intel_renderbuffer_set_draw_offset(stencil_irb
);
323 stencil_mt
= get_stencil_miptree(stencil_irb
);
325 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
326 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
330 stencil_mt
= get_stencil_miptree(stencil_irb
);
331 intel_miptree_get_image_offset(stencil_mt
,
332 stencil_irb
->mt_level
,
333 stencil_irb
->mt_layer
,
334 &stencil_draw_x
, &stencil_draw_y
);
335 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
336 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
338 /* If stencil doesn't match depth, then we'll need to rebase stencil
339 * as well. (if we hadn't decided to rebase stencil before, the
340 * post-stencil depth test will also rebase depth to try to match it
343 if (tile_x
!= stencil_tile_x
||
344 tile_y
!= stencil_tile_y
) {
345 rebase_stencil
= true;
350 /* If we have (just) stencil, check it for ignored low bits as well */
352 intel_miptree_get_image_offset(stencil_mt
,
353 stencil_irb
->mt_level
,
354 stencil_irb
->mt_layer
,
355 &stencil_draw_x
, &stencil_draw_y
);
356 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
357 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
359 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
360 rebase_stencil
= true;
362 if (!brw
->has_surface_tile_offset
) {
363 if (stencil_tile_x
|| stencil_tile_y
)
364 rebase_stencil
= true;
368 if (rebase_stencil
) {
369 perf_debug("HW workaround: blitting stencil level %d to a temporary "
370 "to fix alignment (stencil tile offset %d,%d)\n",
371 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
373 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
374 stencil_mt
= get_stencil_miptree(stencil_irb
);
376 intel_miptree_get_image_offset(stencil_mt
,
377 stencil_irb
->mt_level
,
378 stencil_irb
->mt_layer
,
379 &stencil_draw_x
, &stencil_draw_y
);
380 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
381 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
383 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
384 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
385 intel_renderbuffer_set_draw_offset(depth_irb
);
386 } else if (depth_irb
&& !rebase_depth
) {
387 if (tile_x
!= stencil_tile_x
||
388 tile_y
!= stencil_tile_y
) {
389 perf_debug("HW workaround: blitting depth level %d to a temporary "
390 "to match stencil level %d alignment (depth tile offset "
391 "%d,%d, stencil offset %d,%d)\n",
393 stencil_irb
->mt_level
,
395 stencil_tile_x
, stencil_tile_y
);
397 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
399 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
400 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
402 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
403 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
404 intel_renderbuffer_set_draw_offset(stencil_irb
);
407 WARN_ONCE(stencil_tile_x
!= tile_x
||
408 stencil_tile_y
!= tile_y
,
409 "Rebased stencil tile offset (%d,%d) doesn't match depth "
410 "tile offset (%d,%d).\n",
411 stencil_tile_x
, stencil_tile_y
,
418 tile_x
= stencil_tile_x
;
419 tile_y
= stencil_tile_y
;
422 /* While we just tried to get everything aligned, we may have failed to do
423 * so in the case of rendering to array or 3D textures, where nonzero faces
424 * will still have an offset post-rebase. At least give an informative
427 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
428 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
429 "Truncating offset, bad rendering may occur.\n");
433 /* Now, after rebasing, save off the new dephtstencil state so the hardware
434 * packets can just dereference that without re-calculating tile offsets.
436 brw
->depthstencil
.tile_x
= tile_x
;
437 brw
->depthstencil
.tile_y
= tile_y
;
439 depth_mt
= depth_irb
->mt
;
440 brw
->depthstencil
.depth_mt
= depth_mt
;
441 brw
->depthstencil
.depth_offset
=
442 intel_miptree_get_aligned_offset(depth_mt
,
443 depth_irb
->draw_x
& ~tile_mask_x
,
444 depth_irb
->draw_y
& ~tile_mask_y
,
446 if (intel_renderbuffer_has_hiz(depth_irb
)) {
447 brw
->depthstencil
.hiz_offset
=
448 intel_miptree_get_aligned_offset(depth_mt
,
449 depth_irb
->draw_x
& ~tile_mask_x
,
450 (depth_irb
->draw_y
& ~tile_mask_y
) / 2,
455 stencil_mt
= get_stencil_miptree(stencil_irb
);
457 brw
->depthstencil
.stencil_mt
= stencil_mt
;
458 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
459 /* Note: we can't compute the stencil offset using
460 * intel_region_get_aligned_offset(), because stencil_region claims
461 * that the region is untiled even though it's W tiled.
463 brw
->depthstencil
.stencil_offset
=
464 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
465 (stencil_draw_x
& ~tile_mask_x
) * 64;
471 brw_emit_depthbuffer(struct brw_context
*brw
)
473 struct gl_context
*ctx
= &brw
->ctx
;
474 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
476 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
477 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
478 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
479 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
480 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
481 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
482 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
483 bool separate_stencil
= false;
484 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
485 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
486 uint32_t depth_offset
= 0;
487 uint32_t width
= 1, height
= 1;
490 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
492 /* Gen7 supports only separate stencil */
493 assert(separate_stencil
|| brw
->gen
< 7);
496 /* If there's a packed depth/stencil bound to stencil only, we need to
497 * emit the packed depth/stencil buffer packet.
499 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
500 depth_irb
= stencil_irb
;
501 depth_mt
= stencil_mt
;
504 if (depth_irb
&& depth_mt
) {
505 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
506 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
507 * depthstencil format.
509 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
510 * set to the same value. Gens after 7 implicitly always set
511 * Separate_Stencil_Enable; software cannot disable it.
513 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
514 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
517 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
518 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
520 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
521 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
523 depthbuffer_format
= brw_depthbuffer_format(brw
);
524 depth_surface_type
= BRW_SURFACE_2D
;
525 depth_offset
= brw
->depthstencil
.depth_offset
;
526 width
= depth_irb
->Base
.Base
.Width
;
527 height
= depth_irb
->Base
.Base
.Height
;
528 } else if (separate_stencil
) {
530 * There exists a separate stencil buffer but no depth buffer.
532 * The stencil buffer inherits most of its fields from
533 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
536 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
537 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
538 * [DevGT+]: This field must be set to TRUE.
540 assert(brw
->has_separate_stencil
);
542 depth_surface_type
= BRW_SURFACE_2D
;
543 width
= stencil_irb
->Base
.Base
.Width
;
544 height
= stencil_irb
->Base
.Base
.Height
;
548 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
550 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
552 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
553 depthbuffer_format
, depth_surface_type
,
554 stencil_mt
, hiz
, separate_stencil
,
555 width
, height
, tile_x
, tile_y
);
559 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
560 struct intel_mipmap_tree
*depth_mt
,
561 uint32_t depth_offset
, uint32_t depthbuffer_format
,
562 uint32_t depth_surface_type
,
563 struct intel_mipmap_tree
*stencil_mt
,
564 bool hiz
, bool separate_stencil
,
565 uint32_t width
, uint32_t height
,
566 uint32_t tile_x
, uint32_t tile_y
)
568 /* Enable the hiz bit if we're doing separate stencil, because it and the
569 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
570 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
571 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
572 * Enable must also be enabled.
574 * [DevGT]: This field must be set to the same value (enabled or
575 * disabled) as Hierarchical Depth Buffer Enable
577 bool enable_hiz_ss
= hiz
|| separate_stencil
;
580 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
581 * non-pipelined state that will need the PIPE_CONTROL workaround.
584 intel_emit_post_sync_nonzero_flush(brw
);
585 intel_emit_depth_stall_flushes(brw
);
591 else if (brw
->is_g4x
|| brw
->gen
== 5)
597 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
598 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
599 (depthbuffer_format
<< 18) |
600 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
601 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
602 (BRW_TILEWALK_YMAJOR
<< 26) |
603 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
605 (depth_surface_type
<< 29));
608 OUT_RELOC(depth_mt
->bo
,
609 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
615 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
616 ((height
+ tile_y
- 1) << 19));
619 if (brw
->is_g4x
|| brw
->gen
>= 5)
620 OUT_BATCH(tile_x
| (tile_y
<< 16));
622 assert(tile_x
== 0 && tile_y
== 0);
629 if (hiz
|| separate_stencil
) {
631 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
632 * stencil enable' and 'hiz enable' bits were set. Therefore we must
633 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
634 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
635 * failure to do so causes hangs on gen5 and a stall on gen6.
638 /* Emit hiz buffer. */
640 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_mt
;
642 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
643 OUT_BATCH(hiz_mt
->pitch
- 1);
644 OUT_RELOC(hiz_mt
->bo
,
645 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
646 brw
->depthstencil
.hiz_offset
);
650 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
656 /* Emit stencil buffer. */
657 if (separate_stencil
) {
659 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
660 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
661 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
662 * The pitch must be set to 2x the value computed based on width, as
663 * the stencil buffer is stored with two rows interleaved.
665 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
666 OUT_RELOC(stencil_mt
->bo
,
667 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
668 brw
->depthstencil
.stencil_offset
);
672 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
680 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
681 * params must be emitted.
683 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
684 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
685 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
687 if (brw
->gen
>= 6 || hiz
) {
689 intel_emit_post_sync_nonzero_flush(brw
);
692 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
693 GEN5_DEPTH_CLEAR_VALID
|
695 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
700 const struct brw_tracked_state brw_depthbuffer
= {
702 .mesa
= _NEW_BUFFERS
,
703 .brw
= BRW_NEW_BATCH
,
705 .emit
= brw_emit_depthbuffer
,
710 /***********************************************************************
711 * Polygon stipple packet
714 static void upload_polygon_stipple(struct brw_context
*brw
)
716 struct gl_context
*ctx
= &brw
->ctx
;
720 if (!ctx
->Polygon
.StippleFlag
)
724 intel_emit_post_sync_nonzero_flush(brw
);
727 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
729 /* Polygon stipple is provided in OpenGL order, i.e. bottom
730 * row first. If we're rendering to a window (i.e. the
731 * default frame buffer object, 0), then we need to invert
732 * it to match our pixel layout. But if we're rendering
733 * to a FBO (i.e. any named frame buffer object), we *don't*
734 * need to invert - we already match the layout.
736 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
737 for (i
= 0; i
< 32; i
++)
738 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
741 for (i
= 0; i
< 32; i
++)
742 OUT_BATCH(ctx
->PolygonStipple
[i
]);
747 const struct brw_tracked_state brw_polygon_stipple
= {
749 .mesa
= _NEW_POLYGON
|
751 .brw
= BRW_NEW_CONTEXT
,
753 .emit
= upload_polygon_stipple
757 /***********************************************************************
758 * Polygon stipple offset packet
761 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
763 struct gl_context
*ctx
= &brw
->ctx
;
766 if (!ctx
->Polygon
.StippleFlag
)
770 intel_emit_post_sync_nonzero_flush(brw
);
773 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
777 * If we're drawing to a system window we have to invert the Y axis
778 * in order to match the OpenGL pixel coordinate system, and our
779 * offset must be matched to the window position. If we're drawing
780 * to a user-created FBO then our native pixel coordinate system
781 * works just fine, and there's no window system to worry about.
783 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
784 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
790 const struct brw_tracked_state brw_polygon_stipple_offset
= {
792 .mesa
= _NEW_BUFFERS
|
794 .brw
= BRW_NEW_CONTEXT
,
796 .emit
= upload_polygon_stipple_offset
799 /**********************************************************************
802 static void upload_aa_line_parameters(struct brw_context
*brw
)
804 struct gl_context
*ctx
= &brw
->ctx
;
806 if (!ctx
->Line
.SmoothFlag
)
809 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
810 if (brw
->gen
== 4 && !brw
->is_g4x
)
814 intel_emit_post_sync_nonzero_flush(brw
);
817 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
818 /* use legacy aa line coverage computation */
824 const struct brw_tracked_state brw_aa_line_parameters
= {
827 .brw
= BRW_NEW_CONTEXT
,
829 .emit
= upload_aa_line_parameters
832 /***********************************************************************
833 * Line stipple packet
836 static void upload_line_stipple(struct brw_context
*brw
)
838 struct gl_context
*ctx
= &brw
->ctx
;
842 if (!ctx
->Line
.StippleFlag
)
846 intel_emit_post_sync_nonzero_flush(brw
);
849 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
850 OUT_BATCH(ctx
->Line
.StipplePattern
);
854 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
855 tmpi
= tmp
* (1<<16);
856 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
860 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
861 tmpi
= tmp
* (1<<13);
862 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
868 const struct brw_tracked_state brw_line_stipple
= {
871 .brw
= BRW_NEW_CONTEXT
,
873 .emit
= upload_line_stipple
877 /***********************************************************************
878 * Misc invariant state packets
882 brw_upload_invariant_state(struct brw_context
*brw
)
884 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
886 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
888 intel_emit_post_sync_nonzero_flush(brw
);
890 /* Select the 3D pipeline (as opposed to media) */
891 const uint32_t _3DSTATE_PIPELINE_SELECT
=
892 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
894 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 | (brw
->gen
>= 9 ? (3 << 8) : 0));
898 /* Disable depth offset clamping. */
900 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
907 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
913 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
918 const uint32_t _3DSTATE_VF_STATISTICS
=
919 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
921 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 | 1);
925 const struct brw_tracked_state brw_invariant_state
= {
928 .brw
= BRW_NEW_CONTEXT
,
930 .emit
= brw_upload_invariant_state
934 * Define the base addresses which some state is referenced from.
936 * This allows us to avoid having to emit relocations for the objects,
937 * and is actually required for binding table pointers on gen6.
939 * Surface state base address covers binding table pointers and
940 * surface state objects, but not the surfaces that the surface state
943 static void upload_state_base_address( struct brw_context
*brw
)
945 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
946 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
947 * programmed prior to STATE_BASE_ADDRESS.
949 * However, given that the instruction SBA (general state base
950 * address) on this chipset is always set to 0 across X and GL,
951 * maybe this isn't required for us in particular.
955 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
958 intel_emit_post_sync_nonzero_flush(brw
);
961 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
962 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
963 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
964 1); /* General State Base Address Modify Enable */
965 /* Surface state base address:
966 * BINDING_TABLE_STATE
969 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
970 /* Dynamic state base address:
972 * SAMPLER_BORDER_COLOR_STATE
973 * CLIP, SF, WM/CC viewport state
975 * DEPTH_STENCIL_STATE
977 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
978 * Disable is clear, which we rely on)
980 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
981 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
983 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
984 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
985 1); /* Instruction base address: shader kernels (incl. SIP) */
987 OUT_BATCH(1); /* General state upper bound */
988 /* Dynamic state upper bound. Although the documentation says that
989 * programming it to zero will cause it to be ignored, that is a lie.
990 * If this isn't programmed to a real bound, the sampler border color
991 * pointer is rejected, causing border color to mysteriously fail.
993 OUT_BATCH(0xfffff001);
994 OUT_BATCH(1); /* Indirect object upper bound */
995 OUT_BATCH(1); /* Instruction access upper bound */
997 } else if (brw
->gen
== 5) {
999 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
1000 OUT_BATCH(1); /* General state base address */
1001 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1002 1); /* Surface state base address */
1003 OUT_BATCH(1); /* Indirect object base address */
1004 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1005 1); /* Instruction base address */
1006 OUT_BATCH(0xfffff001); /* General state upper bound */
1007 OUT_BATCH(1); /* Indirect object upper bound */
1008 OUT_BATCH(1); /* Instruction access upper bound */
1012 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1013 OUT_BATCH(1); /* General state base address */
1014 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1015 1); /* Surface state base address */
1016 OUT_BATCH(1); /* Indirect object base address */
1017 OUT_BATCH(1); /* General state upper bound */
1018 OUT_BATCH(1); /* Indirect object upper bound */
1022 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1023 * STATE_BASE_ADDRESS updates require a reissue of:
1025 * 3DSTATE_PIPELINE_POINTERS
1026 * 3DSTATE_BINDING_TABLE_POINTERS
1027 * MEDIA_STATE_POINTERS
1029 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1030 * 1 part 1 says that the folowing packets must be reissued:
1032 * 3DSTATE_CC_POINTERS
1033 * 3DSTATE_BINDING_TABLE_POINTERS
1034 * 3DSTATE_SAMPLER_STATE_POINTERS
1035 * 3DSTATE_VIEWPORT_STATE_POINTERS
1036 * MEDIA_STATE_POINTERS
1038 * Those are always reissued following SBA updates anyway (new
1039 * batch time), except in the case of the program cache BO
1040 * changing. Having a separate state flag makes the sequence more
1044 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
1047 const struct brw_tracked_state brw_state_base_address
= {
1050 .brw
= BRW_NEW_BATCH
|
1051 BRW_NEW_PROGRAM_CACHE
,
1053 .emit
= upload_state_base_address