2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
41 #include "compiler/brw_eu_defines.h"
43 #include "main/framebuffer.h"
44 #include "main/fbobject.h"
45 #include "main/format_utils.h"
46 #include "main/glformats.h"
49 * Upload pointers to the per-stage state.
51 * The state pointers in this packet are all relative to the general state
52 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
55 upload_pipelined_state_pointers(struct brw_context
*brw
)
58 /* Need to flush before changing clip max threads for errata. */
65 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
66 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
67 brw
->vs
.base
.state_offset
);
68 if (brw
->ff_gs
.prog_active
)
69 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
70 brw
->ff_gs
.state_offset
| 1);
73 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
74 brw
->clip
.state_offset
| 1);
75 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
76 brw
->sf
.state_offset
);
77 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
78 brw
->wm
.base
.state_offset
);
79 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
80 brw
->cc
.state_offset
);
83 brw
->ctx
.NewDriverState
|= BRW_NEW_PSP
;
87 upload_psp_urb_cbs(struct brw_context
*brw
)
89 upload_pipelined_state_pointers(brw
);
90 brw_upload_urb_fence(brw
);
91 brw_upload_cs_urb_state(brw
);
94 const struct brw_tracked_state brw_psp_urb_cbs
= {
97 .brw
= BRW_NEW_BATCH
|
99 BRW_NEW_FF_GS_PROG_DATA
|
100 BRW_NEW_GEN4_UNIT_STATE
|
101 BRW_NEW_STATE_BASE_ADDRESS
|
104 .emit
= upload_psp_urb_cbs
,
108 brw_depthbuffer_format(struct brw_context
*brw
)
110 struct gl_context
*ctx
= &brw
->ctx
;
111 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
112 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
113 struct intel_renderbuffer
*srb
;
116 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
117 !srb
->mt
->stencil_mt
&&
118 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
119 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
124 return BRW_DEPTHFORMAT_D32_FLOAT
;
126 return brw_depth_format(brw
, drb
->mt
->format
);
130 * Returns the mask of how many bits of x and y must be handled through the
131 * depthbuffer's draw offset x and y fields.
133 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
134 * between the depth, hiz, and stencil buffers. Because it can be hard to get
135 * all 3 to agree on this value, we want to do as much drawing offset
136 * adjustment as possible by moving the base offset of the 3 buffers, which is
137 * restricted to tile boundaries.
139 * For each buffer, the remainder must be applied through the x/y draw offset.
140 * This returns the worst-case mask of the low bits that have to go into the
141 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
142 * mask, then we're in trouble.
145 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
146 uint32_t depth_level
,
147 uint32_t depth_layer
,
148 struct intel_mipmap_tree
*stencil_mt
,
149 uint32_t *out_tile_mask_x
,
150 uint32_t *out_tile_mask_y
)
152 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
155 intel_get_tile_masks(depth_mt
->tiling
,
157 &tile_mask_x
, &tile_mask_y
);
158 assert(!intel_miptree_level_has_hiz(depth_mt
, depth_level
));
162 if (stencil_mt
->stencil_mt
)
163 stencil_mt
= stencil_mt
->stencil_mt
;
165 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
166 /* Separate stencil buffer uses 64x64 tiles. */
170 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
171 intel_get_tile_masks(stencil_mt
->tiling
,
173 &stencil_tile_mask_x
,
174 &stencil_tile_mask_y
);
176 tile_mask_x
|= stencil_tile_mask_x
;
177 tile_mask_y
|= stencil_tile_mask_y
;
181 *out_tile_mask_x
= tile_mask_x
;
182 *out_tile_mask_y
= tile_mask_y
;
185 static struct intel_mipmap_tree
*
186 get_stencil_miptree(struct intel_renderbuffer
*irb
)
190 if (irb
->mt
->stencil_mt
)
191 return irb
->mt
->stencil_mt
;
196 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
197 GLbitfield clear_mask
)
199 struct gl_context
*ctx
= &brw
->ctx
;
200 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
201 bool rebase_depth
= false;
202 bool rebase_stencil
= false;
203 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
204 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
205 struct intel_mipmap_tree
*depth_mt
= NULL
;
206 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
207 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
208 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
209 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
210 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
213 depth_mt
= depth_irb
->mt
;
215 /* Initialize brw->depthstencil to 'nop' workaround state.
217 brw
->depthstencil
.tile_x
= 0;
218 brw
->depthstencil
.tile_y
= 0;
219 brw
->depthstencil
.depth_offset
= 0;
220 brw
->depthstencil
.stencil_offset
= 0;
221 brw
->depthstencil
.hiz_offset
= 0;
222 brw
->depthstencil
.depth_mt
= NULL
;
223 brw
->depthstencil
.stencil_mt
= NULL
;
225 brw
->depthstencil
.depth_mt
= depth_mt
;
227 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
229 /* Gen6+ doesn't require the workarounds, since we always program the
230 * surface state at the start of the whole surface.
235 /* Check if depth buffer is in depth/stencil format. If so, then it's only
236 * safe to invalidate it if we're also clearing stencil, and both depth_irb
237 * and stencil_irb point to the same miptree.
239 * Note: it's not sufficient to check for the case where
240 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
241 * because this fails to catch depth/stencil buffers on hardware that uses
242 * separate stencil. To catch that case, we check whether
243 * depth_mt->stencil_mt is non-NULL.
245 if (depth_irb
&& invalidate_depth
&&
246 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
247 depth_mt
->stencil_mt
)) {
248 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
249 && depth_irb
->mt
== stencil_irb
->mt
;
252 uint32_t tile_mask_x
, tile_mask_y
;
253 brw_get_depthstencil_tile_masks(depth_mt
,
254 depth_mt
? depth_irb
->mt_level
: 0,
255 depth_mt
? depth_irb
->mt_layer
: 0,
257 &tile_mask_x
, &tile_mask_y
);
260 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
261 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
263 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
264 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
265 * Coordinate Offset X/Y":
267 * "The 3 LSBs of both offsets must be zero to ensure correct
270 if (tile_x
& 7 || tile_y
& 7)
273 /* We didn't even have intra-tile offsets before g45. */
274 if (!brw
->has_surface_tile_offset
) {
275 if (tile_x
|| tile_y
)
280 perf_debug("HW workaround: blitting depth level %d to a temporary "
281 "to fix alignment (depth tile offset %d,%d)\n",
282 depth_irb
->mt_level
, tile_x
, tile_y
);
283 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
284 /* In the case of stencil_irb being the same packed depth/stencil
285 * texture but not the same rb, make it point at our rebased mt, too.
288 stencil_irb
!= depth_irb
&&
289 stencil_irb
->mt
== depth_mt
) {
290 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
291 intel_renderbuffer_set_draw_offset(stencil_irb
);
294 stencil_mt
= get_stencil_miptree(stencil_irb
);
296 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
297 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
301 stencil_mt
= get_stencil_miptree(stencil_irb
);
302 intel_miptree_get_image_offset(stencil_mt
,
303 stencil_irb
->mt_level
,
304 stencil_irb
->mt_layer
,
305 &stencil_draw_x
, &stencil_draw_y
);
306 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
307 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
309 /* If stencil doesn't match depth, then we'll need to rebase stencil
310 * as well. (if we hadn't decided to rebase stencil before, the
311 * post-stencil depth test will also rebase depth to try to match it
314 if (tile_x
!= stencil_tile_x
||
315 tile_y
!= stencil_tile_y
) {
316 rebase_stencil
= true;
321 /* If we have (just) stencil, check it for ignored low bits as well */
323 intel_miptree_get_image_offset(stencil_mt
,
324 stencil_irb
->mt_level
,
325 stencil_irb
->mt_layer
,
326 &stencil_draw_x
, &stencil_draw_y
);
327 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
328 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
330 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
331 rebase_stencil
= true;
333 if (!brw
->has_surface_tile_offset
) {
334 if (stencil_tile_x
|| stencil_tile_y
)
335 rebase_stencil
= true;
339 if (rebase_stencil
) {
340 perf_debug("HW workaround: blitting stencil level %d to a temporary "
341 "to fix alignment (stencil tile offset %d,%d)\n",
342 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
344 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
345 stencil_mt
= get_stencil_miptree(stencil_irb
);
347 intel_miptree_get_image_offset(stencil_mt
,
348 stencil_irb
->mt_level
,
349 stencil_irb
->mt_layer
,
350 &stencil_draw_x
, &stencil_draw_y
);
351 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
352 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
354 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
355 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
356 intel_renderbuffer_set_draw_offset(depth_irb
);
357 } else if (depth_irb
&& !rebase_depth
) {
358 if (tile_x
!= stencil_tile_x
||
359 tile_y
!= stencil_tile_y
) {
360 perf_debug("HW workaround: blitting depth level %d to a temporary "
361 "to match stencil level %d alignment (depth tile offset "
362 "%d,%d, stencil offset %d,%d)\n",
364 stencil_irb
->mt_level
,
366 stencil_tile_x
, stencil_tile_y
);
368 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
370 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
371 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
373 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
374 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
375 intel_renderbuffer_set_draw_offset(stencil_irb
);
378 WARN_ONCE(stencil_tile_x
!= tile_x
||
379 stencil_tile_y
!= tile_y
,
380 "Rebased stencil tile offset (%d,%d) doesn't match depth "
381 "tile offset (%d,%d).\n",
382 stencil_tile_x
, stencil_tile_y
,
389 tile_x
= stencil_tile_x
;
390 tile_y
= stencil_tile_y
;
393 /* While we just tried to get everything aligned, we may have failed to do
394 * so in the case of rendering to array or 3D textures, where nonzero faces
395 * will still have an offset post-rebase. At least give an informative
398 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
399 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
400 "Truncating offset, bad rendering may occur.\n");
404 /* Now, after rebasing, save off the new dephtstencil state so the hardware
405 * packets can just dereference that without re-calculating tile offsets.
407 brw
->depthstencil
.tile_x
= tile_x
;
408 brw
->depthstencil
.tile_y
= tile_y
;
410 depth_mt
= depth_irb
->mt
;
411 brw
->depthstencil
.depth_mt
= depth_mt
;
412 brw
->depthstencil
.depth_offset
=
413 intel_miptree_get_aligned_offset(depth_mt
,
414 depth_irb
->draw_x
& ~tile_mask_x
,
415 depth_irb
->draw_y
& ~tile_mask_y
);
416 if (intel_renderbuffer_has_hiz(depth_irb
)) {
417 brw
->depthstencil
.hiz_offset
=
418 intel_miptree_get_aligned_offset(depth_mt
,
419 depth_irb
->draw_x
& ~tile_mask_x
,
420 (depth_irb
->draw_y
& ~tile_mask_y
) / 2);
424 stencil_mt
= get_stencil_miptree(stencil_irb
);
426 brw
->depthstencil
.stencil_mt
= stencil_mt
;
427 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
428 /* Note: we can't compute the stencil offset using
429 * intel_region_get_aligned_offset(), because stencil_region claims
430 * that the region is untiled even though it's W tiled.
432 brw
->depthstencil
.stencil_offset
=
433 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
434 (stencil_draw_x
& ~tile_mask_x
) * 64;
435 } else if (!depth_irb
) {
436 brw
->depthstencil
.depth_offset
=
437 intel_miptree_get_aligned_offset(
439 stencil_irb
->draw_x
& ~tile_mask_x
,
440 stencil_irb
->draw_y
& ~tile_mask_y
);
446 brw_emit_depthbuffer(struct brw_context
*brw
)
448 struct gl_context
*ctx
= &brw
->ctx
;
449 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
451 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
452 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
453 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
454 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
455 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
456 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
457 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
458 bool separate_stencil
= false;
459 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
460 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
461 uint32_t depth_offset
= 0;
462 uint32_t width
= 1, height
= 1;
465 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
467 /* Gen7 supports only separate stencil */
468 assert(separate_stencil
|| brw
->gen
< 7);
471 /* If there's a packed depth/stencil bound to stencil only, we need to
472 * emit the packed depth/stencil buffer packet.
474 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
475 depth_irb
= stencil_irb
;
476 depth_mt
= stencil_mt
;
479 if (depth_irb
&& depth_mt
) {
480 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
481 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
482 * depthstencil format.
484 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
485 * set to the same value. Gens after 7 implicitly always set
486 * Separate_Stencil_Enable; software cannot disable it.
488 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
489 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
492 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
493 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
495 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
496 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
498 depthbuffer_format
= brw_depthbuffer_format(brw
);
499 depth_surface_type
= BRW_SURFACE_2D
;
500 depth_offset
= brw
->depthstencil
.depth_offset
;
501 width
= depth_irb
->Base
.Base
.Width
;
502 height
= depth_irb
->Base
.Base
.Height
;
503 } else if (separate_stencil
) {
505 * There exists a separate stencil buffer but no depth buffer.
507 * The stencil buffer inherits most of its fields from
508 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
511 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
512 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
513 * [DevGT+]: This field must be set to TRUE.
515 assert(brw
->has_separate_stencil
);
517 depth_surface_type
= BRW_SURFACE_2D
;
518 width
= stencil_irb
->Base
.Base
.Width
;
519 height
= stencil_irb
->Base
.Base
.Height
;
523 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
525 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
527 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
528 depthbuffer_format
, depth_surface_type
,
529 stencil_mt
, hiz
, separate_stencil
,
530 width
, height
, tile_x
, tile_y
);
534 brw_convert_depth_value(mesa_format format
, float value
)
537 case MESA_FORMAT_Z_FLOAT32
:
538 return float_as_int(value
);
539 case MESA_FORMAT_Z_UNORM16
:
540 return value
* ((1u << 16) - 1);
541 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
542 return value
* ((1u << 24) - 1);
544 unreachable("Invalid depth format");
549 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
550 struct intel_mipmap_tree
*depth_mt
,
551 uint32_t depth_offset
, uint32_t depthbuffer_format
,
552 uint32_t depth_surface_type
,
553 struct intel_mipmap_tree
*stencil_mt
,
554 bool hiz
, bool separate_stencil
,
555 uint32_t width
, uint32_t height
,
556 uint32_t tile_x
, uint32_t tile_y
)
558 /* Enable the hiz bit if we're doing separate stencil, because it and the
559 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
560 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
561 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
562 * Enable must also be enabled.
564 * [DevGT]: This field must be set to the same value (enabled or
565 * disabled) as Hierarchical Depth Buffer Enable
567 bool enable_hiz_ss
= hiz
|| separate_stencil
;
570 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
571 * non-pipelined state that will need the PIPE_CONTROL workaround.
574 brw_emit_depth_stall_flushes(brw
);
580 else if (brw
->is_g4x
|| brw
->gen
== 5)
586 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
587 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
588 (depthbuffer_format
<< 18) |
589 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
590 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
591 (BRW_TILEWALK_YMAJOR
<< 26) |
592 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
594 (depth_surface_type
<< 29));
597 OUT_RELOC(depth_mt
->bo
,
598 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
604 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
605 ((height
+ tile_y
- 1) << 19));
608 if (brw
->is_g4x
|| brw
->gen
>= 5)
609 OUT_BATCH(tile_x
| (tile_y
<< 16));
611 assert(tile_x
== 0 && tile_y
== 0);
618 if (hiz
|| separate_stencil
) {
620 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
621 * stencil enable' and 'hiz enable' bits were set. Therefore we must
622 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
623 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
624 * failure to do so causes hangs on gen5 and a stall on gen6.
627 /* Emit hiz buffer. */
631 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
632 OUT_BATCH(depth_mt
->hiz_buf
->aux_base
.pitch
- 1);
633 OUT_RELOC(depth_mt
->hiz_buf
->aux_base
.bo
,
634 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
635 brw
->depthstencil
.hiz_offset
);
639 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
645 /* Emit stencil buffer. */
646 if (separate_stencil
) {
648 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
649 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
650 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
651 * The pitch must be set to 2x the value computed based on width, as
652 * the stencil buffer is stored with two rows interleaved.
654 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
655 OUT_RELOC(stencil_mt
->bo
,
656 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
657 brw
->depthstencil
.stencil_offset
);
661 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
669 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
670 * params must be emitted.
672 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
673 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
674 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
676 if (brw
->gen
>= 6 || hiz
) {
678 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
679 GEN5_DEPTH_CLEAR_VALID
|
682 OUT_BATCH(brw_convert_depth_value(depth_mt
->format
,
683 depth_mt
->fast_clear_color
.f32
[0]));
691 const struct brw_tracked_state brw_depthbuffer
= {
693 .mesa
= _NEW_BUFFERS
,
694 .brw
= BRW_NEW_BATCH
|
697 .emit
= brw_emit_depthbuffer
,
701 brw_emit_select_pipeline(struct brw_context
*brw
, enum brw_pipeline pipeline
)
703 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
704 const uint32_t _3DSTATE_PIPELINE_SELECT
=
705 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
707 if (brw
->gen
>= 8 && brw
->gen
< 10) {
708 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
710 * Software must clear the COLOR_CALC_STATE Valid field in
711 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
712 * with Pipeline Select set to GPGPU.
714 * The internal hardware docs recommend the same workaround for Gen9
717 if (pipeline
== BRW_COMPUTE_PIPELINE
) {
719 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
723 brw
->ctx
.NewDriverState
|= BRW_NEW_CC_STATE
;
728 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
729 * PIPELINE_SELECT [DevBWR+]":
733 * Software must ensure all the write caches are flushed through a
734 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
735 * command to invalidate read only caches prior to programming
736 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
738 const unsigned dc_flush
=
739 brw
->gen
>= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH
: 0;
741 brw_emit_pipe_control_flush(brw
,
742 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
743 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
745 PIPE_CONTROL_NO_WRITE
|
746 PIPE_CONTROL_CS_STALL
);
748 brw_emit_pipe_control_flush(brw
,
749 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
750 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
751 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
752 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
753 PIPE_CONTROL_NO_WRITE
);
756 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
757 * PIPELINE_SELECT [DevBWR+]":
759 * Project: PRE-DEVSNB
761 * Software must ensure the current pipeline is flushed via an
762 * MI_FLUSH or PIPE_CONTROL prior to the execution of PIPELINE_SELECT.
769 /* Select the pipeline */
771 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 |
772 (brw
->gen
>= 9 ? (3 << 8) : 0) |
773 (pipeline
== BRW_COMPUTE_PIPELINE
? 2 : 0));
776 if (brw
->gen
== 7 && !brw
->is_haswell
&&
777 pipeline
== BRW_RENDER_PIPELINE
) {
778 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
779 * PIPELINE_SELECT [DevBWR+]":
781 * Project: DEVIVB, DEVHSW:GT3:A0
783 * Software must send a pipe_control with a CS stall and a post sync
784 * operation and then a dummy DRAW after every MI_SET_CONTEXT and
785 * after any PIPELINE_SELECT that is enabling 3D mode.
787 gen7_emit_cs_stall_flush(brw
);
790 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2));
791 OUT_BATCH(_3DPRIM_POINTLIST
);
802 * Misc invariant state packets
805 brw_upload_invariant_state(struct brw_context
*brw
)
807 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
809 brw_emit_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
810 brw
->last_pipeline
= BRW_RENDER_PIPELINE
;
814 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
820 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
825 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
828 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
829 /* use legacy aa line coverage computation */
835 const uint32_t _3DSTATE_VF_STATISTICS
=
836 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
838 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 | 1);
842 const struct brw_tracked_state brw_invariant_state
= {
845 .brw
= BRW_NEW_BLORP
|
848 .emit
= brw_upload_invariant_state
852 * Define the base addresses which some state is referenced from.
854 * This allows us to avoid having to emit relocations for the objects,
855 * and is actually required for binding table pointers on gen6.
857 * Surface state base address covers binding table pointers and
858 * surface state objects, but not the surfaces that the surface state
862 brw_upload_state_base_address(struct brw_context
*brw
)
864 if (brw
->batch
.state_base_address_emitted
)
867 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
868 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
869 * programmed prior to STATE_BASE_ADDRESS.
871 * However, given that the instruction SBA (general state base
872 * address) on this chipset is always set to 0 across X and GL,
873 * maybe this isn't required for us in particular.
877 const unsigned dc_flush
=
878 brw
->gen
>= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH
: 0;
880 /* Emit a render target cache flush.
882 * This isn't documented anywhere in the PRM. However, it seems to be
883 * necessary prior to changing the surface state base adress. We've
884 * seen issues in Vulkan where we get GPU hangs when using multi-level
885 * command buffers which clear depth, reset state base address, and then
888 * Normally, in GL, we would trust the kernel to do sufficient stalls
889 * and flushes prior to executing our batch. However, it doesn't seem
890 * as if the kernel's flushing is always sufficient and we don't want to
893 * We make this an end-of-pipe sync instead of a normal flush because we
894 * do not know the current status of the GPU. On Haswell at least,
895 * having a fast-clear operation in flight at the same time as a normal
896 * rendering operation can cause hangs. Since the kernel's flushing is
897 * insufficient, we need to ensure that any rendering operations from
898 * other processes are definitely complete before we try to do our own
899 * rendering. It's a bit of a big hammer but it appears to work.
901 brw_emit_end_of_pipe_sync(brw
,
902 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
903 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
908 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
909 int pkt_len
= brw
->gen
>= 9 ? 19 : 16;
911 BEGIN_BATCH(pkt_len
);
912 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (pkt_len
- 2));
913 /* General state base address: stateless DP read/write requests */
914 OUT_BATCH(mocs_wb
<< 4 | 1);
916 OUT_BATCH(mocs_wb
<< 16);
917 /* Surface state base address: */
918 OUT_RELOC64(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
920 /* Dynamic state base address: */
921 OUT_RELOC64(brw
->batch
.bo
,
922 I915_GEM_DOMAIN_RENDER
| I915_GEM_DOMAIN_INSTRUCTION
, 0,
924 /* Indirect object base address: MEDIA_OBJECT data */
925 OUT_BATCH(mocs_wb
<< 4 | 1);
927 /* Instruction base address: shader kernels (incl. SIP) */
928 OUT_RELOC64(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
931 /* General state buffer size */
932 OUT_BATCH(0xfffff001);
933 /* Dynamic state buffer size */
934 OUT_BATCH(ALIGN(brw
->batch
.bo
->size
, 4096) | 1);
935 /* Indirect object upper bound */
936 OUT_BATCH(0xfffff001);
937 /* Instruction access upper bound */
938 OUT_BATCH(ALIGN(brw
->cache
.bo
->size
, 4096) | 1);
945 } else if (brw
->gen
>= 6) {
946 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
949 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
950 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
951 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
952 1); /* General State Base Address Modify Enable */
953 /* Surface state base address:
954 * BINDING_TABLE_STATE
957 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
958 /* Dynamic state base address:
960 * SAMPLER_BORDER_COLOR_STATE
961 * CLIP, SF, WM/CC viewport state
963 * DEPTH_STENCIL_STATE
965 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
966 * Disable is clear, which we rely on)
968 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
969 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
971 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
972 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
973 1); /* Instruction base address: shader kernels (incl. SIP) */
975 OUT_BATCH(1); /* General state upper bound */
976 /* Dynamic state upper bound. Although the documentation says that
977 * programming it to zero will cause it to be ignored, that is a lie.
978 * If this isn't programmed to a real bound, the sampler border color
979 * pointer is rejected, causing border color to mysteriously fail.
981 OUT_BATCH(0xfffff001);
982 OUT_BATCH(1); /* Indirect object upper bound */
983 OUT_BATCH(1); /* Instruction access upper bound */
985 } else if (brw
->gen
== 5) {
987 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
988 OUT_BATCH(1); /* General state base address */
989 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
990 1); /* Surface state base address */
991 OUT_BATCH(1); /* Indirect object base address */
992 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
993 1); /* Instruction base address */
994 OUT_BATCH(0xfffff001); /* General state upper bound */
995 OUT_BATCH(1); /* Indirect object upper bound */
996 OUT_BATCH(1); /* Instruction access upper bound */
1000 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1001 OUT_BATCH(1); /* General state base address */
1002 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1003 1); /* Surface state base address */
1004 OUT_BATCH(1); /* Indirect object base address */
1005 OUT_BATCH(1); /* General state upper bound */
1006 OUT_BATCH(1); /* Indirect object upper bound */
1010 if (brw
->gen
>= 6) {
1011 brw_emit_pipe_control_flush(brw
,
1012 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
1013 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
1014 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1017 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1018 * STATE_BASE_ADDRESS updates require a reissue of:
1020 * 3DSTATE_PIPELINE_POINTERS
1021 * 3DSTATE_BINDING_TABLE_POINTERS
1022 * MEDIA_STATE_POINTERS
1024 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1025 * 1 part 1 says that the folowing packets must be reissued:
1027 * 3DSTATE_CC_POINTERS
1028 * 3DSTATE_BINDING_TABLE_POINTERS
1029 * 3DSTATE_SAMPLER_STATE_POINTERS
1030 * 3DSTATE_VIEWPORT_STATE_POINTERS
1031 * MEDIA_STATE_POINTERS
1033 * Those are always reissued following SBA updates anyway (new
1034 * batch time), except in the case of the program cache BO
1035 * changing. Having a separate state flag makes the sequence more
1039 brw
->ctx
.NewDriverState
|= BRW_NEW_STATE_BASE_ADDRESS
;
1040 brw
->batch
.state_base_address_emitted
= true;