src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "intel_regions.h"
  37
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40 #include "brw_defines.h"
  41
  42 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  43 static void upload_drawing_rect(struct brw_context *brw)
  44 {
  45    struct intel_context *intel = &brw->intel;
  46    struct gl_context *ctx = &intel->ctx;
  47
  48    BEGIN_BATCH(4);
  49    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
  50    OUT_BATCH(0); /* xmin, ymin */
  51    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  52             ((ctx->DrawBuffer->Height - 1) << 16));
  53    OUT_BATCH(0);
  54    ADVANCE_BATCH();
  55 }
  56
  57 const struct brw_tracked_state brw_drawing_rect = {
  58    .dirty = {
  59       .mesa = _NEW_BUFFERS,
  60       .brw = BRW_NEW_CONTEXT,
  61       .cache = 0
  62    },
  63    .emit = upload_drawing_rect
  64 };
  65
  66 /**
  67  * Upload the binding table pointers, which point each stage's array of surface
  68  * state pointers.
  69  *
  70  * The binding table pointers are relative to the surface state base address,
  71  * which points at the batchbuffer containing the streamed batch state.
  72  */
  73 static void upload_binding_table_pointers(struct brw_context *brw)
  74 {
  75    struct intel_context *intel = &brw->intel;
  76
  77    BEGIN_BATCH(6);
  78    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
  79    OUT_BATCH(brw->vs.bind_bo_offset);
  80    OUT_BATCH(0); /* gs */
  81    OUT_BATCH(0); /* clip */
  82    OUT_BATCH(0); /* sf */
  83    OUT_BATCH(brw->wm.bind_bo_offset);
  84    ADVANCE_BATCH();
  85 }
  86
  87 const struct brw_tracked_state brw_binding_table_pointers = {
  88    .dirty = {
  89       .mesa = 0,
  90       .brw = (BRW_NEW_BATCH |
  91               BRW_NEW_STATE_BASE_ADDRESS |
  92               BRW_NEW_VS_BINDING_TABLE |
  93               BRW_NEW_GS_BINDING_TABLE |
  94               BRW_NEW_PS_BINDING_TABLE),
  95       .cache = 0,
  96    },
  97    .emit = upload_binding_table_pointers,
  98 };
  99
 100 /**
 101  * Upload the binding table pointers, which point each stage's array of surface
 102  * state pointers.
 103  *
 104  * The binding table pointers are relative to the surface state base address,
 105  * which points at the batchbuffer containing the streamed batch state.
 106  */
 107 static void upload_gen6_binding_table_pointers(struct brw_context *brw)
 108 {
 109    struct intel_context *intel = &brw->intel;
 110
 111    BEGIN_BATCH(4);
 112    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 113              GEN6_BINDING_TABLE_MODIFY_VS |
 114              GEN6_BINDING_TABLE_MODIFY_GS |
 115              GEN6_BINDING_TABLE_MODIFY_PS |
 116              (4 - 2));
 117    OUT_BATCH(brw->vs.bind_bo_offset); /* vs */
 118    OUT_BATCH(0); /* gs */
 119    OUT_BATCH(brw->wm.bind_bo_offset); /* wm/ps */
 120    ADVANCE_BATCH();
 121 }
 122
 123 const struct brw_tracked_state gen6_binding_table_pointers = {
 124    .dirty = {
 125       .mesa = 0,
 126       .brw = (BRW_NEW_BATCH |
 127               BRW_NEW_STATE_BASE_ADDRESS |
 128               BRW_NEW_VS_BINDING_TABLE |
 129               BRW_NEW_GS_BINDING_TABLE |
 130               BRW_NEW_PS_BINDING_TABLE),
 131       .cache = 0,
 132    },
 133    .emit = upload_gen6_binding_table_pointers,
 134 };
 135
 136 /**
 137  * Upload pointers to the per-stage state.
 138  *
 139  * The state pointers in this packet are all relative to the general state
 140  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 141  */
 142 static void upload_pipelined_state_pointers(struct brw_context *brw )
 143 {
 144    struct intel_context *intel = &brw->intel;
 145
 146    if (intel->gen == 5) {
 147       /* Need to flush before changing clip max threads for errata. */
 148       BEGIN_BATCH(1);
 149       OUT_BATCH(MI_FLUSH);
 150       ADVANCE_BATCH();
 151    }
 152
 153    BEGIN_BATCH(7);
 154    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
 155    OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 156              brw->vs.state_offset);
 157    if (brw->gs.prog_active)
 158       OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 159                 brw->gs.state_offset | 1);
 160    else
 161       OUT_BATCH(0);
 162    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 163              brw->clip.state_offset | 1);
 164    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 165              brw->sf.state_offset);
 166    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 167              brw->wm.state_offset);
 168    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 169              brw->cc.state_offset);
 170    ADVANCE_BATCH();
 171
 172    brw->state.dirty.brw |= BRW_NEW_PSP;
 173 }
 174
 175 static void upload_psp_urb_cbs(struct brw_context *brw )
 176 {
 177    upload_pipelined_state_pointers(brw);
 178    brw_upload_urb_fence(brw);
 179    brw_upload_cs_urb_state(brw);
 180 }
 181
 182 const struct brw_tracked_state brw_psp_urb_cbs = {
 183    .dirty = {
 184       .mesa = 0,
 185       .brw = (BRW_NEW_URB_FENCE |
 186               BRW_NEW_BATCH |
 187               BRW_NEW_STATE_BASE_ADDRESS),
 188       .cache = (CACHE_NEW_VS_UNIT |
 189                 CACHE_NEW_GS_UNIT |
 190                 CACHE_NEW_GS_PROG |
 191                 CACHE_NEW_CLIP_UNIT |
 192                 CACHE_NEW_SF_UNIT |
 193                 CACHE_NEW_WM_UNIT |
 194                 CACHE_NEW_CC_UNIT)
 195    },
 196    .emit = upload_psp_urb_cbs,
 197 };
 198
 199 static void prepare_depthbuffer(struct brw_context *brw)
 200 {
 201    struct intel_context *intel = &brw->intel;
 202    struct gl_context *ctx = &intel->ctx;
 203    struct gl_framebuffer *fb = ctx->DrawBuffer;
 204    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 205    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 206
 207    if (drb)
 208       brw_add_validated_bo(brw, drb->region->bo);
 209    if (drb && drb->hiz_region)
 210       brw_add_validated_bo(brw, drb->hiz_region->bo);
 211    if (srb)
 212       brw_add_validated_bo(brw, srb->region->bo);
 213 }
 214
 215 static void emit_depthbuffer(struct brw_context *brw)
 216 {
 217    struct intel_context *intel = &brw->intel;
 218    struct gl_context *ctx = &intel->ctx;
 219    struct gl_framebuffer *fb = ctx->DrawBuffer;
 220    /* _NEW_BUFFERS */
 221    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 222    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 223    struct intel_region *hiz_region = depth_irb ? depth_irb->hiz_region : NULL;
 224    unsigned int len;
 225
 226    /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
 227     * non-pipelined state that will need the PIPE_CONTROL workaround.
 228     */
 229    if (intel->gen == 6) {
 230       intel_emit_post_sync_nonzero_flush(intel);
 231       intel_emit_depth_stall_flushes(intel);
 232    }
 233
 234    /*
 235     * If either depth or stencil buffer has packed depth/stencil format,
 236     * then don't use separate stencil. Emit only a depth buffer.
 237     */
 238    if (depth_irb && depth_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 239       stencil_irb = NULL;
 240    } else if (!depth_irb && stencil_irb
 241               && stencil_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 242       depth_irb = stencil_irb;
 243       stencil_irb = NULL;
 244    }
 245
 246    if (intel->gen >= 6)
 247       len = 7;
 248    else if (intel->is_g4x || intel->gen == 5)
 249       len = 6;
 250    else
 251       len = 5;
 252
 253    if (!depth_irb && !stencil_irb) {
 254       BEGIN_BATCH(len);
 255       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 256       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 257                 (BRW_SURFACE_NULL << 29));
 258       OUT_BATCH(0);
 259       OUT_BATCH(0);
 260       OUT_BATCH(0);
 261
 262       if (intel->is_g4x || intel->gen >= 5)
 263          OUT_BATCH(0);
 264
 265       if (intel->gen >= 6)
 266          OUT_BATCH(0);
 267
 268       ADVANCE_BATCH();
 269
 270    } else if (!depth_irb && stencil_irb) {
 271       /*
 272        * There exists a separate stencil buffer but no depth buffer.
 273        *
 274        * The stencil buffer inherits most of its fields from
 275        * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
 276        * height.
 277        *
 278        * Since the stencil buffer has quirky pitch requirements, its region
 279        * was allocated with half height and double cpp. So we need
 280        * a multiplier of 2 to obtain the surface's real height.
 281        *
 282        * Enable the hiz bit because it and the separate stencil bit must have
 283        * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
 284        * 1.21 "Separate Stencil Enable":
 285        *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
 286        *     Enable must also be enabled.
 287        *
 288        *     [DevGT]: This field must be set to the same value (enabled or
 289        *     disabled) as Hierarchical Depth Buffer Enable
 290        */
 291       assert(intel->has_separate_stencil);
 292       assert(stencil_irb->Base.Format == MESA_FORMAT_S8);
 293
 294       BEGIN_BATCH(len);
 295       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 296       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 297                 (1 << 21) | /* separate stencil enable */
 298                 (1 << 22) | /* hiz enable */
 299                 (BRW_TILEWALK_YMAJOR << 26) |
 300                 (BRW_SURFACE_2D << 29));
 301       OUT_BATCH(0);
 302       OUT_BATCH(((stencil_irb->region->width - 1) << 6) |
 303                  (2 * stencil_irb->region->height - 1) << 19);
 304       OUT_BATCH(0);
 305       OUT_BATCH(0);
 306
 307       if (intel->gen >= 6)
 308          OUT_BATCH(0);
 309
 310       ADVANCE_BATCH();
 311
 312    } else {
 313       struct intel_region *region = depth_irb->region;
 314       unsigned int format;
 315       uint32_t tile_x, tile_y, offset;
 316
 317       /* If using separate stencil, hiz must be enabled. */
 318       assert(!stencil_irb || hiz_region);
 319
 320       switch (region->cpp) {
 321       case 2:
 322          format = BRW_DEPTHFORMAT_D16_UNORM;
 323          break;
 324       case 4:
 325          if (intel->depth_buffer_is_float)
 326             format = BRW_DEPTHFORMAT_D32_FLOAT;
 327          else if (hiz_region)
 328             format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 329          else
 330             format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 331          break;
 332       default:
 333          assert(0);
 334          return;
 335       }
 336
 337       offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y);
 338
 339       assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
 340       assert(!hiz_region || region->tiling == I915_TILING_Y);
 341
 342       BEGIN_BATCH(len);
 343       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 344       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 345                 (format << 18) |
 346                 ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */
 347                 ((hiz_region ? 1 : 0) << 22) | /* hiz enable */
 348                 (BRW_TILEWALK_YMAJOR << 26) |
 349                 ((region->tiling != I915_TILING_NONE) << 27) |
 350                 (BRW_SURFACE_2D << 29));
 351       OUT_RELOC(region->bo,
 352                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 353                 offset);
 354       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 355                 ((region->width - 1) << 6) |
 356                 ((region->height - 1) << 19));
 357       OUT_BATCH(0);
 358
 359       if (intel->is_g4x || intel->gen >= 5)
 360          OUT_BATCH(tile_x | (tile_y << 16));
 361       else
 362          assert(tile_x == 0 && tile_y == 0);
 363
 364       if (intel->gen >= 6)
 365          OUT_BATCH(0);
 366
 367       ADVANCE_BATCH();
 368    }
 369
 370    if (hiz_region || stencil_irb) {
 371       /*
 372        * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
 373        * stencil enable' and 'hiz enable' bits were set. Therefore we must
 374        * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
 375        * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
 376        * failure to do so causes hangs on gen5 and a stall on gen6.
 377        */
 378
 379       /* Emit hiz buffer. */
 380       if (hiz_region) {
 381          BEGIN_BATCH(3);
 382          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 383          OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 384          OUT_RELOC(hiz_region->bo,
 385                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 386                    0);
 387          ADVANCE_BATCH();
 388       } else {
 389          BEGIN_BATCH(3);
 390          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 391          OUT_BATCH(0);
 392          OUT_BATCH(0);
 393          ADVANCE_BATCH();
 394       }
 395
 396       /* Emit stencil buffer. */
 397       if (stencil_irb) {
 398          BEGIN_BATCH(3);
 399          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 400          OUT_BATCH(stencil_irb->region->pitch * stencil_irb->region->cpp - 1);
 401          OUT_RELOC(stencil_irb->region->bo,
 402                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 403                    0);
 404          ADVANCE_BATCH();
 405       } else {
 406          BEGIN_BATCH(3);
 407          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 408          OUT_BATCH(0);
 409          OUT_BATCH(0);
 410          ADVANCE_BATCH();
 411       }
 412    }
 413
 414    /*
 415     * On Gen >= 6, emit clear params for safety. If using hiz, then clear
 416     * params must be emitted.
 417     *
 418     * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
 419     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
 420     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 421     */
 422    if (intel->gen >= 6 || hiz_region) {
 423       if (intel->gen == 6)
 424          intel_emit_post_sync_nonzero_flush(intel);
 425
 426       BEGIN_BATCH(2);
 427       OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
 428       OUT_BATCH(0);
 429       ADVANCE_BATCH();
 430    }
 431 }
 432
 433 const struct brw_tracked_state brw_depthbuffer = {
 434    .dirty = {
 435       .mesa = _NEW_BUFFERS,
 436       .brw = BRW_NEW_BATCH,
 437       .cache = 0,
 438    },
 439    .prepare = prepare_depthbuffer,
 440    .emit = emit_depthbuffer,
 441 };
 442
 443
 444
 445 /***********************************************************************
 446  * Polygon stipple packet
 447  */
 448
 449 static void upload_polygon_stipple(struct brw_context *brw)
 450 {
 451    struct intel_context *intel = &brw->intel;
 452    struct gl_context *ctx = &brw->intel.ctx;
 453    GLuint i;
 454
 455    /* _NEW_POLYGON */
 456    if (!ctx->Polygon.StippleFlag)
 457       return;
 458
 459    if (intel->gen == 6)
 460       intel_emit_post_sync_nonzero_flush(intel);
 461
 462    BEGIN_BATCH(33);
 463    OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
 464
 465    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 466     * row first.  If we're rendering to a window (i.e. the
 467     * default frame buffer object, 0), then we need to invert
 468     * it to match our pixel layout.  But if we're rendering
 469     * to a FBO (i.e. any named frame buffer object), we *don't*
 470     * need to invert - we already match the layout.
 471     */
 472    if (ctx->DrawBuffer->Name == 0) {
 473       for (i = 0; i < 32; i++)
 474           OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
 475    }
 476    else {
 477       for (i = 0; i < 32; i++)
 478          OUT_BATCH(ctx->PolygonStipple[i]);
 479    }
 480    CACHED_BATCH();
 481 }
 482
 483 const struct brw_tracked_state brw_polygon_stipple = {
 484    .dirty = {
 485       .mesa = (_NEW_POLYGONSTIPPLE |
 486                _NEW_POLYGON),
 487       .brw = BRW_NEW_CONTEXT,
 488       .cache = 0
 489    },
 490    .emit = upload_polygon_stipple
 491 };
 492
 493
 494 /***********************************************************************
 495  * Polygon stipple offset packet
 496  */
 497
 498 static void upload_polygon_stipple_offset(struct brw_context *brw)
 499 {
 500    struct intel_context *intel = &brw->intel;
 501    struct gl_context *ctx = &brw->intel.ctx;
 502
 503    /* _NEW_POLYGON */
 504    if (!ctx->Polygon.StippleFlag)
 505       return;
 506
 507    if (intel->gen == 6)
 508       intel_emit_post_sync_nonzero_flush(intel);
 509
 510    BEGIN_BATCH(2);
 511    OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
 512
 513    /* _NEW_BUFFERS
 514     *
 515     * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 516     * we have to invert the Y axis in order to match the OpenGL
 517     * pixel coordinate system, and our offset must be matched
 518     * to the window position.  If we're drawing to a FBO
 519     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 520     * system works just fine, and there's no window system to
 521     * worry about.
 522     */
 523    if (brw->intel.ctx.DrawBuffer->Name == 0)
 524       OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
 525    else
 526       OUT_BATCH(0);
 527    CACHED_BATCH();
 528 }
 529
 530 const struct brw_tracked_state brw_polygon_stipple_offset = {
 531    .dirty = {
 532       .mesa = (_NEW_BUFFERS |
 533                _NEW_POLYGON),
 534       .brw = BRW_NEW_CONTEXT,
 535       .cache = 0
 536    },
 537    .emit = upload_polygon_stipple_offset
 538 };
 539
 540 /**********************************************************************
 541  * AA Line parameters
 542  */
 543 static void upload_aa_line_parameters(struct brw_context *brw)
 544 {
 545    struct intel_context *intel = &brw->intel;
 546    struct gl_context *ctx = &brw->intel.ctx;
 547
 548    if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
 549       return;
 550
 551    if (intel->gen == 6)
 552       intel_emit_post_sync_nonzero_flush(intel);
 553
 554    OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
 555    /* use legacy aa line coverage computation */
 556    OUT_BATCH(0);
 557    OUT_BATCH(0);
 558    CACHED_BATCH();
 559 }
 560
 561 const struct brw_tracked_state brw_aa_line_parameters = {
 562    .dirty = {
 563       .mesa = _NEW_LINE,
 564       .brw = BRW_NEW_CONTEXT,
 565       .cache = 0
 566    },
 567    .emit = upload_aa_line_parameters
 568 };
 569
 570 /***********************************************************************
 571  * Line stipple packet
 572  */
 573
 574 static void upload_line_stipple(struct brw_context *brw)
 575 {
 576    struct intel_context *intel = &brw->intel;
 577    struct gl_context *ctx = &brw->intel.ctx;
 578    GLfloat tmp;
 579    GLint tmpi;
 580
 581    if (!ctx->Line.StippleFlag)
 582       return;
 583
 584    if (intel->gen == 6)
 585       intel_emit_post_sync_nonzero_flush(intel);
 586
 587    BEGIN_BATCH(3);
 588    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
 589    OUT_BATCH(ctx->Line.StipplePattern);
 590    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 591    tmpi = tmp * (1<<13);
 592    OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
 593    CACHED_BATCH();
 594 }
 595
 596 const struct brw_tracked_state brw_line_stipple = {
 597    .dirty = {
 598       .mesa = _NEW_LINE,
 599       .brw = BRW_NEW_CONTEXT,
 600       .cache = 0
 601    },
 602    .emit = upload_line_stipple
 603 };
 604
 605
 606 /***********************************************************************
 607  * Misc invarient state packets
 608  */
 609
 610 static void upload_invarient_state( struct brw_context *brw )
 611 {
 612    struct intel_context *intel = &brw->intel;
 613
 614    /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
 615    if (intel->gen == 6)
 616       intel_emit_post_sync_nonzero_flush(intel);
 617
 618    /* Select the 3D pipeline (as opposed to media) */
 619    BEGIN_BATCH(1);
 620    OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0);
 621    ADVANCE_BATCH();
 622
 623    if (intel->gen < 6) {
 624       /* Disable depth offset clamping. */
 625       BEGIN_BATCH(2);
 626       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
 627       OUT_BATCH_F(0.0);
 628       ADVANCE_BATCH();
 629    }
 630
 631    if (intel->gen >= 6) {
 632       int i;
 633       int len = intel->gen >= 7 ? 4 : 3;
 634
 635       BEGIN_BATCH(len);
 636       OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
 637       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
 638                 MS_NUMSAMPLES_1);
 639       OUT_BATCH(0); /* positions for 4/8-sample */
 640       if (intel->gen >= 7)
 641          OUT_BATCH(0);
 642       ADVANCE_BATCH();
 643
 644       BEGIN_BATCH(2);
 645       OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
 646       OUT_BATCH(1);
 647       ADVANCE_BATCH();
 648
 649       if (intel->gen < 7) {
 650          for (i = 0; i < 4; i++) {
 651             BEGIN_BATCH(4);
 652             OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
 653             OUT_BATCH(i << SVB_INDEX_SHIFT);
 654             OUT_BATCH(0);
 655             OUT_BATCH(0xffffffff);
 656             ADVANCE_BATCH();
 657          }
 658       }
 659    }
 660
 661    BEGIN_BATCH(2);
 662    OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2));
 663    OUT_BATCH(0);
 664    ADVANCE_BATCH();
 665
 666    BEGIN_BATCH(1);
 667    OUT_BATCH(brw->CMD_VF_STATISTICS << 16 |
 668              (unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0));
 669    ADVANCE_BATCH();
 670 }
 671
 672 const struct brw_tracked_state brw_invarient_state = {
 673    .dirty = {
 674       .mesa = 0,
 675       .brw = BRW_NEW_CONTEXT,
 676       .cache = 0
 677    },
 678    .emit = upload_invarient_state
 679 };
 680
 681 /**
 682  * Define the base addresses which some state is referenced from.
 683  *
 684  * This allows us to avoid having to emit relocations for the objects,
 685  * and is actually required for binding table pointers on gen6.
 686  *
 687  * Surface state base address covers binding table pointers and
 688  * surface state objects, but not the surfaces that the surface state
 689  * objects point to.
 690  */
 691 static void upload_state_base_address( struct brw_context *brw )
 692 {
 693    struct intel_context *intel = &brw->intel;
 694
 695    /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
 696     * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
 697     * programmed prior to STATE_BASE_ADDRESS.
 698     *
 699     * However, given that the instruction SBA (general state base
 700     * address) on this chipset is always set to 0 across X and GL,
 701     * maybe this isn't required for us in particular.
 702     */
 703
 704    if (intel->gen >= 6) {
 705       if (intel->gen == 6)
 706          intel_emit_post_sync_nonzero_flush(intel);
 707
 708        BEGIN_BATCH(10);
 709        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
 710        /* General state base address: stateless DP read/write requests */
 711        OUT_BATCH(1);
 712        /* Surface state base address:
 713         * BINDING_TABLE_STATE
 714         * SURFACE_STATE
 715         */
 716        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
 717         /* Dynamic state base address:
 718          * SAMPLER_STATE
 719          * SAMPLER_BORDER_COLOR_STATE
 720          * CLIP, SF, WM/CC viewport state
 721          * COLOR_CALC_STATE
 722          * DEPTH_STENCIL_STATE
 723          * BLEND_STATE
 724          * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
 725          * Disable is clear, which we rely on)
 726          */
 727        OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
 728                                    I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
 729
 730        OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
 731        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 732                  1); /* Instruction base address: shader kernels (incl. SIP) */
 733
 734        OUT_BATCH(1); /* General state upper bound */
 735        OUT_BATCH(1); /* Dynamic state upper bound */
 736        OUT_BATCH(1); /* Indirect object upper bound */
 737        OUT_BATCH(1); /* Instruction access upper bound */
 738        ADVANCE_BATCH();
 739    } else if (intel->gen == 5) {
 740        BEGIN_BATCH(8);
 741        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 742        OUT_BATCH(1); /* General state base address */
 743        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 744                  1); /* Surface state base address */
 745        OUT_BATCH(1); /* Indirect object base address */
 746        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 747                  1); /* Instruction base address */
 748        OUT_BATCH(1); /* General state upper bound */
 749        OUT_BATCH(1); /* Indirect object upper bound */
 750        OUT_BATCH(1); /* Instruction access upper bound */
 751        ADVANCE_BATCH();
 752    } else {
 753        BEGIN_BATCH(6);
 754        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 755        OUT_BATCH(1); /* General state base address */
 756        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 757                  1); /* Surface state base address */
 758        OUT_BATCH(1); /* Indirect object base address */
 759        OUT_BATCH(1); /* General state upper bound */
 760        OUT_BATCH(1); /* Indirect object upper bound */
 761        ADVANCE_BATCH();
 762    }
 763
 764    /* According to section 3.6.1 of VOL1 of the 965 PRM,
 765     * STATE_BASE_ADDRESS updates require a reissue of:
 766     *
 767     * 3DSTATE_PIPELINE_POINTERS
 768     * 3DSTATE_BINDING_TABLE_POINTERS
 769     * MEDIA_STATE_POINTERS
 770     *
 771     * and this continues through Ironlake.  The Sandy Bridge PRM, vol
 772     * 1 part 1 says that the folowing packets must be reissued:
 773     *
 774     * 3DSTATE_CC_POINTERS
 775     * 3DSTATE_BINDING_TABLE_POINTERS
 776     * 3DSTATE_SAMPLER_STATE_POINTERS
 777     * 3DSTATE_VIEWPORT_STATE_POINTERS
 778     * MEDIA_STATE_POINTERS
 779     *
 780     * Those are always reissued following SBA updates anyway (new
 781     * batch time), except in the case of the program cache BO
 782     * changing.  Having a separate state flag makes the sequence more
 783     * obvious.
 784     */
 785
 786    brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
 787 }
 788
 789 const struct brw_tracked_state brw_state_base_address = {
 790    .dirty = {
 791       .mesa = 0,
 792       .brw = (BRW_NEW_BATCH |
 793               BRW_NEW_PROGRAM_CACHE),
 794       .cache = 0,
 795    },
 796    .emit = upload_state_base_address
 797 };