2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
37 #include "intel_regions.h"
39 #include "brw_context.h"
40 #include "brw_state.h"
41 #include "brw_defines.h"
43 /* Constant single cliprect for framebuffer object or DRI2 drawing */
44 static void upload_drawing_rect(struct brw_context
*brw
)
46 struct intel_context
*intel
= &brw
->intel
;
47 struct gl_context
*ctx
= &intel
->ctx
;
50 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
51 OUT_BATCH(0); /* xmin, ymin */
52 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
53 ((ctx
->DrawBuffer
->Height
- 1) << 16));
58 const struct brw_tracked_state brw_drawing_rect
= {
61 .brw
= BRW_NEW_CONTEXT
,
64 .emit
= upload_drawing_rect
68 * Upload the binding table pointers, which point each stage's array of surface
71 * The binding table pointers are relative to the surface state base address,
72 * which points at the batchbuffer containing the streamed batch state.
74 static void upload_binding_table_pointers(struct brw_context
*brw
)
76 struct intel_context
*intel
= &brw
->intel
;
79 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 | (6 - 2));
80 OUT_BATCH(brw
->bind
.bo_offset
);
81 OUT_BATCH(0); /* gs */
82 OUT_BATCH(0); /* clip */
83 OUT_BATCH(0); /* sf */
84 OUT_BATCH(brw
->bind
.bo_offset
);
88 const struct brw_tracked_state brw_binding_table_pointers
= {
91 .brw
= (BRW_NEW_BATCH
|
92 BRW_NEW_STATE_BASE_ADDRESS
|
93 BRW_NEW_VS_BINDING_TABLE
|
94 BRW_NEW_GS_BINDING_TABLE
|
95 BRW_NEW_PS_BINDING_TABLE
),
98 .emit
= upload_binding_table_pointers
,
102 * Upload the binding table pointers, which point each stage's array of surface
105 * The binding table pointers are relative to the surface state base address,
106 * which points at the batchbuffer containing the streamed batch state.
108 static void upload_gen6_binding_table_pointers(struct brw_context
*brw
)
110 struct intel_context
*intel
= &brw
->intel
;
113 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
114 GEN6_BINDING_TABLE_MODIFY_VS
|
115 GEN6_BINDING_TABLE_MODIFY_GS
|
116 GEN6_BINDING_TABLE_MODIFY_PS
|
118 OUT_BATCH(brw
->bind
.bo_offset
); /* vs */
119 OUT_BATCH(brw
->bind
.bo_offset
); /* gs */
120 OUT_BATCH(brw
->bind
.bo_offset
); /* wm/ps */
124 const struct brw_tracked_state gen6_binding_table_pointers
= {
127 .brw
= (BRW_NEW_BATCH
|
128 BRW_NEW_STATE_BASE_ADDRESS
|
129 BRW_NEW_VS_BINDING_TABLE
|
130 BRW_NEW_GS_BINDING_TABLE
|
131 BRW_NEW_PS_BINDING_TABLE
),
134 .emit
= upload_gen6_binding_table_pointers
,
138 * Upload pointers to the per-stage state.
140 * The state pointers in this packet are all relative to the general state
141 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
143 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
145 struct intel_context
*intel
= &brw
->intel
;
147 if (intel
->gen
== 5) {
148 /* Need to flush before changing clip max threads for errata. */
155 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
156 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
157 brw
->vs
.state_offset
);
158 if (brw
->gs
.prog_active
)
159 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
160 brw
->gs
.state_offset
| 1);
163 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
164 brw
->clip
.state_offset
| 1);
165 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
166 brw
->sf
.state_offset
);
167 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
168 brw
->wm
.state_offset
);
169 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
170 brw
->cc
.state_offset
);
173 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
176 static void upload_psp_urb_cbs(struct brw_context
*brw
)
178 upload_pipelined_state_pointers(brw
);
179 brw_upload_urb_fence(brw
);
180 brw_upload_cs_urb_state(brw
);
183 const struct brw_tracked_state brw_psp_urb_cbs
= {
186 .brw
= (BRW_NEW_URB_FENCE
|
188 BRW_NEW_STATE_BASE_ADDRESS
),
189 .cache
= (CACHE_NEW_VS_UNIT
|
192 CACHE_NEW_CLIP_UNIT
|
197 .emit
= upload_psp_urb_cbs
,
201 brw_depthbuffer_format(struct brw_context
*brw
)
203 struct intel_context
*intel
= &brw
->intel
;
204 struct gl_context
*ctx
= &intel
->ctx
;
205 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
206 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
207 struct intel_renderbuffer
*srb
;
210 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
211 !srb
->mt
->stencil_mt
&&
212 (intel_rb_format(srb
) == MESA_FORMAT_S8_Z24
||
213 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_X24S8
)) {
218 return BRW_DEPTHFORMAT_D32_FLOAT
;
220 switch (drb
->mt
->format
) {
221 case MESA_FORMAT_Z16
:
222 return BRW_DEPTHFORMAT_D16_UNORM
;
223 case MESA_FORMAT_Z32_FLOAT
:
224 return BRW_DEPTHFORMAT_D32_FLOAT
;
225 case MESA_FORMAT_X8_Z24
:
226 if (intel
->gen
>= 6) {
227 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
229 /* Use D24_UNORM_S8, not D24_UNORM_X8.
231 * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
232 * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
233 * 3DSTATE_DEPTH_BUFFER.Surface_Format).
235 * However, on Gen5, D24_UNORM_X8 may be used only if separate
236 * stencil is enabled, and we never enable it. From the Ironlake PRM,
237 * same section as above, Bit 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Buffer_Enable:
238 * If this field is disabled, the Surface Format of the depth
239 * buffer cannot be D24_UNORM_X8_UINT.
241 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
243 case MESA_FORMAT_S8_Z24
:
244 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
245 case MESA_FORMAT_Z32_FLOAT_X24S8
:
246 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT
;
248 _mesa_problem(ctx
, "Unexpected depth format %s\n",
249 _mesa_get_format_name(intel_rb_format(drb
)));
250 return BRW_DEPTHFORMAT_D16_UNORM
;
254 static void emit_depthbuffer(struct brw_context
*brw
)
256 struct intel_context
*intel
= &brw
->intel
;
257 struct gl_context
*ctx
= &intel
->ctx
;
258 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
260 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
261 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
262 struct intel_mipmap_tree
*stencil_mt
= NULL
;
263 struct intel_region
*hiz_region
= NULL
;
265 bool separate_stencil
= false;
269 depth_irb
->mt
->hiz_mt
) {
270 hiz_region
= depth_irb
->mt
->hiz_mt
->region
;
273 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
274 * non-pipelined state that will need the PIPE_CONTROL workaround.
276 if (intel
->gen
== 6) {
277 intel_emit_post_sync_nonzero_flush(intel
);
278 intel_emit_depth_stall_flushes(intel
);
281 /* Find the real separate stencil mt if present. */
283 stencil_mt
= stencil_irb
->mt
;
284 if (stencil_mt
->stencil_mt
)
285 stencil_mt
= stencil_mt
->stencil_mt
;
287 if (stencil_mt
->format
== MESA_FORMAT_S8
)
288 separate_stencil
= true;
291 /* If there's a packed depth/stencil bound to stencil only, we need to
292 * emit the packed depth/stencil buffer packet.
294 if (!depth_irb
&& stencil_irb
&& !separate_stencil
)
295 depth_irb
= stencil_irb
;
299 else if (intel
->is_g4x
|| intel
->gen
== 5)
304 if (!depth_irb
&& !separate_stencil
) {
306 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
307 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
308 (BRW_SURFACE_NULL
<< 29));
313 if (intel
->is_g4x
|| intel
->gen
>= 5)
321 } else if (!depth_irb
&& separate_stencil
) {
323 * There exists a separate stencil buffer but no depth buffer.
325 * The stencil buffer inherits most of its fields from
326 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
329 * Since the stencil buffer has quirky pitch requirements, its region
330 * was allocated with half height and double cpp. So we need
331 * a multiplier of 2 to obtain the surface's real height.
333 * Enable the hiz bit because it and the separate stencil bit must have
334 * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
335 * 1.21 "Separate Stencil Enable":
336 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
337 * Enable must also be enabled.
339 * [DevGT]: This field must be set to the same value (enabled or
340 * disabled) as Hierarchical Depth Buffer Enable
342 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
343 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
344 * [DevGT+]: This field must be set to TRUE.
346 assert(intel
->has_separate_stencil
);
349 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
350 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
351 (1 << 21) | /* separate stencil enable */
352 (1 << 22) | /* hiz enable */
353 (BRW_TILEWALK_YMAJOR
<< 26) |
354 (1 << 27) | /* tiled surface */
355 (BRW_SURFACE_2D
<< 29));
357 OUT_BATCH(((stencil_irb
->Base
.Width
- 1) << 6) |
358 (stencil_irb
->Base
.Height
- 1) << 19);
368 struct intel_region
*region
= depth_irb
->mt
->region
;
369 uint32_t tile_x
, tile_y
, offset
;
371 /* If using separate stencil, hiz must be enabled. */
372 assert(!separate_stencil
|| hiz_region
);
374 offset
= intel_renderbuffer_tile_offsets(depth_irb
, &tile_x
, &tile_y
);
376 assert(intel
->gen
< 6 || region
->tiling
== I915_TILING_Y
);
377 assert(!hiz_region
|| region
->tiling
== I915_TILING_Y
);
380 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
381 OUT_BATCH(((region
->pitch
* region
->cpp
) - 1) |
382 (brw_depthbuffer_format(brw
) << 18) |
383 ((hiz_region
? 1 : 0) << 21) | /* separate stencil enable */
384 ((hiz_region
? 1 : 0) << 22) | /* hiz enable */
385 (BRW_TILEWALK_YMAJOR
<< 26) |
386 ((region
->tiling
!= I915_TILING_NONE
) << 27) |
387 (BRW_SURFACE_2D
<< 29));
388 OUT_RELOC(region
->bo
,
389 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
391 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1) |
392 (((depth_irb
->Base
.Width
+ tile_x
)- 1) << 6) |
393 (((depth_irb
->Base
.Height
+ tile_y
) - 1) << 19));
396 if (intel
->is_g4x
|| intel
->gen
>= 5)
397 OUT_BATCH(tile_x
| (tile_y
<< 16));
399 assert(tile_x
== 0 && tile_y
== 0);
407 if (hiz_region
|| separate_stencil
) {
409 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
410 * stencil enable' and 'hiz enable' bits were set. Therefore we must
411 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
412 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
413 * failure to do so causes hangs on gen5 and a stall on gen6.
416 /* Emit hiz buffer. */
419 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
420 OUT_BATCH(hiz_region
->pitch
* hiz_region
->cpp
- 1);
421 OUT_RELOC(hiz_region
->bo
,
422 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
427 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
433 /* Emit stencil buffer. */
434 if (separate_stencil
) {
435 struct intel_region
*region
= stencil_mt
->region
;
437 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
438 OUT_BATCH(region
->pitch
* region
->cpp
- 1);
439 OUT_RELOC(region
->bo
,
440 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
445 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
453 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
454 * params must be emitted.
456 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
457 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
458 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
460 if (intel
->gen
>= 6 || hiz_region
) {
462 intel_emit_post_sync_nonzero_flush(intel
);
465 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 | (2 - 2));
471 const struct brw_tracked_state brw_depthbuffer
= {
473 .mesa
= _NEW_BUFFERS
,
474 .brw
= BRW_NEW_BATCH
,
477 .emit
= emit_depthbuffer
,
482 /***********************************************************************
483 * Polygon stipple packet
486 static void upload_polygon_stipple(struct brw_context
*brw
)
488 struct intel_context
*intel
= &brw
->intel
;
489 struct gl_context
*ctx
= &brw
->intel
.ctx
;
493 if (!ctx
->Polygon
.StippleFlag
)
497 intel_emit_post_sync_nonzero_flush(intel
);
500 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
502 /* Polygon stipple is provided in OpenGL order, i.e. bottom
503 * row first. If we're rendering to a window (i.e. the
504 * default frame buffer object, 0), then we need to invert
505 * it to match our pixel layout. But if we're rendering
506 * to a FBO (i.e. any named frame buffer object), we *don't*
507 * need to invert - we already match the layout.
509 if (ctx
->DrawBuffer
->Name
== 0) {
510 for (i
= 0; i
< 32; i
++)
511 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
514 for (i
= 0; i
< 32; i
++)
515 OUT_BATCH(ctx
->PolygonStipple
[i
]);
520 const struct brw_tracked_state brw_polygon_stipple
= {
522 .mesa
= (_NEW_POLYGONSTIPPLE
|
524 .brw
= BRW_NEW_CONTEXT
,
527 .emit
= upload_polygon_stipple
531 /***********************************************************************
532 * Polygon stipple offset packet
535 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
537 struct intel_context
*intel
= &brw
->intel
;
538 struct gl_context
*ctx
= &brw
->intel
.ctx
;
541 if (!ctx
->Polygon
.StippleFlag
)
545 intel_emit_post_sync_nonzero_flush(intel
);
548 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
552 * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
553 * we have to invert the Y axis in order to match the OpenGL
554 * pixel coordinate system, and our offset must be matched
555 * to the window position. If we're drawing to a FBO
556 * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
557 * system works just fine, and there's no window system to
560 if (brw
->intel
.ctx
.DrawBuffer
->Name
== 0)
561 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
567 const struct brw_tracked_state brw_polygon_stipple_offset
= {
569 .mesa
= (_NEW_BUFFERS
|
571 .brw
= BRW_NEW_CONTEXT
,
574 .emit
= upload_polygon_stipple_offset
577 /**********************************************************************
580 static void upload_aa_line_parameters(struct brw_context
*brw
)
582 struct intel_context
*intel
= &brw
->intel
;
583 struct gl_context
*ctx
= &brw
->intel
.ctx
;
585 if (!ctx
->Line
.SmoothFlag
|| !brw
->has_aa_line_parameters
)
589 intel_emit_post_sync_nonzero_flush(intel
);
591 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
592 /* use legacy aa line coverage computation */
598 const struct brw_tracked_state brw_aa_line_parameters
= {
601 .brw
= BRW_NEW_CONTEXT
,
604 .emit
= upload_aa_line_parameters
607 /***********************************************************************
608 * Line stipple packet
611 static void upload_line_stipple(struct brw_context
*brw
)
613 struct intel_context
*intel
= &brw
->intel
;
614 struct gl_context
*ctx
= &brw
->intel
.ctx
;
618 if (!ctx
->Line
.StippleFlag
)
622 intel_emit_post_sync_nonzero_flush(intel
);
625 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
626 OUT_BATCH(ctx
->Line
.StipplePattern
);
627 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
628 tmpi
= tmp
* (1<<13);
629 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
633 const struct brw_tracked_state brw_line_stipple
= {
636 .brw
= BRW_NEW_CONTEXT
,
639 .emit
= upload_line_stipple
643 /***********************************************************************
644 * Misc invariant state packets
647 static void upload_invariant_state( struct brw_context
*brw
)
649 struct intel_context
*intel
= &brw
->intel
;
651 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
653 intel_emit_post_sync_nonzero_flush(intel
);
655 /* Select the 3D pipeline (as opposed to media) */
657 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16 | 0);
660 if (intel
->gen
< 6) {
661 /* Disable depth offset clamping. */
663 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
668 if (intel
->gen
>= 6) {
670 int len
= intel
->gen
>= 7 ? 4 : 3;
673 OUT_BATCH(_3DSTATE_MULTISAMPLE
<< 16 | (len
- 2));
674 OUT_BATCH(MS_PIXEL_LOCATION_CENTER
|
676 OUT_BATCH(0); /* positions for 4/8-sample */
682 OUT_BATCH(_3DSTATE_SAMPLE_MASK
<< 16 | (2 - 2));
686 if (intel
->gen
< 7) {
687 for (i
= 0; i
< 4; i
++) {
689 OUT_BATCH(_3DSTATE_GS_SVB_INDEX
<< 16 | (4 - 2));
690 OUT_BATCH(i
<< SVB_INDEX_SHIFT
);
692 OUT_BATCH(0xffffffff);
699 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
704 OUT_BATCH(brw
->CMD_VF_STATISTICS
<< 16 |
705 (unlikely(INTEL_DEBUG
& DEBUG_STATS
) ? 1 : 0));
709 const struct brw_tracked_state brw_invariant_state
= {
712 .brw
= BRW_NEW_CONTEXT
,
715 .emit
= upload_invariant_state
719 * Define the base addresses which some state is referenced from.
721 * This allows us to avoid having to emit relocations for the objects,
722 * and is actually required for binding table pointers on gen6.
724 * Surface state base address covers binding table pointers and
725 * surface state objects, but not the surfaces that the surface state
728 static void upload_state_base_address( struct brw_context
*brw
)
730 struct intel_context
*intel
= &brw
->intel
;
732 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
733 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
734 * programmed prior to STATE_BASE_ADDRESS.
736 * However, given that the instruction SBA (general state base
737 * address) on this chipset is always set to 0 across X and GL,
738 * maybe this isn't required for us in particular.
741 if (intel
->gen
>= 6) {
743 intel_emit_post_sync_nonzero_flush(intel
);
746 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
747 /* General state base address: stateless DP read/write requests */
749 /* Surface state base address:
750 * BINDING_TABLE_STATE
753 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
754 /* Dynamic state base address:
756 * SAMPLER_BORDER_COLOR_STATE
757 * CLIP, SF, WM/CC viewport state
759 * DEPTH_STENCIL_STATE
761 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
762 * Disable is clear, which we rely on)
764 OUT_RELOC(intel
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
765 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
767 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
768 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
769 1); /* Instruction base address: shader kernels (incl. SIP) */
771 OUT_BATCH(1); /* General state upper bound */
772 /* Dynamic state upper bound. Although the documentation says that
773 * programming it to zero will cause it to be ignored, that is a lie.
774 * If this isn't programmed to a real bound, the sampler border color
775 * pointer is rejected, causing border color to mysteriously fail.
777 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
778 intel
->batch
.bo
->size
| 1);
779 OUT_BATCH(1); /* Indirect object upper bound */
780 OUT_BATCH(1); /* Instruction access upper bound */
782 } else if (intel
->gen
== 5) {
784 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
785 OUT_BATCH(1); /* General state base address */
786 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
787 1); /* Surface state base address */
788 OUT_BATCH(1); /* Indirect object base address */
789 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
790 1); /* Instruction base address */
791 OUT_BATCH(1); /* General state upper bound */
792 OUT_BATCH(1); /* Indirect object upper bound */
793 OUT_BATCH(1); /* Instruction access upper bound */
797 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
798 OUT_BATCH(1); /* General state base address */
799 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
800 1); /* Surface state base address */
801 OUT_BATCH(1); /* Indirect object base address */
802 OUT_BATCH(1); /* General state upper bound */
803 OUT_BATCH(1); /* Indirect object upper bound */
807 /* According to section 3.6.1 of VOL1 of the 965 PRM,
808 * STATE_BASE_ADDRESS updates require a reissue of:
810 * 3DSTATE_PIPELINE_POINTERS
811 * 3DSTATE_BINDING_TABLE_POINTERS
812 * MEDIA_STATE_POINTERS
814 * and this continues through Ironlake. The Sandy Bridge PRM, vol
815 * 1 part 1 says that the folowing packets must be reissued:
817 * 3DSTATE_CC_POINTERS
818 * 3DSTATE_BINDING_TABLE_POINTERS
819 * 3DSTATE_SAMPLER_STATE_POINTERS
820 * 3DSTATE_VIEWPORT_STATE_POINTERS
821 * MEDIA_STATE_POINTERS
823 * Those are always reissued following SBA updates anyway (new
824 * batch time), except in the case of the program cache BO
825 * changing. Having a separate state flag makes the sequence more
829 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
832 const struct brw_tracked_state brw_state_base_address
= {
835 .brw
= (BRW_NEW_BATCH
|
836 BRW_NEW_PROGRAM_CACHE
),
839 .emit
= upload_state_base_address