2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
37 #include "intel_regions.h"
39 #include "brw_context.h"
40 #include "brw_state.h"
41 #include "brw_defines.h"
43 /* Constant single cliprect for framebuffer object or DRI2 drawing */
44 static void upload_drawing_rect(struct brw_context
*brw
)
46 struct intel_context
*intel
= &brw
->intel
;
47 struct gl_context
*ctx
= &intel
->ctx
;
50 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
51 OUT_BATCH(0); /* xmin, ymin */
52 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
53 ((ctx
->DrawBuffer
->Height
- 1) << 16));
58 const struct brw_tracked_state brw_drawing_rect
= {
61 .brw
= BRW_NEW_CONTEXT
,
64 .emit
= upload_drawing_rect
68 * Upload the binding table pointers, which point each stage's array of surface
71 * The binding table pointers are relative to the surface state base address,
72 * which points at the batchbuffer containing the streamed batch state.
74 static void upload_binding_table_pointers(struct brw_context
*brw
)
76 struct intel_context
*intel
= &brw
->intel
;
79 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 | (6 - 2));
80 OUT_BATCH(brw
->bind
.bo_offset
);
81 OUT_BATCH(0); /* gs */
82 OUT_BATCH(0); /* clip */
83 OUT_BATCH(0); /* sf */
84 OUT_BATCH(brw
->bind
.bo_offset
);
88 const struct brw_tracked_state brw_binding_table_pointers
= {
91 .brw
= (BRW_NEW_BATCH
|
92 BRW_NEW_STATE_BASE_ADDRESS
|
93 BRW_NEW_VS_BINDING_TABLE
|
94 BRW_NEW_GS_BINDING_TABLE
|
95 BRW_NEW_PS_BINDING_TABLE
),
98 .emit
= upload_binding_table_pointers
,
102 * Upload the binding table pointers, which point each stage's array of surface
105 * The binding table pointers are relative to the surface state base address,
106 * which points at the batchbuffer containing the streamed batch state.
108 static void upload_gen6_binding_table_pointers(struct brw_context
*brw
)
110 struct intel_context
*intel
= &brw
->intel
;
113 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
114 GEN6_BINDING_TABLE_MODIFY_VS
|
115 GEN6_BINDING_TABLE_MODIFY_GS
|
116 GEN6_BINDING_TABLE_MODIFY_PS
|
118 OUT_BATCH(brw
->bind
.bo_offset
); /* vs */
119 OUT_BATCH(brw
->bind
.bo_offset
); /* gs */
120 OUT_BATCH(brw
->bind
.bo_offset
); /* wm/ps */
124 const struct brw_tracked_state gen6_binding_table_pointers
= {
127 .brw
= (BRW_NEW_BATCH
|
128 BRW_NEW_STATE_BASE_ADDRESS
|
129 BRW_NEW_VS_BINDING_TABLE
|
130 BRW_NEW_GS_BINDING_TABLE
|
131 BRW_NEW_PS_BINDING_TABLE
),
134 .emit
= upload_gen6_binding_table_pointers
,
138 * Upload pointers to the per-stage state.
140 * The state pointers in this packet are all relative to the general state
141 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
143 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
145 struct intel_context
*intel
= &brw
->intel
;
147 if (intel
->gen
== 5) {
148 /* Need to flush before changing clip max threads for errata. */
155 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
156 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
157 brw
->vs
.state_offset
);
158 if (brw
->gs
.prog_active
)
159 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
160 brw
->gs
.state_offset
| 1);
163 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
164 brw
->clip
.state_offset
| 1);
165 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
166 brw
->sf
.state_offset
);
167 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
168 brw
->wm
.state_offset
);
169 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
170 brw
->cc
.state_offset
);
173 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
176 static void upload_psp_urb_cbs(struct brw_context
*brw
)
178 upload_pipelined_state_pointers(brw
);
179 brw_upload_urb_fence(brw
);
180 brw_upload_cs_urb_state(brw
);
183 const struct brw_tracked_state brw_psp_urb_cbs
= {
186 .brw
= (BRW_NEW_URB_FENCE
|
188 BRW_NEW_STATE_BASE_ADDRESS
),
189 .cache
= (CACHE_NEW_VS_UNIT
|
192 CACHE_NEW_CLIP_UNIT
|
197 .emit
= upload_psp_urb_cbs
,
201 brw_depthbuffer_format(struct brw_context
*brw
)
203 struct intel_context
*intel
= &brw
->intel
;
204 struct gl_context
*ctx
= &intel
->ctx
;
205 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
206 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
207 struct intel_renderbuffer
*srb
;
210 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
211 !srb
->mt
->stencil_mt
&&
212 (srb
->Base
.Format
== MESA_FORMAT_S8_Z24
||
213 srb
->Base
.Format
== MESA_FORMAT_Z32_FLOAT_X24S8
)) {
218 return BRW_DEPTHFORMAT_D32_FLOAT
;
220 switch (drb
->mt
->format
) {
221 case MESA_FORMAT_Z16
:
222 return BRW_DEPTHFORMAT_D16_UNORM
;
223 case MESA_FORMAT_Z32_FLOAT
:
224 return BRW_DEPTHFORMAT_D32_FLOAT
;
225 case MESA_FORMAT_X8_Z24
:
226 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
227 case MESA_FORMAT_S8_Z24
:
228 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
229 case MESA_FORMAT_Z32_FLOAT_X24S8
:
230 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT
;
232 _mesa_problem(ctx
, "Unexpected depth format %s\n",
233 _mesa_get_format_name(drb
->Base
.Format
));
234 return BRW_DEPTHFORMAT_D16_UNORM
;
238 static void emit_depthbuffer(struct brw_context
*brw
)
240 struct intel_context
*intel
= &brw
->intel
;
241 struct gl_context
*ctx
= &intel
->ctx
;
242 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
244 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
245 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
246 struct intel_mipmap_tree
*stencil_mt
= NULL
;
247 struct intel_region
*hiz_region
= NULL
;
249 bool separate_stencil
= false;
253 depth_irb
->mt
->hiz_mt
) {
254 hiz_region
= depth_irb
->mt
->hiz_mt
->region
;
257 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
258 * non-pipelined state that will need the PIPE_CONTROL workaround.
260 if (intel
->gen
== 6) {
261 intel_emit_post_sync_nonzero_flush(intel
);
262 intel_emit_depth_stall_flushes(intel
);
265 /* Find the real separate stencil mt if present. */
267 stencil_mt
= stencil_irb
->mt
;
268 if (stencil_mt
->stencil_mt
)
269 stencil_mt
= stencil_mt
->stencil_mt
;
271 if (stencil_mt
->format
== MESA_FORMAT_S8
)
272 separate_stencil
= true;
275 /* If there's a packed depth/stencil bound to stencil only, we need to
276 * emit the packed depth/stencil buffer packet.
278 if (!depth_irb
&& stencil_irb
&& !separate_stencil
)
279 depth_irb
= stencil_irb
;
283 else if (intel
->is_g4x
|| intel
->gen
== 5)
288 if (!depth_irb
&& !separate_stencil
) {
290 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
291 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
292 (BRW_SURFACE_NULL
<< 29));
297 if (intel
->is_g4x
|| intel
->gen
>= 5)
305 } else if (!depth_irb
&& separate_stencil
) {
307 * There exists a separate stencil buffer but no depth buffer.
309 * The stencil buffer inherits most of its fields from
310 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
313 * Since the stencil buffer has quirky pitch requirements, its region
314 * was allocated with half height and double cpp. So we need
315 * a multiplier of 2 to obtain the surface's real height.
317 * Enable the hiz bit because it and the separate stencil bit must have
318 * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
319 * 1.21 "Separate Stencil Enable":
320 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
321 * Enable must also be enabled.
323 * [DevGT]: This field must be set to the same value (enabled or
324 * disabled) as Hierarchical Depth Buffer Enable
326 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
327 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
328 * [DevGT+]: This field must be set to TRUE.
330 struct intel_region
*region
= stencil_mt
->region
;
332 assert(intel
->has_separate_stencil
);
335 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
336 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
337 (1 << 21) | /* separate stencil enable */
338 (1 << 22) | /* hiz enable */
339 (BRW_TILEWALK_YMAJOR
<< 26) |
340 (1 << 27) | /* tiled surface */
341 (BRW_SURFACE_2D
<< 29));
343 OUT_BATCH(((region
->width
- 1) << 6) |
344 (2 * region
->height
- 1) << 19);
354 struct intel_region
*region
= depth_irb
->mt
->region
;
355 uint32_t tile_x
, tile_y
, offset
;
357 /* If using separate stencil, hiz must be enabled. */
358 assert(!separate_stencil
|| hiz_region
);
360 offset
= intel_renderbuffer_tile_offsets(depth_irb
, &tile_x
, &tile_y
);
362 assert(intel
->gen
< 6 || region
->tiling
== I915_TILING_Y
);
363 assert(!hiz_region
|| region
->tiling
== I915_TILING_Y
);
366 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
367 OUT_BATCH(((region
->pitch
* region
->cpp
) - 1) |
368 (brw_depthbuffer_format(brw
) << 18) |
369 ((hiz_region
? 1 : 0) << 21) | /* separate stencil enable */
370 ((hiz_region
? 1 : 0) << 22) | /* hiz enable */
371 (BRW_TILEWALK_YMAJOR
<< 26) |
372 ((region
->tiling
!= I915_TILING_NONE
) << 27) |
373 (BRW_SURFACE_2D
<< 29));
374 OUT_RELOC(region
->bo
,
375 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
377 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1) |
378 ((region
->width
- 1) << 6) |
379 ((region
->height
- 1) << 19));
382 if (intel
->is_g4x
|| intel
->gen
>= 5)
383 OUT_BATCH(tile_x
| (tile_y
<< 16));
385 assert(tile_x
== 0 && tile_y
== 0);
393 if (hiz_region
|| separate_stencil
) {
395 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
396 * stencil enable' and 'hiz enable' bits were set. Therefore we must
397 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
398 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
399 * failure to do so causes hangs on gen5 and a stall on gen6.
402 /* Emit hiz buffer. */
405 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
406 OUT_BATCH(hiz_region
->pitch
* hiz_region
->cpp
- 1);
407 OUT_RELOC(hiz_region
->bo
,
408 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
413 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
419 /* Emit stencil buffer. */
420 if (separate_stencil
) {
421 struct intel_region
*region
= stencil_mt
->region
;
423 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
424 OUT_BATCH(region
->pitch
* region
->cpp
- 1);
425 OUT_RELOC(region
->bo
,
426 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
431 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
439 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
440 * params must be emitted.
442 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
443 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
444 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
446 if (intel
->gen
>= 6 || hiz_region
) {
448 intel_emit_post_sync_nonzero_flush(intel
);
451 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 | (2 - 2));
457 const struct brw_tracked_state brw_depthbuffer
= {
459 .mesa
= _NEW_BUFFERS
,
460 .brw
= BRW_NEW_BATCH
,
463 .emit
= emit_depthbuffer
,
468 /***********************************************************************
469 * Polygon stipple packet
472 static void upload_polygon_stipple(struct brw_context
*brw
)
474 struct intel_context
*intel
= &brw
->intel
;
475 struct gl_context
*ctx
= &brw
->intel
.ctx
;
479 if (!ctx
->Polygon
.StippleFlag
)
483 intel_emit_post_sync_nonzero_flush(intel
);
486 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
488 /* Polygon stipple is provided in OpenGL order, i.e. bottom
489 * row first. If we're rendering to a window (i.e. the
490 * default frame buffer object, 0), then we need to invert
491 * it to match our pixel layout. But if we're rendering
492 * to a FBO (i.e. any named frame buffer object), we *don't*
493 * need to invert - we already match the layout.
495 if (ctx
->DrawBuffer
->Name
== 0) {
496 for (i
= 0; i
< 32; i
++)
497 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
500 for (i
= 0; i
< 32; i
++)
501 OUT_BATCH(ctx
->PolygonStipple
[i
]);
506 const struct brw_tracked_state brw_polygon_stipple
= {
508 .mesa
= (_NEW_POLYGONSTIPPLE
|
510 .brw
= BRW_NEW_CONTEXT
,
513 .emit
= upload_polygon_stipple
517 /***********************************************************************
518 * Polygon stipple offset packet
521 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
523 struct intel_context
*intel
= &brw
->intel
;
524 struct gl_context
*ctx
= &brw
->intel
.ctx
;
527 if (!ctx
->Polygon
.StippleFlag
)
531 intel_emit_post_sync_nonzero_flush(intel
);
534 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
538 * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
539 * we have to invert the Y axis in order to match the OpenGL
540 * pixel coordinate system, and our offset must be matched
541 * to the window position. If we're drawing to a FBO
542 * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
543 * system works just fine, and there's no window system to
546 if (brw
->intel
.ctx
.DrawBuffer
->Name
== 0)
547 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
553 const struct brw_tracked_state brw_polygon_stipple_offset
= {
555 .mesa
= (_NEW_BUFFERS
|
557 .brw
= BRW_NEW_CONTEXT
,
560 .emit
= upload_polygon_stipple_offset
563 /**********************************************************************
566 static void upload_aa_line_parameters(struct brw_context
*brw
)
568 struct intel_context
*intel
= &brw
->intel
;
569 struct gl_context
*ctx
= &brw
->intel
.ctx
;
571 if (!ctx
->Line
.SmoothFlag
|| !brw
->has_aa_line_parameters
)
575 intel_emit_post_sync_nonzero_flush(intel
);
577 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
578 /* use legacy aa line coverage computation */
584 const struct brw_tracked_state brw_aa_line_parameters
= {
587 .brw
= BRW_NEW_CONTEXT
,
590 .emit
= upload_aa_line_parameters
593 /***********************************************************************
594 * Line stipple packet
597 static void upload_line_stipple(struct brw_context
*brw
)
599 struct intel_context
*intel
= &brw
->intel
;
600 struct gl_context
*ctx
= &brw
->intel
.ctx
;
604 if (!ctx
->Line
.StippleFlag
)
608 intel_emit_post_sync_nonzero_flush(intel
);
611 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
612 OUT_BATCH(ctx
->Line
.StipplePattern
);
613 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
614 tmpi
= tmp
* (1<<13);
615 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
619 const struct brw_tracked_state brw_line_stipple
= {
622 .brw
= BRW_NEW_CONTEXT
,
625 .emit
= upload_line_stipple
629 /***********************************************************************
630 * Misc invarient state packets
633 static void upload_invarient_state( struct brw_context
*brw
)
635 struct intel_context
*intel
= &brw
->intel
;
637 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
639 intel_emit_post_sync_nonzero_flush(intel
);
641 /* Select the 3D pipeline (as opposed to media) */
643 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16 | 0);
646 if (intel
->gen
< 6) {
647 /* Disable depth offset clamping. */
649 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
654 if (intel
->gen
>= 6) {
656 int len
= intel
->gen
>= 7 ? 4 : 3;
659 OUT_BATCH(_3DSTATE_MULTISAMPLE
<< 16 | (len
- 2));
660 OUT_BATCH(MS_PIXEL_LOCATION_CENTER
|
662 OUT_BATCH(0); /* positions for 4/8-sample */
668 OUT_BATCH(_3DSTATE_SAMPLE_MASK
<< 16 | (2 - 2));
672 if (intel
->gen
< 7) {
673 for (i
= 0; i
< 4; i
++) {
675 OUT_BATCH(_3DSTATE_GS_SVB_INDEX
<< 16 | (4 - 2));
676 OUT_BATCH(i
<< SVB_INDEX_SHIFT
);
678 OUT_BATCH(0xffffffff);
685 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
690 OUT_BATCH(brw
->CMD_VF_STATISTICS
<< 16 |
691 (unlikely(INTEL_DEBUG
& DEBUG_STATS
) ? 1 : 0));
695 const struct brw_tracked_state brw_invarient_state
= {
698 .brw
= BRW_NEW_CONTEXT
,
701 .emit
= upload_invarient_state
705 * Define the base addresses which some state is referenced from.
707 * This allows us to avoid having to emit relocations for the objects,
708 * and is actually required for binding table pointers on gen6.
710 * Surface state base address covers binding table pointers and
711 * surface state objects, but not the surfaces that the surface state
714 static void upload_state_base_address( struct brw_context
*brw
)
716 struct intel_context
*intel
= &brw
->intel
;
718 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
719 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
720 * programmed prior to STATE_BASE_ADDRESS.
722 * However, given that the instruction SBA (general state base
723 * address) on this chipset is always set to 0 across X and GL,
724 * maybe this isn't required for us in particular.
727 if (intel
->gen
>= 6) {
729 intel_emit_post_sync_nonzero_flush(intel
);
732 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
733 /* General state base address: stateless DP read/write requests */
735 /* Surface state base address:
736 * BINDING_TABLE_STATE
739 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
740 /* Dynamic state base address:
742 * SAMPLER_BORDER_COLOR_STATE
743 * CLIP, SF, WM/CC viewport state
745 * DEPTH_STENCIL_STATE
747 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
748 * Disable is clear, which we rely on)
750 OUT_RELOC(intel
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
751 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
753 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
754 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
755 1); /* Instruction base address: shader kernels (incl. SIP) */
757 OUT_BATCH(1); /* General state upper bound */
758 OUT_BATCH(1); /* Dynamic state upper bound */
759 OUT_BATCH(1); /* Indirect object upper bound */
760 OUT_BATCH(1); /* Instruction access upper bound */
762 } else if (intel
->gen
== 5) {
764 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
765 OUT_BATCH(1); /* General state base address */
766 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
767 1); /* Surface state base address */
768 OUT_BATCH(1); /* Indirect object base address */
769 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
770 1); /* Instruction base address */
771 OUT_BATCH(1); /* General state upper bound */
772 OUT_BATCH(1); /* Indirect object upper bound */
773 OUT_BATCH(1); /* Instruction access upper bound */
777 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
778 OUT_BATCH(1); /* General state base address */
779 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
780 1); /* Surface state base address */
781 OUT_BATCH(1); /* Indirect object base address */
782 OUT_BATCH(1); /* General state upper bound */
783 OUT_BATCH(1); /* Indirect object upper bound */
787 /* According to section 3.6.1 of VOL1 of the 965 PRM,
788 * STATE_BASE_ADDRESS updates require a reissue of:
790 * 3DSTATE_PIPELINE_POINTERS
791 * 3DSTATE_BINDING_TABLE_POINTERS
792 * MEDIA_STATE_POINTERS
794 * and this continues through Ironlake. The Sandy Bridge PRM, vol
795 * 1 part 1 says that the folowing packets must be reissued:
797 * 3DSTATE_CC_POINTERS
798 * 3DSTATE_BINDING_TABLE_POINTERS
799 * 3DSTATE_SAMPLER_STATE_POINTERS
800 * 3DSTATE_VIEWPORT_STATE_POINTERS
801 * MEDIA_STATE_POINTERS
803 * Those are always reissued following SBA updates anyway (new
804 * batch time), except in the case of the program cache BO
805 * changing. Having a separate state flag makes the sequence more
809 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
812 const struct brw_tracked_state brw_state_base_address
= {
815 .brw
= (BRW_NEW_BATCH
|
816 BRW_NEW_PROGRAM_CACHE
),
819 .emit
= upload_state_base_address