2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
37 #include "intel_regions.h"
39 #include "brw_context.h"
40 #include "brw_state.h"
41 #include "brw_defines.h"
43 /* Constant single cliprect for framebuffer object or DRI2 drawing */
44 static void upload_drawing_rect(struct brw_context
*brw
)
46 struct intel_context
*intel
= &brw
->intel
;
47 struct gl_context
*ctx
= &intel
->ctx
;
50 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
51 OUT_BATCH(0); /* xmin, ymin */
52 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
53 ((ctx
->DrawBuffer
->Height
- 1) << 16));
58 const struct brw_tracked_state brw_drawing_rect
= {
61 .brw
= BRW_NEW_CONTEXT
,
64 .emit
= upload_drawing_rect
68 * Upload the binding table pointers, which point each stage's array of surface
71 * The binding table pointers are relative to the surface state base address,
72 * which points at the batchbuffer containing the streamed batch state.
74 static void upload_binding_table_pointers(struct brw_context
*brw
)
76 struct intel_context
*intel
= &brw
->intel
;
79 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 | (6 - 2));
80 OUT_BATCH(brw
->bind
.bo_offset
);
81 OUT_BATCH(0); /* gs */
82 OUT_BATCH(0); /* clip */
83 OUT_BATCH(0); /* sf */
84 OUT_BATCH(brw
->bind
.bo_offset
);
88 const struct brw_tracked_state brw_binding_table_pointers
= {
91 .brw
= (BRW_NEW_BATCH
|
92 BRW_NEW_STATE_BASE_ADDRESS
|
93 BRW_NEW_VS_BINDING_TABLE
|
94 BRW_NEW_GS_BINDING_TABLE
|
95 BRW_NEW_PS_BINDING_TABLE
),
98 .emit
= upload_binding_table_pointers
,
102 * Upload the binding table pointers, which point each stage's array of surface
105 * The binding table pointers are relative to the surface state base address,
106 * which points at the batchbuffer containing the streamed batch state.
108 static void upload_gen6_binding_table_pointers(struct brw_context
*brw
)
110 struct intel_context
*intel
= &brw
->intel
;
113 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS
<< 16 |
114 GEN6_BINDING_TABLE_MODIFY_VS
|
115 GEN6_BINDING_TABLE_MODIFY_GS
|
116 GEN6_BINDING_TABLE_MODIFY_PS
|
118 OUT_BATCH(brw
->bind
.bo_offset
); /* vs */
119 OUT_BATCH(0); /* gs */
120 OUT_BATCH(brw
->bind
.bo_offset
); /* wm/ps */
124 const struct brw_tracked_state gen6_binding_table_pointers
= {
127 .brw
= (BRW_NEW_BATCH
|
128 BRW_NEW_STATE_BASE_ADDRESS
|
129 BRW_NEW_VS_BINDING_TABLE
|
130 BRW_NEW_GS_BINDING_TABLE
|
131 BRW_NEW_PS_BINDING_TABLE
),
134 .emit
= upload_gen6_binding_table_pointers
,
138 * Upload pointers to the per-stage state.
140 * The state pointers in this packet are all relative to the general state
141 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
143 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
145 struct intel_context
*intel
= &brw
->intel
;
147 if (intel
->gen
== 5) {
148 /* Need to flush before changing clip max threads for errata. */
155 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
156 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
157 brw
->vs
.state_offset
);
158 if (brw
->gs
.prog_active
)
159 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
160 brw
->gs
.state_offset
| 1);
163 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
164 brw
->clip
.state_offset
| 1);
165 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
166 brw
->sf
.state_offset
);
167 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
168 brw
->wm
.state_offset
);
169 OUT_RELOC(brw
->intel
.batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
170 brw
->cc
.state_offset
);
173 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
176 static void upload_psp_urb_cbs(struct brw_context
*brw
)
178 upload_pipelined_state_pointers(brw
);
179 brw_upload_urb_fence(brw
);
180 brw_upload_cs_urb_state(brw
);
183 const struct brw_tracked_state brw_psp_urb_cbs
= {
186 .brw
= (BRW_NEW_URB_FENCE
|
188 BRW_NEW_STATE_BASE_ADDRESS
),
189 .cache
= (CACHE_NEW_VS_UNIT
|
192 CACHE_NEW_CLIP_UNIT
|
197 .emit
= upload_psp_urb_cbs
,
200 static void emit_depthbuffer(struct brw_context
*brw
)
202 struct intel_context
*intel
= &brw
->intel
;
203 struct gl_context
*ctx
= &intel
->ctx
;
204 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
206 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
207 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
208 struct intel_region
*hiz_region
= NULL
;
213 depth_irb
->mt
->hiz_mt
) {
214 hiz_region
= depth_irb
->mt
->hiz_mt
->region
;
217 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
218 * non-pipelined state that will need the PIPE_CONTROL workaround.
220 if (intel
->gen
== 6) {
221 intel_emit_post_sync_nonzero_flush(intel
);
222 intel_emit_depth_stall_flushes(intel
);
226 * If either depth or stencil buffer has packed depth/stencil format,
227 * then don't use separate stencil. Emit only a depth buffer.
229 if (depth_irb
&& depth_irb
->Base
.Format
== MESA_FORMAT_S8_Z24
) {
231 } else if (!depth_irb
&& stencil_irb
232 && stencil_irb
->Base
.Format
== MESA_FORMAT_S8_Z24
) {
233 depth_irb
= stencil_irb
;
239 else if (intel
->is_g4x
|| intel
->gen
== 5)
244 if (!depth_irb
&& !stencil_irb
) {
246 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
247 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
248 (BRW_SURFACE_NULL
<< 29));
253 if (intel
->is_g4x
|| intel
->gen
>= 5)
261 } else if (!depth_irb
&& stencil_irb
) {
263 * There exists a separate stencil buffer but no depth buffer.
265 * The stencil buffer inherits most of its fields from
266 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
269 * Since the stencil buffer has quirky pitch requirements, its region
270 * was allocated with half height and double cpp. So we need
271 * a multiplier of 2 to obtain the surface's real height.
273 * Enable the hiz bit because it and the separate stencil bit must have
274 * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
275 * 1.21 "Separate Stencil Enable":
276 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
277 * Enable must also be enabled.
279 * [DevGT]: This field must be set to the same value (enabled or
280 * disabled) as Hierarchical Depth Buffer Enable
282 struct intel_region
*region
= stencil_irb
->mt
->region
;
284 assert(intel
->has_separate_stencil
);
285 assert(stencil_irb
->Base
.Format
== MESA_FORMAT_S8
);
288 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
289 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT
<< 18) |
290 (1 << 21) | /* separate stencil enable */
291 (1 << 22) | /* hiz enable */
292 (BRW_TILEWALK_YMAJOR
<< 26) |
293 (BRW_SURFACE_2D
<< 29));
295 OUT_BATCH(((region
->width
- 1) << 6) |
296 (2 * region
->height
- 1) << 19);
306 struct intel_region
*region
= depth_irb
->mt
->region
;
308 uint32_t tile_x
, tile_y
, offset
;
310 /* If using separate stencil, hiz must be enabled. */
311 assert(!stencil_irb
|| hiz_region
);
313 switch (region
->cpp
) {
315 format
= BRW_DEPTHFORMAT_D16_UNORM
;
318 if (intel
->depth_buffer_is_float
)
319 format
= BRW_DEPTHFORMAT_D32_FLOAT
;
321 format
= BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
323 format
= BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
330 offset
= intel_renderbuffer_tile_offsets(depth_irb
, &tile_x
, &tile_y
);
332 assert(intel
->gen
< 6 || region
->tiling
== I915_TILING_Y
);
333 assert(!hiz_region
|| region
->tiling
== I915_TILING_Y
);
336 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
337 OUT_BATCH(((region
->pitch
* region
->cpp
) - 1) |
339 ((hiz_region
? 1 : 0) << 21) | /* separate stencil enable */
340 ((hiz_region
? 1 : 0) << 22) | /* hiz enable */
341 (BRW_TILEWALK_YMAJOR
<< 26) |
342 ((region
->tiling
!= I915_TILING_NONE
) << 27) |
343 (BRW_SURFACE_2D
<< 29));
344 OUT_RELOC(region
->bo
,
345 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
347 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< 1) |
348 ((region
->width
- 1) << 6) |
349 ((region
->height
- 1) << 19));
352 if (intel
->is_g4x
|| intel
->gen
>= 5)
353 OUT_BATCH(tile_x
| (tile_y
<< 16));
355 assert(tile_x
== 0 && tile_y
== 0);
363 if (hiz_region
|| stencil_irb
) {
365 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
366 * stencil enable' and 'hiz enable' bits were set. Therefore we must
367 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
368 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
369 * failure to do so causes hangs on gen5 and a stall on gen6.
372 /* Emit hiz buffer. */
375 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
376 OUT_BATCH(hiz_region
->pitch
* hiz_region
->cpp
- 1);
377 OUT_RELOC(hiz_region
->bo
,
378 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
383 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
389 /* Emit stencil buffer. */
391 struct intel_region
*region
= stencil_irb
->mt
->region
;
393 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
394 OUT_BATCH(region
->pitch
* region
->cpp
- 1);
395 OUT_RELOC(region
->bo
,
396 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
401 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
409 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
410 * params must be emitted.
412 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
413 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
414 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
416 if (intel
->gen
>= 6 || hiz_region
) {
418 intel_emit_post_sync_nonzero_flush(intel
);
421 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 | (2 - 2));
427 const struct brw_tracked_state brw_depthbuffer
= {
429 .mesa
= _NEW_BUFFERS
,
430 .brw
= BRW_NEW_BATCH
,
433 .emit
= emit_depthbuffer
,
438 /***********************************************************************
439 * Polygon stipple packet
442 static void upload_polygon_stipple(struct brw_context
*brw
)
444 struct intel_context
*intel
= &brw
->intel
;
445 struct gl_context
*ctx
= &brw
->intel
.ctx
;
449 if (!ctx
->Polygon
.StippleFlag
)
453 intel_emit_post_sync_nonzero_flush(intel
);
456 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
458 /* Polygon stipple is provided in OpenGL order, i.e. bottom
459 * row first. If we're rendering to a window (i.e. the
460 * default frame buffer object, 0), then we need to invert
461 * it to match our pixel layout. But if we're rendering
462 * to a FBO (i.e. any named frame buffer object), we *don't*
463 * need to invert - we already match the layout.
465 if (ctx
->DrawBuffer
->Name
== 0) {
466 for (i
= 0; i
< 32; i
++)
467 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
470 for (i
= 0; i
< 32; i
++)
471 OUT_BATCH(ctx
->PolygonStipple
[i
]);
476 const struct brw_tracked_state brw_polygon_stipple
= {
478 .mesa
= (_NEW_POLYGONSTIPPLE
|
480 .brw
= BRW_NEW_CONTEXT
,
483 .emit
= upload_polygon_stipple
487 /***********************************************************************
488 * Polygon stipple offset packet
491 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
493 struct intel_context
*intel
= &brw
->intel
;
494 struct gl_context
*ctx
= &brw
->intel
.ctx
;
497 if (!ctx
->Polygon
.StippleFlag
)
501 intel_emit_post_sync_nonzero_flush(intel
);
504 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
508 * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
509 * we have to invert the Y axis in order to match the OpenGL
510 * pixel coordinate system, and our offset must be matched
511 * to the window position. If we're drawing to a FBO
512 * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
513 * system works just fine, and there's no window system to
516 if (brw
->intel
.ctx
.DrawBuffer
->Name
== 0)
517 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
523 const struct brw_tracked_state brw_polygon_stipple_offset
= {
525 .mesa
= (_NEW_BUFFERS
|
527 .brw
= BRW_NEW_CONTEXT
,
530 .emit
= upload_polygon_stipple_offset
533 /**********************************************************************
536 static void upload_aa_line_parameters(struct brw_context
*brw
)
538 struct intel_context
*intel
= &brw
->intel
;
539 struct gl_context
*ctx
= &brw
->intel
.ctx
;
541 if (!ctx
->Line
.SmoothFlag
|| !brw
->has_aa_line_parameters
)
545 intel_emit_post_sync_nonzero_flush(intel
);
547 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
548 /* use legacy aa line coverage computation */
554 const struct brw_tracked_state brw_aa_line_parameters
= {
557 .brw
= BRW_NEW_CONTEXT
,
560 .emit
= upload_aa_line_parameters
563 /***********************************************************************
564 * Line stipple packet
567 static void upload_line_stipple(struct brw_context
*brw
)
569 struct intel_context
*intel
= &brw
->intel
;
570 struct gl_context
*ctx
= &brw
->intel
.ctx
;
574 if (!ctx
->Line
.StippleFlag
)
578 intel_emit_post_sync_nonzero_flush(intel
);
581 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
582 OUT_BATCH(ctx
->Line
.StipplePattern
);
583 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
584 tmpi
= tmp
* (1<<13);
585 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
589 const struct brw_tracked_state brw_line_stipple
= {
592 .brw
= BRW_NEW_CONTEXT
,
595 .emit
= upload_line_stipple
599 /***********************************************************************
600 * Misc invarient state packets
603 static void upload_invarient_state( struct brw_context
*brw
)
605 struct intel_context
*intel
= &brw
->intel
;
607 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
609 intel_emit_post_sync_nonzero_flush(intel
);
611 /* Select the 3D pipeline (as opposed to media) */
613 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16 | 0);
616 if (intel
->gen
< 6) {
617 /* Disable depth offset clamping. */
619 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
624 if (intel
->gen
>= 6) {
626 int len
= intel
->gen
>= 7 ? 4 : 3;
629 OUT_BATCH(_3DSTATE_MULTISAMPLE
<< 16 | (len
- 2));
630 OUT_BATCH(MS_PIXEL_LOCATION_CENTER
|
632 OUT_BATCH(0); /* positions for 4/8-sample */
638 OUT_BATCH(_3DSTATE_SAMPLE_MASK
<< 16 | (2 - 2));
642 if (intel
->gen
< 7) {
643 for (i
= 0; i
< 4; i
++) {
645 OUT_BATCH(_3DSTATE_GS_SVB_INDEX
<< 16 | (4 - 2));
646 OUT_BATCH(i
<< SVB_INDEX_SHIFT
);
648 OUT_BATCH(0xffffffff);
655 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
660 OUT_BATCH(brw
->CMD_VF_STATISTICS
<< 16 |
661 (unlikely(INTEL_DEBUG
& DEBUG_STATS
) ? 1 : 0));
665 const struct brw_tracked_state brw_invarient_state
= {
668 .brw
= BRW_NEW_CONTEXT
,
671 .emit
= upload_invarient_state
675 * Define the base addresses which some state is referenced from.
677 * This allows us to avoid having to emit relocations for the objects,
678 * and is actually required for binding table pointers on gen6.
680 * Surface state base address covers binding table pointers and
681 * surface state objects, but not the surfaces that the surface state
684 static void upload_state_base_address( struct brw_context
*brw
)
686 struct intel_context
*intel
= &brw
->intel
;
688 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
689 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
690 * programmed prior to STATE_BASE_ADDRESS.
692 * However, given that the instruction SBA (general state base
693 * address) on this chipset is always set to 0 across X and GL,
694 * maybe this isn't required for us in particular.
697 if (intel
->gen
>= 6) {
699 intel_emit_post_sync_nonzero_flush(intel
);
702 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
703 /* General state base address: stateless DP read/write requests */
705 /* Surface state base address:
706 * BINDING_TABLE_STATE
709 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
710 /* Dynamic state base address:
712 * SAMPLER_BORDER_COLOR_STATE
713 * CLIP, SF, WM/CC viewport state
715 * DEPTH_STENCIL_STATE
717 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
718 * Disable is clear, which we rely on)
720 OUT_RELOC(intel
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
721 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
723 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
724 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
725 1); /* Instruction base address: shader kernels (incl. SIP) */
727 OUT_BATCH(1); /* General state upper bound */
728 OUT_BATCH(1); /* Dynamic state upper bound */
729 OUT_BATCH(1); /* Indirect object upper bound */
730 OUT_BATCH(1); /* Instruction access upper bound */
732 } else if (intel
->gen
== 5) {
734 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
735 OUT_BATCH(1); /* General state base address */
736 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
737 1); /* Surface state base address */
738 OUT_BATCH(1); /* Indirect object base address */
739 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
740 1); /* Instruction base address */
741 OUT_BATCH(1); /* General state upper bound */
742 OUT_BATCH(1); /* Indirect object upper bound */
743 OUT_BATCH(1); /* Instruction access upper bound */
747 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
748 OUT_BATCH(1); /* General state base address */
749 OUT_RELOC(intel
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
750 1); /* Surface state base address */
751 OUT_BATCH(1); /* Indirect object base address */
752 OUT_BATCH(1); /* General state upper bound */
753 OUT_BATCH(1); /* Indirect object upper bound */
757 /* According to section 3.6.1 of VOL1 of the 965 PRM,
758 * STATE_BASE_ADDRESS updates require a reissue of:
760 * 3DSTATE_PIPELINE_POINTERS
761 * 3DSTATE_BINDING_TABLE_POINTERS
762 * MEDIA_STATE_POINTERS
764 * and this continues through Ironlake. The Sandy Bridge PRM, vol
765 * 1 part 1 says that the folowing packets must be reissued:
767 * 3DSTATE_CC_POINTERS
768 * 3DSTATE_BINDING_TABLE_POINTERS
769 * 3DSTATE_SAMPLER_STATE_POINTERS
770 * 3DSTATE_VIEWPORT_STATE_POINTERS
771 * MEDIA_STATE_POINTERS
773 * Those are always reissued following SBA updates anyway (new
774 * batch time), except in the case of the program cache BO
775 * changing. Having a separate state flag makes the sequence more
779 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
782 const struct brw_tracked_state brw_state_base_address
= {
785 .brw
= (BRW_NEW_BATCH
|
786 BRW_NEW_PROGRAM_CACHE
),
789 .emit
= upload_state_base_address