2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
37 #include "intel_regions.h"
39 #include "brw_context.h"
40 #include "brw_state.h"
41 #include "brw_defines.h"
43 #include "main/fbobject.h"
44 #include "main/glformats.h"
46 /* Constant single cliprect for framebuffer object or DRI2 drawing */
47 static void upload_drawing_rect(struct brw_context
*brw
)
49 struct gl_context
*ctx
= &brw
->ctx
;
51 /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined. */
53 intel_emit_post_sync_nonzero_flush(brw
);
56 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
57 OUT_BATCH(0); /* xmin, ymin */
58 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
59 ((ctx
->DrawBuffer
->Height
- 1) << 16));
64 const struct brw_tracked_state brw_drawing_rect
= {
67 .brw
= BRW_NEW_CONTEXT
,
70 .emit
= upload_drawing_rect
74 * Upload pointers to the per-stage state.
76 * The state pointers in this packet are all relative to the general state
77 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
79 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
82 /* Need to flush before changing clip max threads for errata. */
89 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
90 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
91 brw
->vs
.base
.state_offset
);
92 if (brw
->ff_gs
.prog_active
)
93 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
94 brw
->ff_gs
.state_offset
| 1);
97 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
98 brw
->clip
.state_offset
| 1);
99 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
100 brw
->sf
.state_offset
);
101 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
102 brw
->wm
.base
.state_offset
);
103 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
104 brw
->cc
.state_offset
);
107 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
110 static void upload_psp_urb_cbs(struct brw_context
*brw
)
112 upload_pipelined_state_pointers(brw
);
113 brw_upload_urb_fence(brw
);
114 brw_upload_cs_urb_state(brw
);
117 const struct brw_tracked_state brw_psp_urb_cbs
= {
120 .brw
= (BRW_NEW_URB_FENCE
|
122 BRW_NEW_STATE_BASE_ADDRESS
),
123 .cache
= (CACHE_NEW_VS_UNIT
|
124 CACHE_NEW_FF_GS_UNIT
|
125 CACHE_NEW_FF_GS_PROG
|
126 CACHE_NEW_CLIP_UNIT
|
131 .emit
= upload_psp_urb_cbs
,
135 brw_depthbuffer_format(struct brw_context
*brw
)
137 struct gl_context
*ctx
= &brw
->ctx
;
138 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
139 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
140 struct intel_renderbuffer
*srb
;
143 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
144 !srb
->mt
->stencil_mt
&&
145 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
146 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
151 return BRW_DEPTHFORMAT_D32_FLOAT
;
153 switch (drb
->mt
->format
) {
154 case MESA_FORMAT_Z_UNORM16
:
155 return BRW_DEPTHFORMAT_D16_UNORM
;
156 case MESA_FORMAT_Z_FLOAT32
:
157 return BRW_DEPTHFORMAT_D32_FLOAT
;
158 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
160 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
162 /* Use D24_UNORM_S8, not D24_UNORM_X8.
164 * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
165 * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
166 * 3DSTATE_DEPTH_BUFFER.Surface_Format).
168 * However, on Gen5, D24_UNORM_X8 may be used only if separate
169 * stencil is enabled, and we never enable it. From the Ironlake PRM,
170 * same section as above, Bit 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Buffer_Enable:
171 * If this field is disabled, the Surface Format of the depth
172 * buffer cannot be D24_UNORM_X8_UINT.
174 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
176 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
177 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
178 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
179 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT
;
181 _mesa_problem(ctx
, "Unexpected depth format %s\n",
182 _mesa_get_format_name(intel_rb_format(drb
)));
183 return BRW_DEPTHFORMAT_D16_UNORM
;
188 * Returns the mask of how many bits of x and y must be handled through the
189 * depthbuffer's draw offset x and y fields.
191 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
192 * between the depth, hiz, and stencil buffers. Because it can be hard to get
193 * all 3 to agree on this value, we want to do as much drawing offset
194 * adjustment as possible by moving the base offset of the 3 buffers, which is
195 * restricted to tile boundaries.
197 * For each buffer, the remainder must be applied through the x/y draw offset.
198 * This returns the worst-case mask of the low bits that have to go into the
199 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
200 * mask, then we're in trouble.
203 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
204 uint32_t depth_level
,
205 uint32_t depth_layer
,
206 struct intel_mipmap_tree
*stencil_mt
,
207 uint32_t *out_tile_mask_x
,
208 uint32_t *out_tile_mask_y
)
210 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
213 intel_region_get_tile_masks(depth_mt
->region
,
214 &tile_mask_x
, &tile_mask_y
, false);
216 if (intel_miptree_slice_has_hiz(depth_mt
, depth_level
, depth_layer
)) {
217 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
218 intel_region_get_tile_masks(depth_mt
->hiz_mt
->region
,
219 &hiz_tile_mask_x
, &hiz_tile_mask_y
, false);
221 /* Each HiZ row represents 2 rows of pixels */
222 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
224 tile_mask_x
|= hiz_tile_mask_x
;
225 tile_mask_y
|= hiz_tile_mask_y
;
230 if (stencil_mt
->stencil_mt
)
231 stencil_mt
= stencil_mt
->stencil_mt
;
233 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
234 /* Separate stencil buffer uses 64x64 tiles. */
238 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
239 intel_region_get_tile_masks(stencil_mt
->region
,
240 &stencil_tile_mask_x
,
241 &stencil_tile_mask_y
, false);
243 tile_mask_x
|= stencil_tile_mask_x
;
244 tile_mask_y
|= stencil_tile_mask_y
;
248 *out_tile_mask_x
= tile_mask_x
;
249 *out_tile_mask_y
= tile_mask_y
;
252 static struct intel_mipmap_tree
*
253 get_stencil_miptree(struct intel_renderbuffer
*irb
)
257 if (irb
->mt
->stencil_mt
)
258 return irb
->mt
->stencil_mt
;
263 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
264 GLbitfield clear_mask
)
266 struct gl_context
*ctx
= &brw
->ctx
;
267 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
268 bool rebase_depth
= false;
269 bool rebase_stencil
= false;
270 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
271 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
272 struct intel_mipmap_tree
*depth_mt
= NULL
;
273 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
274 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
275 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
276 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
277 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
280 depth_mt
= depth_irb
->mt
;
282 /* Initialize brw->depthstencil to 'nop' workaround state.
284 brw
->depthstencil
.tile_x
= 0;
285 brw
->depthstencil
.tile_y
= 0;
286 brw
->depthstencil
.depth_offset
= 0;
287 brw
->depthstencil
.stencil_offset
= 0;
288 brw
->depthstencil
.hiz_offset
= 0;
289 brw
->depthstencil
.depth_mt
= NULL
;
290 brw
->depthstencil
.stencil_mt
= NULL
;
292 brw
->depthstencil
.depth_mt
= depth_mt
;
294 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
296 /* Gen7+ doesn't require the workarounds, since we always program the
297 * surface state at the start of the whole surface.
302 /* Check if depth buffer is in depth/stencil format. If so, then it's only
303 * safe to invalidate it if we're also clearing stencil, and both depth_irb
304 * and stencil_irb point to the same miptree.
306 * Note: it's not sufficient to check for the case where
307 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
308 * because this fails to catch depth/stencil buffers on hardware that uses
309 * separate stencil. To catch that case, we check whether
310 * depth_mt->stencil_mt is non-NULL.
312 if (depth_irb
&& invalidate_depth
&&
313 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
314 depth_mt
->stencil_mt
)) {
315 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
316 && depth_irb
->mt
== stencil_irb
->mt
;
319 uint32_t tile_mask_x
, tile_mask_y
;
320 brw_get_depthstencil_tile_masks(depth_mt
,
321 depth_mt
? depth_irb
->mt_level
: 0,
322 depth_mt
? depth_irb
->mt_layer
: 0,
324 &tile_mask_x
, &tile_mask_y
);
327 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
328 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
330 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
331 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
332 * Coordinate Offset X/Y":
334 * "The 3 LSBs of both offsets must be zero to ensure correct
337 if (tile_x
& 7 || tile_y
& 7)
340 /* We didn't even have intra-tile offsets before g45. */
341 if (!brw
->has_surface_tile_offset
) {
342 if (tile_x
|| tile_y
)
347 perf_debug("HW workaround: blitting depth level %d to a temporary "
348 "to fix alignment (depth tile offset %d,%d)\n",
349 depth_irb
->mt_level
, tile_x
, tile_y
);
350 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
351 /* In the case of stencil_irb being the same packed depth/stencil
352 * texture but not the same rb, make it point at our rebased mt, too.
355 stencil_irb
!= depth_irb
&&
356 stencil_irb
->mt
== depth_mt
) {
357 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
358 intel_renderbuffer_set_draw_offset(stencil_irb
);
361 stencil_mt
= get_stencil_miptree(stencil_irb
);
363 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
364 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
368 stencil_mt
= get_stencil_miptree(stencil_irb
);
369 intel_miptree_get_image_offset(stencil_mt
,
370 stencil_irb
->mt_level
,
371 stencil_irb
->mt_layer
,
372 &stencil_draw_x
, &stencil_draw_y
);
373 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
374 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
376 /* If stencil doesn't match depth, then we'll need to rebase stencil
377 * as well. (if we hadn't decided to rebase stencil before, the
378 * post-stencil depth test will also rebase depth to try to match it
381 if (tile_x
!= stencil_tile_x
||
382 tile_y
!= stencil_tile_y
) {
383 rebase_stencil
= true;
388 /* If we have (just) stencil, check it for ignored low bits as well */
390 intel_miptree_get_image_offset(stencil_mt
,
391 stencil_irb
->mt_level
,
392 stencil_irb
->mt_layer
,
393 &stencil_draw_x
, &stencil_draw_y
);
394 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
395 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
397 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
398 rebase_stencil
= true;
400 if (!brw
->has_surface_tile_offset
) {
401 if (stencil_tile_x
|| stencil_tile_y
)
402 rebase_stencil
= true;
406 if (rebase_stencil
) {
407 perf_debug("HW workaround: blitting stencil level %d to a temporary "
408 "to fix alignment (stencil tile offset %d,%d)\n",
409 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
411 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
412 stencil_mt
= get_stencil_miptree(stencil_irb
);
414 intel_miptree_get_image_offset(stencil_mt
,
415 stencil_irb
->mt_level
,
416 stencil_irb
->mt_layer
,
417 &stencil_draw_x
, &stencil_draw_y
);
418 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
419 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
421 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
422 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
423 intel_renderbuffer_set_draw_offset(depth_irb
);
424 } else if (depth_irb
&& !rebase_depth
) {
425 if (tile_x
!= stencil_tile_x
||
426 tile_y
!= stencil_tile_y
) {
427 perf_debug("HW workaround: blitting depth level %d to a temporary "
428 "to match stencil level %d alignment (depth tile offset "
429 "%d,%d, stencil offset %d,%d)\n",
431 stencil_irb
->mt_level
,
433 stencil_tile_x
, stencil_tile_y
);
435 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
437 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
438 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
440 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
441 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
442 intel_renderbuffer_set_draw_offset(stencil_irb
);
445 WARN_ONCE(stencil_tile_x
!= tile_x
||
446 stencil_tile_y
!= tile_y
,
447 "Rebased stencil tile offset (%d,%d) doesn't match depth "
448 "tile offset (%d,%d).\n",
449 stencil_tile_x
, stencil_tile_y
,
456 tile_x
= stencil_tile_x
;
457 tile_y
= stencil_tile_y
;
460 /* While we just tried to get everything aligned, we may have failed to do
461 * so in the case of rendering to array or 3D textures, where nonzero faces
462 * will still have an offset post-rebase. At least give an informative
465 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
466 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
467 "Truncating offset, bad rendering may occur.\n");
471 /* Now, after rebasing, save off the new dephtstencil state so the hardware
472 * packets can just dereference that without re-calculating tile offsets.
474 brw
->depthstencil
.tile_x
= tile_x
;
475 brw
->depthstencil
.tile_y
= tile_y
;
477 depth_mt
= depth_irb
->mt
;
478 brw
->depthstencil
.depth_mt
= depth_mt
;
479 brw
->depthstencil
.depth_offset
=
480 intel_region_get_aligned_offset(depth_mt
->region
,
481 depth_irb
->draw_x
& ~tile_mask_x
,
482 depth_irb
->draw_y
& ~tile_mask_y
,
484 if (intel_renderbuffer_has_hiz(depth_irb
)) {
485 brw
->depthstencil
.hiz_offset
=
486 intel_region_get_aligned_offset(depth_mt
->region
,
487 depth_irb
->draw_x
& ~tile_mask_x
,
488 (depth_irb
->draw_y
& ~tile_mask_y
) /
494 stencil_mt
= get_stencil_miptree(stencil_irb
);
496 brw
->depthstencil
.stencil_mt
= stencil_mt
;
497 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
498 /* Note: we can't compute the stencil offset using
499 * intel_region_get_aligned_offset(), because stencil_region claims
500 * that the region is untiled even though it's W tiled.
502 brw
->depthstencil
.stencil_offset
=
503 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->region
->pitch
+
504 (stencil_draw_x
& ~tile_mask_x
) * 64;
510 brw_emit_depthbuffer(struct brw_context
*brw
)
512 struct gl_context
*ctx
= &brw
->ctx
;
513 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
515 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
516 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
517 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
518 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
519 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
520 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
521 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
522 bool separate_stencil
= false;
523 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
524 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
525 uint32_t depth_offset
= 0;
526 uint32_t width
= 1, height
= 1;
529 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
531 /* Gen7 supports only separate stencil */
532 assert(separate_stencil
|| brw
->gen
< 7);
535 /* If there's a packed depth/stencil bound to stencil only, we need to
536 * emit the packed depth/stencil buffer packet.
538 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
539 depth_irb
= stencil_irb
;
540 depth_mt
= stencil_mt
;
543 if (depth_irb
&& depth_mt
) {
544 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
545 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
546 * depthstencil format.
548 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
549 * set to the same value. Gens after 7 implicitly always set
550 * Separate_Stencil_Enable; software cannot disable it.
552 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
553 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
556 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
557 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
559 assert(brw
->gen
< 6 || depth_mt
->region
->tiling
== I915_TILING_Y
);
560 assert(!hiz
|| depth_mt
->region
->tiling
== I915_TILING_Y
);
562 depthbuffer_format
= brw_depthbuffer_format(brw
);
563 depth_surface_type
= BRW_SURFACE_2D
;
564 depth_offset
= brw
->depthstencil
.depth_offset
;
565 width
= depth_irb
->Base
.Base
.Width
;
566 height
= depth_irb
->Base
.Base
.Height
;
567 } else if (separate_stencil
) {
569 * There exists a separate stencil buffer but no depth buffer.
571 * The stencil buffer inherits most of its fields from
572 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
575 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
576 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
577 * [DevGT+]: This field must be set to TRUE.
579 assert(brw
->has_separate_stencil
);
581 depth_surface_type
= BRW_SURFACE_2D
;
582 width
= stencil_irb
->Base
.Base
.Width
;
583 height
= stencil_irb
->Base
.Base
.Height
;
586 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
587 depthbuffer_format
, depth_surface_type
,
588 stencil_mt
, hiz
, separate_stencil
,
589 width
, height
, tile_x
, tile_y
);
593 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
594 struct intel_mipmap_tree
*depth_mt
,
595 uint32_t depth_offset
, uint32_t depthbuffer_format
,
596 uint32_t depth_surface_type
,
597 struct intel_mipmap_tree
*stencil_mt
,
598 bool hiz
, bool separate_stencil
,
599 uint32_t width
, uint32_t height
,
600 uint32_t tile_x
, uint32_t tile_y
)
602 /* Enable the hiz bit if we're doing separate stencil, because it and the
603 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
604 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
605 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
606 * Enable must also be enabled.
608 * [DevGT]: This field must be set to the same value (enabled or
609 * disabled) as Hierarchical Depth Buffer Enable
611 bool enable_hiz_ss
= hiz
|| separate_stencil
;
614 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
615 * non-pipelined state that will need the PIPE_CONTROL workaround.
618 intel_emit_post_sync_nonzero_flush(brw
);
619 intel_emit_depth_stall_flushes(brw
);
625 else if (brw
->is_g4x
|| brw
->gen
== 5)
631 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
632 OUT_BATCH((depth_mt
? depth_mt
->region
->pitch
- 1 : 0) |
633 (depthbuffer_format
<< 18) |
634 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
635 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
636 (BRW_TILEWALK_YMAJOR
<< 26) |
637 ((depth_mt
? depth_mt
->region
->tiling
!= I915_TILING_NONE
: 1)
639 (depth_surface_type
<< 29));
642 OUT_RELOC(depth_mt
->region
->bo
,
643 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
649 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
650 ((height
+ tile_y
- 1) << 19));
653 if (brw
->is_g4x
|| brw
->gen
>= 5)
654 OUT_BATCH(tile_x
| (tile_y
<< 16));
656 assert(tile_x
== 0 && tile_y
== 0);
663 if (hiz
|| separate_stencil
) {
665 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
666 * stencil enable' and 'hiz enable' bits were set. Therefore we must
667 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
668 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
669 * failure to do so causes hangs on gen5 and a stall on gen6.
672 /* Emit hiz buffer. */
674 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_mt
;
676 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
677 OUT_BATCH(hiz_mt
->region
->pitch
- 1);
678 OUT_RELOC(hiz_mt
->region
->bo
,
679 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
680 brw
->depthstencil
.hiz_offset
);
684 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
690 /* Emit stencil buffer. */
691 if (separate_stencil
) {
692 struct intel_region
*region
= stencil_mt
->region
;
695 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
696 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
697 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
698 * The pitch must be set to 2x the value computed based on width, as
699 * the stencil buffer is stored with two rows interleaved.
701 OUT_BATCH(2 * region
->pitch
- 1);
702 OUT_RELOC(region
->bo
,
703 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
704 brw
->depthstencil
.stencil_offset
);
708 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
716 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
717 * params must be emitted.
719 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
720 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
721 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
723 if (brw
->gen
>= 6 || hiz
) {
725 intel_emit_post_sync_nonzero_flush(brw
);
728 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
729 GEN5_DEPTH_CLEAR_VALID
|
731 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
736 const struct brw_tracked_state brw_depthbuffer
= {
738 .mesa
= _NEW_BUFFERS
,
739 .brw
= BRW_NEW_BATCH
,
742 .emit
= brw_emit_depthbuffer
,
747 /***********************************************************************
748 * Polygon stipple packet
751 static void upload_polygon_stipple(struct brw_context
*brw
)
753 struct gl_context
*ctx
= &brw
->ctx
;
757 if (!ctx
->Polygon
.StippleFlag
)
761 intel_emit_post_sync_nonzero_flush(brw
);
764 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
766 /* Polygon stipple is provided in OpenGL order, i.e. bottom
767 * row first. If we're rendering to a window (i.e. the
768 * default frame buffer object, 0), then we need to invert
769 * it to match our pixel layout. But if we're rendering
770 * to a FBO (i.e. any named frame buffer object), we *don't*
771 * need to invert - we already match the layout.
773 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
774 for (i
= 0; i
< 32; i
++)
775 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
778 for (i
= 0; i
< 32; i
++)
779 OUT_BATCH(ctx
->PolygonStipple
[i
]);
784 const struct brw_tracked_state brw_polygon_stipple
= {
786 .mesa
= (_NEW_POLYGONSTIPPLE
|
788 .brw
= BRW_NEW_CONTEXT
,
791 .emit
= upload_polygon_stipple
795 /***********************************************************************
796 * Polygon stipple offset packet
799 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
801 struct gl_context
*ctx
= &brw
->ctx
;
804 if (!ctx
->Polygon
.StippleFlag
)
808 intel_emit_post_sync_nonzero_flush(brw
);
811 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
815 * If we're drawing to a system window we have to invert the Y axis
816 * in order to match the OpenGL pixel coordinate system, and our
817 * offset must be matched to the window position. If we're drawing
818 * to a user-created FBO then our native pixel coordinate system
819 * works just fine, and there's no window system to worry about.
821 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
822 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
828 const struct brw_tracked_state brw_polygon_stipple_offset
= {
830 .mesa
= (_NEW_BUFFERS
|
832 .brw
= BRW_NEW_CONTEXT
,
835 .emit
= upload_polygon_stipple_offset
838 /**********************************************************************
841 static void upload_aa_line_parameters(struct brw_context
*brw
)
843 struct gl_context
*ctx
= &brw
->ctx
;
845 if (!ctx
->Line
.SmoothFlag
)
848 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
849 if (brw
->gen
== 4 && !brw
->is_g4x
)
853 intel_emit_post_sync_nonzero_flush(brw
);
856 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
857 /* use legacy aa line coverage computation */
863 const struct brw_tracked_state brw_aa_line_parameters
= {
866 .brw
= BRW_NEW_CONTEXT
,
869 .emit
= upload_aa_line_parameters
872 /***********************************************************************
873 * Line stipple packet
876 static void upload_line_stipple(struct brw_context
*brw
)
878 struct gl_context
*ctx
= &brw
->ctx
;
882 if (!ctx
->Line
.StippleFlag
)
886 intel_emit_post_sync_nonzero_flush(brw
);
889 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
890 OUT_BATCH(ctx
->Line
.StipplePattern
);
894 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
895 tmpi
= tmp
* (1<<16);
896 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
900 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
901 tmpi
= tmp
* (1<<13);
902 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
908 const struct brw_tracked_state brw_line_stipple
= {
911 .brw
= BRW_NEW_CONTEXT
,
914 .emit
= upload_line_stipple
918 /***********************************************************************
919 * Misc invariant state packets
923 brw_upload_invariant_state(struct brw_context
*brw
)
925 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
927 intel_emit_post_sync_nonzero_flush(brw
);
929 /* Select the 3D pipeline (as opposed to media) */
931 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16 | 0);
935 /* Disable depth offset clamping. */
937 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
944 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
950 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
956 OUT_BATCH(brw
->CMD_VF_STATISTICS
<< 16 |
957 (unlikely(INTEL_DEBUG
& DEBUG_STATS
) ? 1 : 0));
961 const struct brw_tracked_state brw_invariant_state
= {
964 .brw
= BRW_NEW_CONTEXT
,
967 .emit
= brw_upload_invariant_state
971 * Define the base addresses which some state is referenced from.
973 * This allows us to avoid having to emit relocations for the objects,
974 * and is actually required for binding table pointers on gen6.
976 * Surface state base address covers binding table pointers and
977 * surface state objects, but not the surfaces that the surface state
980 static void upload_state_base_address( struct brw_context
*brw
)
982 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
983 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
984 * programmed prior to STATE_BASE_ADDRESS.
986 * However, given that the instruction SBA (general state base
987 * address) on this chipset is always set to 0 across X and GL,
988 * maybe this isn't required for us in particular.
992 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
995 intel_emit_post_sync_nonzero_flush(brw
);
998 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
999 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
1000 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
1001 1); /* General State Base Address Modify Enable */
1002 /* Surface state base address:
1003 * BINDING_TABLE_STATE
1006 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
1007 /* Dynamic state base address:
1009 * SAMPLER_BORDER_COLOR_STATE
1010 * CLIP, SF, WM/CC viewport state
1012 * DEPTH_STENCIL_STATE
1014 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
1015 * Disable is clear, which we rely on)
1017 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
1018 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
1020 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
1021 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1022 1); /* Instruction base address: shader kernels (incl. SIP) */
1024 OUT_BATCH(1); /* General state upper bound */
1025 /* Dynamic state upper bound. Although the documentation says that
1026 * programming it to zero will cause it to be ignored, that is a lie.
1027 * If this isn't programmed to a real bound, the sampler border color
1028 * pointer is rejected, causing border color to mysteriously fail.
1030 OUT_BATCH(0xfffff001);
1031 OUT_BATCH(1); /* Indirect object upper bound */
1032 OUT_BATCH(1); /* Instruction access upper bound */
1034 } else if (brw
->gen
== 5) {
1036 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
1037 OUT_BATCH(1); /* General state base address */
1038 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1039 1); /* Surface state base address */
1040 OUT_BATCH(1); /* Indirect object base address */
1041 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1042 1); /* Instruction base address */
1043 OUT_BATCH(0xfffff001); /* General state upper bound */
1044 OUT_BATCH(1); /* Indirect object upper bound */
1045 OUT_BATCH(1); /* Instruction access upper bound */
1049 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1050 OUT_BATCH(1); /* General state base address */
1051 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1052 1); /* Surface state base address */
1053 OUT_BATCH(1); /* Indirect object base address */
1054 OUT_BATCH(1); /* General state upper bound */
1055 OUT_BATCH(1); /* Indirect object upper bound */
1059 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1060 * STATE_BASE_ADDRESS updates require a reissue of:
1062 * 3DSTATE_PIPELINE_POINTERS
1063 * 3DSTATE_BINDING_TABLE_POINTERS
1064 * MEDIA_STATE_POINTERS
1066 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1067 * 1 part 1 says that the folowing packets must be reissued:
1069 * 3DSTATE_CC_POINTERS
1070 * 3DSTATE_BINDING_TABLE_POINTERS
1071 * 3DSTATE_SAMPLER_STATE_POINTERS
1072 * 3DSTATE_VIEWPORT_STATE_POINTERS
1073 * MEDIA_STATE_POINTERS
1075 * Those are always reissued following SBA updates anyway (new
1076 * batch time), except in the case of the program cache BO
1077 * changing. Having a separate state flag makes the sequence more
1081 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
1084 const struct brw_tracked_state brw_state_base_address
= {
1087 .brw
= (BRW_NEW_BATCH
|
1088 BRW_NEW_PROGRAM_CACHE
),
1091 .emit
= upload_state_base_address