src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "intel_regions.h"
  37
  38 #include "brw_context.h"
  39 #include "brw_state.h"
  40 #include "brw_defines.h"
  41
  42 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  43 static void upload_drawing_rect(struct brw_context *brw)
  44 {
  45    struct intel_context *intel = &brw->intel;
  46    struct gl_context *ctx = &intel->ctx;
  47
  48    BEGIN_BATCH(4);
  49    OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
  50    OUT_BATCH(0); /* xmin, ymin */
  51    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  52             ((ctx->DrawBuffer->Height - 1) << 16));
  53    OUT_BATCH(0);
  54    ADVANCE_BATCH();
  55 }
  56
  57 const struct brw_tracked_state brw_drawing_rect = {
  58    .dirty = {
  59       .mesa = _NEW_BUFFERS,
  60       .brw = BRW_NEW_CONTEXT,
  61       .cache = 0
  62    },
  63    .emit = upload_drawing_rect
  64 };
  65
  66 /**
  67  * Upload the binding table pointers, which point each stage's array of surface
  68  * state pointers.
  69  *
  70  * The binding table pointers are relative to the surface state base address,
  71  * which points at the batchbuffer containing the streamed batch state.
  72  */
  73 static void upload_binding_table_pointers(struct brw_context *brw)
  74 {
  75    struct intel_context *intel = &brw->intel;
  76
  77    BEGIN_BATCH(6);
  78    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
  79    OUT_BATCH(brw->vs.bind_bo_offset);
  80    OUT_BATCH(0); /* gs */
  81    OUT_BATCH(0); /* clip */
  82    OUT_BATCH(0); /* sf */
  83    OUT_BATCH(brw->wm.bind_bo_offset);
  84    ADVANCE_BATCH();
  85 }
  86
  87 const struct brw_tracked_state brw_binding_table_pointers = {
  88    .dirty = {
  89       .mesa = 0,
  90       .brw = BRW_NEW_BATCH
  91            | BRW_NEW_VS_BINDING_TABLE
  92            | BRW_NEW_GS_BINDING_TABLE
  93            | BRW_NEW_PS_BINDING_TABLE,
  94       .cache = 0,
  95    },
  96    .emit = upload_binding_table_pointers,
  97 };
  98
  99 /**
 100  * Upload the binding table pointers, which point each stage's array of surface
 101  * state pointers.
 102  *
 103  * The binding table pointers are relative to the surface state base address,
 104  * which points at the batchbuffer containing the streamed batch state.
 105  */
 106 static void upload_gen6_binding_table_pointers(struct brw_context *brw)
 107 {
 108    struct intel_context *intel = &brw->intel;
 109
 110    BEGIN_BATCH(4);
 111    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 112              GEN6_BINDING_TABLE_MODIFY_VS |
 113              GEN6_BINDING_TABLE_MODIFY_GS |
 114              GEN6_BINDING_TABLE_MODIFY_PS |
 115              (4 - 2));
 116    OUT_BATCH(brw->vs.bind_bo_offset); /* vs */
 117    OUT_BATCH(0); /* gs */
 118    OUT_BATCH(brw->wm.bind_bo_offset); /* wm/ps */
 119    ADVANCE_BATCH();
 120 }
 121
 122 const struct brw_tracked_state gen6_binding_table_pointers = {
 123    .dirty = {
 124       .mesa = 0,
 125       .brw = BRW_NEW_BATCH
 126            | BRW_NEW_VS_BINDING_TABLE
 127            | BRW_NEW_GS_BINDING_TABLE
 128            | BRW_NEW_PS_BINDING_TABLE,
 129       .cache = 0,
 130    },
 131    .emit = upload_gen6_binding_table_pointers,
 132 };
 133
 134 /**
 135  * Upload pointers to the per-stage state.
 136  *
 137  * The state pointers in this packet are all relative to the general state
 138  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 139  */
 140 static void upload_pipelined_state_pointers(struct brw_context *brw )
 141 {
 142    struct intel_context *intel = &brw->intel;
 143
 144    if (intel->gen == 5) {
 145       /* Need to flush before changing clip max threads for errata. */
 146       BEGIN_BATCH(1);
 147       OUT_BATCH(MI_FLUSH);
 148       ADVANCE_BATCH();
 149    }
 150
 151    BEGIN_BATCH(7);
 152    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
 153    OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 154              brw->vs.state_offset);
 155    if (brw->gs.prog_active)
 156       OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 157                 brw->gs.state_offset | 1);
 158    else
 159       OUT_BATCH(0);
 160    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 161              brw->clip.state_offset | 1);
 162    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 163              brw->sf.state_offset);
 164    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 165              brw->wm.state_offset);
 166    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 167              brw->cc.state_offset);
 168    ADVANCE_BATCH();
 169
 170    brw->state.dirty.brw |= BRW_NEW_PSP;
 171 }
 172
 173 static void upload_psp_urb_cbs(struct brw_context *brw )
 174 {
 175    upload_pipelined_state_pointers(brw);
 176    brw_upload_urb_fence(brw);
 177    brw_upload_cs_urb_state(brw);
 178 }
 179
 180 const struct brw_tracked_state brw_psp_urb_cbs = {
 181    .dirty = {
 182       .mesa = 0,
 183       .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH,
 184       .cache = (CACHE_NEW_VS_UNIT |
 185                 CACHE_NEW_GS_UNIT |
 186                 CACHE_NEW_GS_PROG |
 187                 CACHE_NEW_CLIP_UNIT |
 188                 CACHE_NEW_SF_UNIT |
 189                 CACHE_NEW_WM_UNIT |
 190                 CACHE_NEW_CC_UNIT)
 191    },
 192    .emit = upload_psp_urb_cbs,
 193 };
 194
 195 static void prepare_depthbuffer(struct brw_context *brw)
 196 {
 197    struct intel_context *intel = &brw->intel;
 198    struct gl_context *ctx = &intel->ctx;
 199    struct gl_framebuffer *fb = ctx->DrawBuffer;
 200    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 201    struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 202
 203    if (drb)
 204       brw_add_validated_bo(brw, drb->region->buffer);
 205    if (drb && drb->hiz_region)
 206       brw_add_validated_bo(brw, drb->hiz_region->buffer);
 207    if (srb)
 208       brw_add_validated_bo(brw, srb->region->buffer);
 209 }
 210
 211 static void emit_depthbuffer(struct brw_context *brw)
 212 {
 213    struct intel_context *intel = &brw->intel;
 214    struct gl_context *ctx = &intel->ctx;
 215    struct gl_framebuffer *fb = ctx->DrawBuffer;
 216    /* _NEW_BUFFERS */
 217    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 218    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 219    struct intel_region *hiz_region = depth_irb ? depth_irb->hiz_region : NULL;
 220    unsigned int len;
 221
 222    /*
 223     * If either depth or stencil buffer has packed depth/stencil format,
 224     * then don't use separate stencil. Emit only a depth buffer.
 225     */
 226    if (depth_irb && depth_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 227       stencil_irb = NULL;
 228    } else if (!depth_irb && stencil_irb
 229               && stencil_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 230       depth_irb = stencil_irb;
 231       stencil_irb = NULL;
 232    }
 233
 234    if (intel->gen >= 6)
 235       len = 7;
 236    else if (intel->is_g4x || intel->gen == 5)
 237       len = 6;
 238    else
 239       len = 5;
 240
 241    if (!depth_irb && !stencil_irb) {
 242       BEGIN_BATCH(len);
 243       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 244       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 245                 (BRW_SURFACE_NULL << 29));
 246       OUT_BATCH(0);
 247       OUT_BATCH(0);
 248       OUT_BATCH(0);
 249
 250       if (intel->is_g4x || intel->gen >= 5)
 251          OUT_BATCH(0);
 252
 253       if (intel->gen >= 6)
 254          OUT_BATCH(0);
 255
 256       ADVANCE_BATCH();
 257
 258    } else if (!depth_irb && stencil_irb) {
 259       /*
 260        * There exists a separate stencil buffer but no depth buffer.
 261        *
 262        * The stencil buffer inherits most of its fields from
 263        * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
 264        * height.
 265        *
 266        * Since the stencil buffer has quirky pitch requirements, its region
 267        * was allocated with half height and double cpp. So we need
 268        * a multiplier of 2 to obtain the surface's real height.
 269        *
 270        * Enable the hiz bit because it and the separate stencil bit must have
 271        * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
 272        * 1.21 "Separate Stencil Enable":
 273        *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
 274        *     Enable must also be enabled.
 275        *
 276        *     [DevGT]: This field must be set to the same value (enabled or
 277        *     disabled) as Hierarchical Depth Buffer Enable
 278        */
 279       assert(intel->has_separate_stencil);
 280       assert(stencil_irb->Base.Format == MESA_FORMAT_S8);
 281
 282       BEGIN_BATCH(len);
 283       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 284       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 285                 (1 << 21) | /* separate stencil enable */
 286                 (1 << 22) | /* hiz enable */
 287                 (BRW_TILEWALK_YMAJOR << 26) |
 288                 (BRW_SURFACE_2D << 29));
 289       OUT_BATCH(0);
 290       OUT_BATCH(((stencil_irb->region->width - 1) << 6) |
 291                  (2 * stencil_irb->region->height - 1) << 19);
 292       OUT_BATCH(0);
 293       OUT_BATCH(0);
 294
 295       if (intel->gen >= 6)
 296          OUT_BATCH(0);
 297
 298       ADVANCE_BATCH();
 299
 300    } else {
 301       struct intel_region *region = depth_irb->region;
 302       unsigned int format;
 303       uint32_t tile_x, tile_y, offset;
 304
 305       /* If using separate stencil, hiz must be enabled. */
 306       assert(!stencil_irb || hiz_region);
 307
 308       switch (region->cpp) {
 309       case 2:
 310          format = BRW_DEPTHFORMAT_D16_UNORM;
 311          break;
 312       case 4:
 313          if (intel->depth_buffer_is_float)
 314             format = BRW_DEPTHFORMAT_D32_FLOAT;
 315          else if (hiz_region)
 316             format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 317          else
 318             format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 319          break;
 320       default:
 321          assert(0);
 322          return;
 323       }
 324
 325       offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y);
 326
 327       assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
 328       assert(!hiz_region || region->tiling == I915_TILING_Y);
 329
 330       BEGIN_BATCH(len);
 331       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 332       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 333                 (format << 18) |
 334                 ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */
 335                 ((hiz_region ? 1 : 0) << 22) | /* hiz enable */
 336                 (BRW_TILEWALK_YMAJOR << 26) |
 337                 ((region->tiling != I915_TILING_NONE) << 27) |
 338                 (BRW_SURFACE_2D << 29));
 339       OUT_RELOC(region->buffer,
 340                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 341                 offset);
 342       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 343                 ((region->width - 1) << 6) |
 344                 ((region->height - 1) << 19));
 345       OUT_BATCH(0);
 346
 347       if (intel->is_g4x || intel->gen >= 5)
 348          OUT_BATCH(tile_x | (tile_y << 16));
 349       else
 350          assert(tile_x == 0 && tile_y == 0);
 351
 352       if (intel->gen >= 6)
 353          OUT_BATCH(0);
 354
 355       ADVANCE_BATCH();
 356    }
 357
 358    /* Emit hiz buffer. */
 359    if (hiz_region || stencil_irb) {
 360       BEGIN_BATCH(3);
 361       OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 362       OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 363       OUT_RELOC(hiz_region->buffer,
 364                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 365                 0);
 366       ADVANCE_BATCH();
 367    }
 368
 369    /* Emit stencil buffer. */
 370    if (hiz_region || stencil_irb) {
 371       BEGIN_BATCH(3);
 372       OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 373       OUT_BATCH(stencil_irb->region->pitch * stencil_irb->region->cpp - 1);
 374       OUT_RELOC(stencil_irb->region->buffer,
 375                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 376                 0);
 377       ADVANCE_BATCH();
 378    }
 379
 380    /*
 381     * On Gen >= 6, emit clear params for safety. If using hiz, then clear
 382     * params must be emitted.
 383     *
 384     * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
 385     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
 386     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 387     */
 388    if (intel->gen >= 6 || hiz_region) {
 389       BEGIN_BATCH(2);
 390       OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
 391       OUT_BATCH(0);
 392       ADVANCE_BATCH();
 393    }
 394 }
 395
 396 const struct brw_tracked_state brw_depthbuffer = {
 397    .dirty = {
 398       .mesa = _NEW_BUFFERS,
 399       .brw = BRW_NEW_BATCH,
 400       .cache = 0,
 401    },
 402    .prepare = prepare_depthbuffer,
 403    .emit = emit_depthbuffer,
 404 };
 405
 406
 407
 408 /***********************************************************************
 409  * Polygon stipple packet
 410  */
 411
 412 static void upload_polygon_stipple(struct brw_context *brw)
 413 {
 414    struct intel_context *intel = &brw->intel;
 415    struct gl_context *ctx = &brw->intel.ctx;
 416    GLuint i;
 417
 418    if (!ctx->Polygon.StippleFlag)
 419       return;
 420
 421    BEGIN_BATCH(33);
 422    OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
 423
 424    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 425     * row first.  If we're rendering to a window (i.e. the
 426     * default frame buffer object, 0), then we need to invert
 427     * it to match our pixel layout.  But if we're rendering
 428     * to a FBO (i.e. any named frame buffer object), we *don't*
 429     * need to invert - we already match the layout.
 430     */
 431    if (ctx->DrawBuffer->Name == 0) {
 432       for (i = 0; i < 32; i++)
 433           OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
 434    }
 435    else {
 436       for (i = 0; i < 32; i++)
 437          OUT_BATCH(ctx->PolygonStipple[i]);
 438    }
 439    CACHED_BATCH();
 440 }
 441
 442 const struct brw_tracked_state brw_polygon_stipple = {
 443    .dirty = {
 444       .mesa = _NEW_POLYGONSTIPPLE,
 445       .brw = BRW_NEW_CONTEXT,
 446       .cache = 0
 447    },
 448    .emit = upload_polygon_stipple
 449 };
 450
 451
 452 /***********************************************************************
 453  * Polygon stipple offset packet
 454  */
 455
 456 static void upload_polygon_stipple_offset(struct brw_context *brw)
 457 {
 458    struct intel_context *intel = &brw->intel;
 459    struct gl_context *ctx = &brw->intel.ctx;
 460
 461    if (!ctx->Polygon.StippleFlag)
 462       return;
 463
 464    BEGIN_BATCH(2);
 465    OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
 466
 467    /* If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 468     * we have to invert the Y axis in order to match the OpenGL
 469     * pixel coordinate system, and our offset must be matched
 470     * to the window position.  If we're drawing to a FBO
 471     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 472     * system works just fine, and there's no window system to
 473     * worry about.
 474     */
 475    if (brw->intel.ctx.DrawBuffer->Name == 0)
 476       OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
 477    else
 478       OUT_BATCH(0);
 479    CACHED_BATCH();
 480 }
 481
 482 #define _NEW_WINDOW_POS 0x40000000
 483
 484 const struct brw_tracked_state brw_polygon_stipple_offset = {
 485    .dirty = {
 486       .mesa = _NEW_WINDOW_POS | _NEW_POLYGONSTIPPLE,
 487       .brw = BRW_NEW_CONTEXT,
 488       .cache = 0
 489    },
 490    .emit = upload_polygon_stipple_offset
 491 };
 492
 493 /**********************************************************************
 494  * AA Line parameters
 495  */
 496 static void upload_aa_line_parameters(struct brw_context *brw)
 497 {
 498    struct intel_context *intel = &brw->intel;
 499    struct gl_context *ctx = &brw->intel.ctx;
 500
 501    if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
 502       return;
 503
 504    OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
 505    /* use legacy aa line coverage computation */
 506    OUT_BATCH(0);
 507    OUT_BATCH(0);
 508    CACHED_BATCH();
 509 }
 510
 511 const struct brw_tracked_state brw_aa_line_parameters = {
 512    .dirty = {
 513       .mesa = _NEW_LINE,
 514       .brw = BRW_NEW_CONTEXT,
 515       .cache = 0
 516    },
 517    .emit = upload_aa_line_parameters
 518 };
 519
 520 /***********************************************************************
 521  * Line stipple packet
 522  */
 523
 524 static void upload_line_stipple(struct brw_context *brw)
 525 {
 526    struct intel_context *intel = &brw->intel;
 527    struct gl_context *ctx = &brw->intel.ctx;
 528    GLfloat tmp;
 529    GLint tmpi;
 530
 531    if (!ctx->Line.StippleFlag)
 532       return;
 533
 534    BEGIN_BATCH(3);
 535    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
 536    OUT_BATCH(ctx->Line.StipplePattern);
 537    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 538    tmpi = tmp * (1<<13);
 539    OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
 540    CACHED_BATCH();
 541 }
 542
 543 const struct brw_tracked_state brw_line_stipple = {
 544    .dirty = {
 545       .mesa = _NEW_LINE,
 546       .brw = BRW_NEW_CONTEXT,
 547       .cache = 0
 548    },
 549    .emit = upload_line_stipple
 550 };
 551
 552
 553 /***********************************************************************
 554  * Misc invarient state packets
 555  */
 556
 557 static void upload_invarient_state( struct brw_context *brw )
 558 {
 559    struct intel_context *intel = &brw->intel;
 560
 561    {
 562       /* 0x61040000  Pipeline Select */
 563       /*     PipelineSelect            : 0 */
 564       struct brw_pipeline_select ps;
 565
 566       memset(&ps, 0, sizeof(ps));
 567       ps.header.opcode = brw->CMD_PIPELINE_SELECT;
 568       ps.header.pipeline_select = 0;
 569       BRW_BATCH_STRUCT(brw, &ps);
 570    }
 571
 572    if (intel->gen < 6) {
 573       struct brw_global_depth_offset_clamp gdo;
 574       memset(&gdo, 0, sizeof(gdo));
 575
 576       /* Disable depth offset clamping.
 577        */
 578       gdo.header.opcode = _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP;
 579       gdo.header.length = sizeof(gdo)/4 - 2;
 580       gdo.depth_offset_clamp = 0.0;
 581
 582       BRW_BATCH_STRUCT(brw, &gdo);
 583    }
 584
 585    if (intel->gen >= 6) {
 586       int i;
 587       int len = intel->gen >= 7 ? 4 : 3;
 588
 589       BEGIN_BATCH(len);
 590       OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
 591       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
 592                 MS_NUMSAMPLES_1);
 593       OUT_BATCH(0); /* positions for 4/8-sample */
 594       if (intel->gen >= 7)
 595          OUT_BATCH(0);
 596       ADVANCE_BATCH();
 597
 598       BEGIN_BATCH(2);
 599       OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
 600       OUT_BATCH(1);
 601       ADVANCE_BATCH();
 602
 603       if (intel->gen < 7) {
 604          for (i = 0; i < 4; i++) {
 605             BEGIN_BATCH(4);
 606             OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
 607             OUT_BATCH(i << SVB_INDEX_SHIFT);
 608             OUT_BATCH(0);
 609             OUT_BATCH(0xffffffff);
 610             ADVANCE_BATCH();
 611          }
 612       }
 613    }
 614
 615    /* 0x61020000  State Instruction Pointer */
 616    {
 617       struct brw_system_instruction_pointer sip;
 618       memset(&sip, 0, sizeof(sip));
 619
 620       sip.header.opcode = CMD_STATE_INSN_POINTER;
 621       sip.header.length = 0;
 622       sip.bits0.pad = 0;
 623       sip.bits0.system_instruction_pointer = 0;
 624       BRW_BATCH_STRUCT(brw, &sip);
 625    }
 626
 627
 628    {
 629       struct brw_vf_statistics vfs;
 630       memset(&vfs, 0, sizeof(vfs));
 631
 632       vfs.opcode = brw->CMD_VF_STATISTICS;
 633       if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 634          vfs.statistics_enable = 1;
 635
 636       BRW_BATCH_STRUCT(brw, &vfs);
 637    }
 638 }
 639
 640 const struct brw_tracked_state brw_invarient_state = {
 641    .dirty = {
 642       .mesa = 0,
 643       .brw = BRW_NEW_CONTEXT,
 644       .cache = 0
 645    },
 646    .emit = upload_invarient_state
 647 };
 648
 649 /**
 650  * Define the base addresses which some state is referenced from.
 651  *
 652  * This allows us to avoid having to emit relocations for the objects,
 653  * and is actually required for binding table pointers on gen6.
 654  *
 655  * Surface state base address covers binding table pointers and
 656  * surface state objects, but not the surfaces that the surface state
 657  * objects point to.
 658  */
 659 static void upload_state_base_address( struct brw_context *brw )
 660 {
 661    struct intel_context *intel = &brw->intel;
 662
 663    if (intel->gen >= 6) {
 664        BEGIN_BATCH(10);
 665        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
 666        /* General state base address: stateless DP read/write requests */
 667        OUT_BATCH(1);
 668        /* Surface state base address:
 669         * BINDING_TABLE_STATE
 670         * SURFACE_STATE
 671         */
 672        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
 673         /* Dynamic state base address:
 674          * SAMPLER_STATE
 675          * SAMPLER_BORDER_COLOR_STATE
 676          * CLIP, SF, WM/CC viewport state
 677          * COLOR_CALC_STATE
 678          * DEPTH_STENCIL_STATE
 679          * BLEND_STATE
 680          * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
 681          * Disable is clear, which we rely on)
 682          */
 683        OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
 684                                    I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
 685
 686        OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
 687        OUT_BATCH(1); /* Instruction base address: shader kernels (incl. SIP) */
 688        OUT_BATCH(1); /* General state upper bound */
 689        OUT_BATCH(1); /* Dynamic state upper bound */
 690        OUT_BATCH(1); /* Indirect object upper bound */
 691        OUT_BATCH(1); /* Instruction access upper bound */
 692        ADVANCE_BATCH();
 693    } else if (intel->gen == 5) {
 694        BEGIN_BATCH(8);
 695        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 696        OUT_BATCH(1); /* General state base address */
 697        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 698                  1); /* Surface state base address */
 699        OUT_BATCH(1); /* Indirect object base address */
 700        OUT_BATCH(1); /* Instruction base address */
 701        OUT_BATCH(1); /* General state upper bound */
 702        OUT_BATCH(1); /* Indirect object upper bound */
 703        OUT_BATCH(1); /* Instruction access upper bound */
 704        ADVANCE_BATCH();
 705    } else {
 706        BEGIN_BATCH(6);
 707        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 708        OUT_BATCH(1); /* General state base address */
 709        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 710                  1); /* Surface state base address */
 711        OUT_BATCH(1); /* Indirect object base address */
 712        OUT_BATCH(1); /* General state upper bound */
 713        OUT_BATCH(1); /* Indirect object upper bound */
 714        ADVANCE_BATCH();
 715    }
 716 }
 717
 718 const struct brw_tracked_state brw_state_base_address = {
 719    .dirty = {
 720       .mesa = 0,
 721       .brw = BRW_NEW_BATCH,
 722       .cache = 0,
 723    },
 724    .emit = upload_state_base_address
 725 };