src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_regions.h"
  36
  37 #include "brw_context.h"
  38 #include "brw_state.h"
  39 #include "brw_defines.h"
  40
  41
  42
  43
  44
  45 /***********************************************************************
  46  * Blend color
  47  */
  48
  49 static void upload_blend_constant_color(struct brw_context *brw)
  50 {
  51    struct brw_blend_constant_color bcc;
  52
  53    memset(&bcc, 0, sizeof(bcc));
  54    bcc.header.opcode = CMD_BLEND_CONSTANT_COLOR;
  55    bcc.header.length = sizeof(bcc)/4-2;
  56    bcc.blend_constant_color[0] = brw->attribs.Color->BlendColor[0];
  57    bcc.blend_constant_color[1] = brw->attribs.Color->BlendColor[1];
  58    bcc.blend_constant_color[2] = brw->attribs.Color->BlendColor[2];
  59    bcc.blend_constant_color[3] = brw->attribs.Color->BlendColor[3];
  60
  61    BRW_CACHED_BATCH_STRUCT(brw, &bcc);
  62 }
  63
  64
  65 const struct brw_tracked_state brw_blend_constant_color = {
  66    .dirty = {
  67       .mesa = _NEW_COLOR,
  68       .brw = 0,
  69       .cache = 0
  70    },
  71    .update = upload_blend_constant_color
  72 };
  73
  74 /***********************************************************************
  75  * Drawing rectangle -- Need for AUB file only.
  76  */
  77 static void upload_drawing_rect(struct brw_context *brw)
  78 {
  79    struct intel_context *intel = &brw->intel;
  80    struct brw_drawrect bdr;
  81    int x1, y1;
  82    int x2, y2;
  83
  84    /* If there is a single cliprect, set it here.  Otherwise iterate
  85     * over them in brw_draw_prim().
  86     */
  87    if (brw->intel.numClipRects > 1)
  88       return;
  89
  90    x1 = brw->intel.pClipRects[0].x1;
  91    y1 = brw->intel.pClipRects[0].y1;
  92    x2 = brw->intel.pClipRects[0].x2;
  93    y2 = brw->intel.pClipRects[0].y2;
  94
  95    if (x1 < 0) x1 = 0;
  96    if (y1 < 0) y1 = 0;
  97    if (x2 > intel->intelScreen->width) x2 = intel->intelScreen->width;
  98    if (y2 > intel->intelScreen->height) y2 = intel->intelScreen->height;
  99
 100    memset(&bdr, 0, sizeof(bdr));
 101    bdr.header.opcode = CMD_DRAW_RECT;
 102    bdr.header.length = sizeof(bdr)/4 - 2;
 103    bdr.xmin = x1;
 104    bdr.ymin = y1;
 105    bdr.xmax = x2;
 106    bdr.ymax = y2;
 107    bdr.xorg = intel->drawX;
 108    bdr.yorg = intel->drawY;
 109
 110    /* Can't use BRW_CACHED_BATCH_STRUCT because this is also emitted
 111     * uncached in brw_draw.c:
 112     */
 113    BRW_BATCH_STRUCT(brw, &bdr);
 114 }
 115
 116 const struct brw_tracked_state brw_drawing_rect = {
 117    .dirty = {
 118       .mesa = _NEW_WINDOW_POS,
 119       .brw = 0,
 120       .cache = 0
 121    },
 122    .update = upload_drawing_rect
 123 };
 124
 125 /**
 126  * Upload the binding table pointers, which point each stage's array of surface
 127  * state pointers.
 128  *
 129  * The binding table pointers are relative to the surface state base address,
 130  * which is 0.
 131  */
 132 static void upload_binding_table_pointers(struct brw_context *brw)
 133 {
 134    struct intel_context *intel = &brw->intel;
 135
 136    BEGIN_BATCH(6, INTEL_BATCH_NO_CLIPRECTS);
 137    OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2));
 138    OUT_BATCH(0); /* vs */
 139    OUT_BATCH(0); /* gs */
 140    OUT_BATCH(0); /* clip */
 141    OUT_BATCH(0); /* sf */
 142    OUT_RELOC(brw->wm.bind_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
 143    ADVANCE_BATCH();
 144 }
 145
 146 const struct brw_tracked_state brw_binding_table_pointers = {
 147    .update = upload_binding_table_pointers,
 148    .always_update = GL_TRUE, /* Has a relocation in the batchbuffer */
 149 };
 150
 151
 152 /**
 153  * Upload pointers to the per-stage state.
 154  *
 155  * The state pointers in this packet are all relative to the general state
 156  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 157  */
 158 static void upload_pipelined_state_pointers(struct brw_context *brw )
 159 {
 160    struct intel_context *intel = &brw->intel;
 161
 162    BEGIN_BATCH(7, INTEL_BATCH_NO_CLIPRECTS);
 163    OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
 164    OUT_RELOC(brw->vs.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
 165    if (brw->gs.prog_active)
 166       OUT_RELOC(brw->gs.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 1);
 167    else
 168       OUT_BATCH(0);
 169    if (!brw->metaops.active)
 170       OUT_RELOC(brw->clip.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 1);
 171    else
 172       OUT_BATCH(0);
 173    OUT_RELOC(brw->sf.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
 174    OUT_RELOC(brw->wm.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
 175    OUT_RELOC(brw->cc.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
 176    ADVANCE_BATCH();
 177
 178    brw->state.dirty.brw |= BRW_NEW_PSP;
 179 }
 180
 181 #if 0
 182 /* Combined into brw_psp_urb_cbs */
 183 const struct brw_tracked_state brw_pipelined_state_pointers = {
 184    .dirty = {
 185       .mesa = 0,
 186       .brw = BRW_NEW_METAOPS,
 187       .cache = (CACHE_NEW_VS_UNIT |
 188                 CACHE_NEW_GS_UNIT |
 189                 CACHE_NEW_GS_PROG |
 190                 CACHE_NEW_CLIP_UNIT |
 191                 CACHE_NEW_SF_UNIT |
 192                 CACHE_NEW_WM_UNIT |
 193                 CACHE_NEW_CC_UNIT)
 194    },
 195    .update = upload_pipelined_state_pointers
 196    .always_update = GL_TRUE, /* Has a relocation in the batchbuffer */
 197 };
 198 #endif
 199
 200 static void upload_psp_urb_cbs(struct brw_context *brw )
 201 {
 202    upload_pipelined_state_pointers(brw);
 203    brw_upload_urb_fence(brw);
 204    brw_upload_constant_buffer_state(brw);
 205 }
 206
 207
 208 const struct brw_tracked_state brw_psp_urb_cbs = {
 209    .dirty = {
 210       .mesa = 0,
 211       .brw = BRW_NEW_URB_FENCE | BRW_NEW_METAOPS,
 212       .cache = (CACHE_NEW_VS_UNIT |
 213                 CACHE_NEW_GS_UNIT |
 214                 CACHE_NEW_GS_PROG |
 215                 CACHE_NEW_CLIP_UNIT |
 216                 CACHE_NEW_SF_UNIT |
 217                 CACHE_NEW_WM_UNIT |
 218                 CACHE_NEW_CC_UNIT)
 219    },
 220    .update = upload_psp_urb_cbs,
 221    .always_update = GL_TRUE, /* psp has relocations. */
 222 };
 223
 224 /**
 225  * Upload the depthbuffer offset and format.
 226  *
 227  * We have to do this per state validation as we need to emit the relocation
 228  * in the batch buffer.
 229  */
 230 static void upload_depthbuffer(struct brw_context *brw)
 231 {
 232    struct intel_context *intel = &brw->intel;
 233    struct intel_region *region = brw->state.depth_region;
 234
 235    if (region == NULL) {
 236       BEGIN_BATCH(5, INTEL_BATCH_NO_CLIPRECTS);
 237       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (5 - 2));
 238       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 239                 (BRW_SURFACE_NULL << 29));
 240       OUT_BATCH(0);
 241       OUT_BATCH(0);
 242       OUT_BATCH(0);
 243       ADVANCE_BATCH();
 244    } else {
 245       unsigned int format;
 246
 247       switch (region->cpp) {
 248       case 2:
 249          format = BRW_DEPTHFORMAT_D16_UNORM;
 250          break;
 251       case 4:
 252          if (intel->depth_buffer_is_float)
 253             format = BRW_DEPTHFORMAT_D32_FLOAT;
 254          else
 255             format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 256          break;
 257       default:
 258          assert(0);
 259          return;
 260       }
 261
 262       BEGIN_BATCH(5, INTEL_BATCH_NO_CLIPRECTS);
 263       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (5 - 2));
 264       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 265                 (format << 18) |
 266                 (BRW_TILEWALK_YMAJOR << 26) |
 267                 (region->tiled << 27) |
 268                 (BRW_SURFACE_2D << 29));
 269       OUT_RELOC(region->buffer,
 270                 DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0);
 271       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 272                 ((region->pitch - 1) << 6) |
 273                 ((region->height - 1) << 19));
 274       OUT_BATCH(0);
 275       ADVANCE_BATCH();
 276    }
 277 }
 278
 279 const struct brw_tracked_state brw_depthbuffer = {
 280    .update = upload_depthbuffer,
 281    .always_update = GL_TRUE,
 282 };
 283
 284
 285
 286 /***********************************************************************
 287  * Polygon stipple packet
 288  */
 289
 290 static void upload_polygon_stipple(struct brw_context *brw)
 291 {
 292    struct brw_polygon_stipple bps;
 293    GLuint i;
 294
 295    memset(&bps, 0, sizeof(bps));
 296    bps.header.opcode = CMD_POLY_STIPPLE_PATTERN;
 297    bps.header.length = sizeof(bps)/4-2;
 298
 299    for (i = 0; i < 32; i++)
 300       bps.stipple[i] = brw->attribs.PolygonStipple[31 - i]; /* invert */
 301
 302    BRW_CACHED_BATCH_STRUCT(brw, &bps);
 303 }
 304
 305 const struct brw_tracked_state brw_polygon_stipple = {
 306    .dirty = {
 307       .mesa = _NEW_POLYGONSTIPPLE,
 308       .brw = 0,
 309       .cache = 0
 310    },
 311    .update = upload_polygon_stipple
 312 };
 313
 314
 315 /***********************************************************************
 316  * Polygon stipple offset packet
 317  */
 318
 319 static void upload_polygon_stipple_offset(struct brw_context *brw)
 320 {
 321    __DRIdrawablePrivate *dPriv = brw->intel.driDrawable;
 322    struct brw_polygon_stipple_offset bpso;
 323
 324    memset(&bpso, 0, sizeof(bpso));
 325    bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
 326    bpso.header.length = sizeof(bpso)/4-2;
 327
 328    bpso.bits0.x_offset = (32 - (dPriv->x & 31)) & 31;
 329    bpso.bits0.y_offset = (32 - ((dPriv->y + dPriv->h) & 31)) & 31;
 330
 331    BRW_CACHED_BATCH_STRUCT(brw, &bpso);
 332 }
 333
 334 const struct brw_tracked_state brw_polygon_stipple_offset = {
 335    .dirty = {
 336       .mesa = _NEW_WINDOW_POS,
 337       .brw = 0,
 338       .cache = 0
 339    },
 340    .update = upload_polygon_stipple_offset
 341 };
 342
 343 /***********************************************************************
 344  * Line stipple packet
 345  */
 346
 347 static void upload_line_stipple(struct brw_context *brw)
 348 {
 349    struct brw_line_stipple bls;
 350    GLfloat tmp;
 351    GLint tmpi;
 352
 353    memset(&bls, 0, sizeof(bls));
 354    bls.header.opcode = CMD_LINE_STIPPLE_PATTERN;
 355    bls.header.length = sizeof(bls)/4 - 2;
 356
 357    bls.bits0.pattern = brw->attribs.Line->StipplePattern;
 358    bls.bits1.repeat_count = brw->attribs.Line->StippleFactor;
 359
 360    tmp = 1.0 / (GLfloat) brw->attribs.Line->StippleFactor;
 361    tmpi = tmp * (1<<13);
 362
 363
 364    bls.bits1.inverse_repeat_count = tmpi;
 365
 366    BRW_CACHED_BATCH_STRUCT(brw, &bls);
 367 }
 368
 369 const struct brw_tracked_state brw_line_stipple = {
 370    .dirty = {
 371       .mesa = _NEW_LINE,
 372       .brw = 0,
 373       .cache = 0
 374    },
 375    .update = upload_line_stipple
 376 };
 377
 378
 379
 380 /***********************************************************************
 381  * Misc constant state packets
 382  */
 383
 384 static void upload_pipe_control(struct brw_context *brw)
 385 {
 386    struct brw_pipe_control pc;
 387
 388    return;
 389
 390    memset(&pc, 0, sizeof(pc));
 391
 392    pc.header.opcode = CMD_PIPE_CONTROL;
 393    pc.header.length = sizeof(pc)/4 - 2;
 394    pc.header.post_sync_operation = PIPE_CONTROL_NOWRITE;
 395
 396    pc.header.instruction_state_cache_flush_enable = 1;
 397
 398    pc.bits1.dest_addr_type = PIPE_CONTROL_GTTWRITE_GLOBAL;
 399
 400    BRW_BATCH_STRUCT(brw, &pc);
 401 }
 402
 403 const struct brw_tracked_state brw_pipe_control = {
 404    .dirty = {
 405       .mesa = 0,
 406       .brw = BRW_NEW_CONTEXT,
 407       .cache = 0
 408    },
 409    .update = upload_pipe_control
 410 };
 411
 412
 413 /***********************************************************************
 414  * Misc invarient state packets
 415  */
 416
 417 static void upload_invarient_state( struct brw_context *brw )
 418 {
 419    {
 420       /* 0x61040000  Pipeline Select */
 421       /*     PipelineSelect            : 0 */
 422       struct brw_pipeline_select ps;
 423
 424       memset(&ps, 0, sizeof(ps));
 425       ps.header.opcode = CMD_PIPELINE_SELECT;
 426       ps.header.pipeline_select = 0;
 427       BRW_BATCH_STRUCT(brw, &ps);
 428    }
 429
 430    {
 431       struct brw_global_depth_offset_clamp gdo;
 432       memset(&gdo, 0, sizeof(gdo));
 433
 434       /* Disable depth offset clamping.
 435        */
 436       gdo.header.opcode = CMD_GLOBAL_DEPTH_OFFSET_CLAMP;
 437       gdo.header.length = sizeof(gdo)/4 - 2;
 438       gdo.depth_offset_clamp = 0.0;
 439
 440       BRW_BATCH_STRUCT(brw, &gdo);
 441    }
 442
 443
 444    /* 0x61020000  State Instruction Pointer */
 445    {
 446       struct brw_system_instruction_pointer sip;
 447       memset(&sip, 0, sizeof(sip));
 448
 449       sip.header.opcode = CMD_STATE_INSN_POINTER;
 450       sip.header.length = 0;
 451       sip.bits0.pad = 0;
 452       sip.bits0.system_instruction_pointer = 0;
 453       BRW_BATCH_STRUCT(brw, &sip);
 454    }
 455
 456
 457    {
 458       struct brw_vf_statistics vfs;
 459       memset(&vfs, 0, sizeof(vfs));
 460
 461       vfs.opcode = CMD_VF_STATISTICS;
 462       if (INTEL_DEBUG & DEBUG_STATS)
 463          vfs.statistics_enable = 1;
 464
 465       BRW_BATCH_STRUCT(brw, &vfs);
 466    }
 467 }
 468
 469 const struct brw_tracked_state brw_invarient_state = {
 470    .dirty = {
 471       .mesa = 0,
 472       .brw = BRW_NEW_CONTEXT,
 473       .cache = 0
 474    },
 475    .update = upload_invarient_state
 476 };
 477
 478 /**
 479  * Define the base addresses which some state is referenced from.
 480  *
 481  * This allows us to avoid having to emit relocations in many places for
 482  * cached state, and instead emit pointers inside of large, mostly-static
 483  * state pools.  This comes at the expense of memory, and more expensive cache
 484  * misses.
 485  */
 486 static void upload_state_base_address( struct brw_context *brw )
 487 {
 488    struct intel_context *intel = &brw->intel;
 489
 490    /* Output the structure (brw_state_base_address) directly to the
 491     * batchbuffer, so we can emit relocations inline.
 492     */
 493    BEGIN_BATCH(6, INTEL_BATCH_NO_CLIPRECTS);
 494    OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 495    OUT_BATCH(1); /* General state base address */
 496    OUT_BATCH(1); /* Surface state base address */
 497    OUT_BATCH(1); /* Indirect object base address */
 498    OUT_BATCH(1); /* General state upper bound */
 499    OUT_BATCH(1); /* Indirect object upper bound */
 500    ADVANCE_BATCH();
 501 }
 502
 503 const struct brw_tracked_state brw_state_base_address = {
 504    .dirty = {
 505       .mesa = 0,
 506       .brw = BRW_NEW_CONTEXT,
 507       .cache = 0,
 508    },
 509    .update = upload_state_base_address
 510 };