src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_fbo.h"
  36 #include "intel_mipmap_tree.h"
  37 #include "intel_regions.h"
  38
  39 #include "brw_context.h"
  40 #include "brw_state.h"
  41 #include "brw_defines.h"
  42
  43 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  44 static void upload_drawing_rect(struct brw_context *brw)
  45 {
  46    struct intel_context *intel = &brw->intel;
  47    struct gl_context *ctx = &intel->ctx;
  48
  49    BEGIN_BATCH(4);
  50    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
  51    OUT_BATCH(0); /* xmin, ymin */
  52    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  53             ((ctx->DrawBuffer->Height - 1) << 16));
  54    OUT_BATCH(0);
  55    ADVANCE_BATCH();
  56 }
  57
  58 const struct brw_tracked_state brw_drawing_rect = {
  59    .dirty = {
  60       .mesa = _NEW_BUFFERS,
  61       .brw = BRW_NEW_CONTEXT,
  62       .cache = 0
  63    },
  64    .emit = upload_drawing_rect
  65 };
  66
  67 /**
  68  * Upload the binding table pointers, which point each stage's array of surface
  69  * state pointers.
  70  *
  71  * The binding table pointers are relative to the surface state base address,
  72  * which points at the batchbuffer containing the streamed batch state.
  73  */
  74 static void upload_binding_table_pointers(struct brw_context *brw)
  75 {
  76    struct intel_context *intel = &brw->intel;
  77
  78    BEGIN_BATCH(6);
  79    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
  80    OUT_BATCH(brw->bind.bo_offset);
  81    OUT_BATCH(0); /* gs */
  82    OUT_BATCH(0); /* clip */
  83    OUT_BATCH(0); /* sf */
  84    OUT_BATCH(brw->bind.bo_offset);
  85    ADVANCE_BATCH();
  86 }
  87
  88 const struct brw_tracked_state brw_binding_table_pointers = {
  89    .dirty = {
  90       .mesa = 0,
  91       .brw = (BRW_NEW_BATCH |
  92               BRW_NEW_STATE_BASE_ADDRESS |
  93               BRW_NEW_VS_BINDING_TABLE |
  94               BRW_NEW_GS_BINDING_TABLE |
  95               BRW_NEW_PS_BINDING_TABLE),
  96       .cache = 0,
  97    },
  98    .emit = upload_binding_table_pointers,
  99 };
 100
 101 /**
 102  * Upload the binding table pointers, which point each stage's array of surface
 103  * state pointers.
 104  *
 105  * The binding table pointers are relative to the surface state base address,
 106  * which points at the batchbuffer containing the streamed batch state.
 107  */
 108 static void upload_gen6_binding_table_pointers(struct brw_context *brw)
 109 {
 110    struct intel_context *intel = &brw->intel;
 111
 112    BEGIN_BATCH(4);
 113    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 |
 114              GEN6_BINDING_TABLE_MODIFY_VS |
 115              GEN6_BINDING_TABLE_MODIFY_GS |
 116              GEN6_BINDING_TABLE_MODIFY_PS |
 117              (4 - 2));
 118    OUT_BATCH(brw->bind.bo_offset); /* vs */
 119    OUT_BATCH(0); /* gs */
 120    OUT_BATCH(brw->bind.bo_offset); /* wm/ps */
 121    ADVANCE_BATCH();
 122 }
 123
 124 const struct brw_tracked_state gen6_binding_table_pointers = {
 125    .dirty = {
 126       .mesa = 0,
 127       .brw = (BRW_NEW_BATCH |
 128               BRW_NEW_STATE_BASE_ADDRESS |
 129               BRW_NEW_VS_BINDING_TABLE |
 130               BRW_NEW_GS_BINDING_TABLE |
 131               BRW_NEW_PS_BINDING_TABLE),
 132       .cache = 0,
 133    },
 134    .emit = upload_gen6_binding_table_pointers,
 135 };
 136
 137 /**
 138  * Upload pointers to the per-stage state.
 139  *
 140  * The state pointers in this packet are all relative to the general state
 141  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 142  */
 143 static void upload_pipelined_state_pointers(struct brw_context *brw )
 144 {
 145    struct intel_context *intel = &brw->intel;
 146
 147    if (intel->gen == 5) {
 148       /* Need to flush before changing clip max threads for errata. */
 149       BEGIN_BATCH(1);
 150       OUT_BATCH(MI_FLUSH);
 151       ADVANCE_BATCH();
 152    }
 153
 154    BEGIN_BATCH(7);
 155    OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
 156    OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 157              brw->vs.state_offset);
 158    if (brw->gs.prog_active)
 159       OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 160                 brw->gs.state_offset | 1);
 161    else
 162       OUT_BATCH(0);
 163    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 164              brw->clip.state_offset | 1);
 165    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 166              brw->sf.state_offset);
 167    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 168              brw->wm.state_offset);
 169    OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 170              brw->cc.state_offset);
 171    ADVANCE_BATCH();
 172
 173    brw->state.dirty.brw |= BRW_NEW_PSP;
 174 }
 175
 176 static void upload_psp_urb_cbs(struct brw_context *brw )
 177 {
 178    upload_pipelined_state_pointers(brw);
 179    brw_upload_urb_fence(brw);
 180    brw_upload_cs_urb_state(brw);
 181 }
 182
 183 const struct brw_tracked_state brw_psp_urb_cbs = {
 184    .dirty = {
 185       .mesa = 0,
 186       .brw = (BRW_NEW_URB_FENCE |
 187               BRW_NEW_BATCH |
 188               BRW_NEW_STATE_BASE_ADDRESS),
 189       .cache = (CACHE_NEW_VS_UNIT |
 190                 CACHE_NEW_GS_UNIT |
 191                 CACHE_NEW_GS_PROG |
 192                 CACHE_NEW_CLIP_UNIT |
 193                 CACHE_NEW_SF_UNIT |
 194                 CACHE_NEW_WM_UNIT |
 195                 CACHE_NEW_CC_UNIT)
 196    },
 197    .emit = upload_psp_urb_cbs,
 198 };
 199
 200 uint32_t
 201 brw_depthbuffer_format(struct brw_context *brw)
 202 {
 203    struct intel_context *intel = &brw->intel;
 204    struct gl_context *ctx = &intel->ctx;
 205    struct gl_framebuffer *fb = ctx->DrawBuffer;
 206    struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 207    struct intel_renderbuffer *srb;
 208
 209    if (!drb &&
 210        (srb = intel_get_renderbuffer(fb, BUFFER_STENCIL)) &&
 211        srb->Base.Format == MESA_FORMAT_S8_Z24) {
 212       drb = srb;
 213    }
 214
 215    switch (drb->Base.Format) {
 216    case MESA_FORMAT_Z16:
 217       return BRW_DEPTHFORMAT_D16_UNORM;
 218    case MESA_FORMAT_Z32_FLOAT:
 219       return BRW_DEPTHFORMAT_D32_FLOAT;
 220    case MESA_FORMAT_X8_Z24:
 221       return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 222    case MESA_FORMAT_S8_Z24:
 223       return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 224    default:
 225       _mesa_problem(ctx, "Unexpected depth format %s\n",
 226                     _mesa_get_format_name(drb->Base.Format));
 227       return BRW_DEPTHFORMAT_D16_UNORM;
 228    }
 229 }
 230
 231 static void emit_depthbuffer(struct brw_context *brw)
 232 {
 233    struct intel_context *intel = &brw->intel;
 234    struct gl_context *ctx = &intel->ctx;
 235    struct gl_framebuffer *fb = ctx->DrawBuffer;
 236    /* _NEW_BUFFERS */
 237    struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
 238    struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
 239    struct intel_region *hiz_region = NULL;
 240    unsigned int len;
 241
 242    if (depth_irb &&
 243        depth_irb->mt &&
 244        depth_irb->mt->hiz_mt) {
 245       hiz_region = depth_irb->mt->hiz_mt->region;
 246    }
 247
 248    /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
 249     * non-pipelined state that will need the PIPE_CONTROL workaround.
 250     */
 251    if (intel->gen == 6) {
 252       intel_emit_post_sync_nonzero_flush(intel);
 253       intel_emit_depth_stall_flushes(intel);
 254    }
 255
 256    /*
 257     * If either depth or stencil buffer has packed depth/stencil format,
 258     * then don't use separate stencil. Emit only a depth buffer.
 259     */
 260    if (depth_irb && depth_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 261       stencil_irb = NULL;
 262    } else if (!depth_irb && stencil_irb
 263               && stencil_irb->Base.Format == MESA_FORMAT_S8_Z24) {
 264       depth_irb = stencil_irb;
 265       stencil_irb = NULL;
 266    }
 267
 268    if (intel->gen >= 6)
 269       len = 7;
 270    else if (intel->is_g4x || intel->gen == 5)
 271       len = 6;
 272    else
 273       len = 5;
 274
 275    if (!depth_irb && !stencil_irb) {
 276       BEGIN_BATCH(len);
 277       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 278       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 279                 (BRW_SURFACE_NULL << 29));
 280       OUT_BATCH(0);
 281       OUT_BATCH(0);
 282       OUT_BATCH(0);
 283
 284       if (intel->is_g4x || intel->gen >= 5)
 285          OUT_BATCH(0);
 286
 287       if (intel->gen >= 6)
 288          OUT_BATCH(0);
 289
 290       ADVANCE_BATCH();
 291
 292    } else if (!depth_irb && stencil_irb) {
 293       /*
 294        * There exists a separate stencil buffer but no depth buffer.
 295        *
 296        * The stencil buffer inherits most of its fields from
 297        * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
 298        * height.
 299        *
 300        * Since the stencil buffer has quirky pitch requirements, its region
 301        * was allocated with half height and double cpp. So we need
 302        * a multiplier of 2 to obtain the surface's real height.
 303        *
 304        * Enable the hiz bit because it and the separate stencil bit must have
 305        * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit
 306        * 1.21 "Separate Stencil Enable":
 307        *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
 308        *     Enable must also be enabled.
 309        *
 310        *     [DevGT]: This field must be set to the same value (enabled or
 311        *     disabled) as Hierarchical Depth Buffer Enable
 312        *
 313        * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
 314        * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
 315        *     [DevGT+]: This field must be set to TRUE.
 316        */
 317       struct intel_region *region = stencil_irb->mt->region;
 318
 319       assert(intel->has_separate_stencil);
 320       assert(stencil_irb->Base.Format == MESA_FORMAT_S8);
 321
 322       BEGIN_BATCH(len);
 323       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 324       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 325                 (1 << 21) | /* separate stencil enable */
 326                 (1 << 22) | /* hiz enable */
 327                 (BRW_TILEWALK_YMAJOR << 26) |
 328                 (1 << 27) | /* tiled surface */
 329                 (BRW_SURFACE_2D << 29));
 330       OUT_BATCH(0);
 331       OUT_BATCH(((region->width - 1) << 6) |
 332                  (2 * region->height - 1) << 19);
 333       OUT_BATCH(0);
 334       OUT_BATCH(0);
 335
 336       if (intel->gen >= 6)
 337          OUT_BATCH(0);
 338
 339       ADVANCE_BATCH();
 340
 341    } else {
 342       struct intel_region *region = depth_irb->mt->region;
 343       uint32_t tile_x, tile_y, offset;
 344
 345       /* If using separate stencil, hiz must be enabled. */
 346       assert(!stencil_irb || hiz_region);
 347
 348       offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y);
 349
 350       assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
 351       assert(!hiz_region || region->tiling == I915_TILING_Y);
 352
 353       BEGIN_BATCH(len);
 354       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
 355       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 356                 (brw_depthbuffer_format(brw) << 18) |
 357                 ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */
 358                 ((hiz_region ? 1 : 0) << 22) | /* hiz enable */
 359                 (BRW_TILEWALK_YMAJOR << 26) |
 360                 ((region->tiling != I915_TILING_NONE) << 27) |
 361                 (BRW_SURFACE_2D << 29));
 362       OUT_RELOC(region->bo,
 363                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 364                 offset);
 365       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 366                 ((region->width - 1) << 6) |
 367                 ((region->height - 1) << 19));
 368       OUT_BATCH(0);
 369
 370       if (intel->is_g4x || intel->gen >= 5)
 371          OUT_BATCH(tile_x | (tile_y << 16));
 372       else
 373          assert(tile_x == 0 && tile_y == 0);
 374
 375       if (intel->gen >= 6)
 376          OUT_BATCH(0);
 377
 378       ADVANCE_BATCH();
 379    }
 380
 381    if (hiz_region || stencil_irb) {
 382       /*
 383        * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
 384        * stencil enable' and 'hiz enable' bits were set. Therefore we must
 385        * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
 386        * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
 387        * failure to do so causes hangs on gen5 and a stall on gen6.
 388        */
 389
 390       /* Emit hiz buffer. */
 391       if (hiz_region) {
 392          BEGIN_BATCH(3);
 393          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 394          OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 395          OUT_RELOC(hiz_region->bo,
 396                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 397                    0);
 398          ADVANCE_BATCH();
 399       } else {
 400          BEGIN_BATCH(3);
 401          OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 402          OUT_BATCH(0);
 403          OUT_BATCH(0);
 404          ADVANCE_BATCH();
 405       }
 406
 407       /* Emit stencil buffer. */
 408       if (stencil_irb) {
 409          struct intel_region *region = stencil_irb->mt->region;
 410          BEGIN_BATCH(3);
 411          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 412          OUT_BATCH(region->pitch * region->cpp - 1);
 413          OUT_RELOC(region->bo,
 414                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 415                    0);
 416          ADVANCE_BATCH();
 417       } else {
 418          BEGIN_BATCH(3);
 419          OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 420          OUT_BATCH(0);
 421          OUT_BATCH(0);
 422          ADVANCE_BATCH();
 423       }
 424    }
 425
 426    /*
 427     * On Gen >= 6, emit clear params for safety. If using hiz, then clear
 428     * params must be emitted.
 429     *
 430     * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
 431     *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
 432     *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
 433     */
 434    if (intel->gen >= 6 || hiz_region) {
 435       if (intel->gen == 6)
 436          intel_emit_post_sync_nonzero_flush(intel);
 437
 438       BEGIN_BATCH(2);
 439       OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
 440       OUT_BATCH(0);
 441       ADVANCE_BATCH();
 442    }
 443 }
 444
 445 const struct brw_tracked_state brw_depthbuffer = {
 446    .dirty = {
 447       .mesa = _NEW_BUFFERS,
 448       .brw = BRW_NEW_BATCH,
 449       .cache = 0,
 450    },
 451    .emit = emit_depthbuffer,
 452 };
 453
 454
 455
 456 /***********************************************************************
 457  * Polygon stipple packet
 458  */
 459
 460 static void upload_polygon_stipple(struct brw_context *brw)
 461 {
 462    struct intel_context *intel = &brw->intel;
 463    struct gl_context *ctx = &brw->intel.ctx;
 464    GLuint i;
 465
 466    /* _NEW_POLYGON */
 467    if (!ctx->Polygon.StippleFlag)
 468       return;
 469
 470    if (intel->gen == 6)
 471       intel_emit_post_sync_nonzero_flush(intel);
 472
 473    BEGIN_BATCH(33);
 474    OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
 475
 476    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 477     * row first.  If we're rendering to a window (i.e. the
 478     * default frame buffer object, 0), then we need to invert
 479     * it to match our pixel layout.  But if we're rendering
 480     * to a FBO (i.e. any named frame buffer object), we *don't*
 481     * need to invert - we already match the layout.
 482     */
 483    if (ctx->DrawBuffer->Name == 0) {
 484       for (i = 0; i < 32; i++)
 485           OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
 486    }
 487    else {
 488       for (i = 0; i < 32; i++)
 489          OUT_BATCH(ctx->PolygonStipple[i]);
 490    }
 491    CACHED_BATCH();
 492 }
 493
 494 const struct brw_tracked_state brw_polygon_stipple = {
 495    .dirty = {
 496       .mesa = (_NEW_POLYGONSTIPPLE |
 497                _NEW_POLYGON),
 498       .brw = BRW_NEW_CONTEXT,
 499       .cache = 0
 500    },
 501    .emit = upload_polygon_stipple
 502 };
 503
 504
 505 /***********************************************************************
 506  * Polygon stipple offset packet
 507  */
 508
 509 static void upload_polygon_stipple_offset(struct brw_context *brw)
 510 {
 511    struct intel_context *intel = &brw->intel;
 512    struct gl_context *ctx = &brw->intel.ctx;
 513
 514    /* _NEW_POLYGON */
 515    if (!ctx->Polygon.StippleFlag)
 516       return;
 517
 518    if (intel->gen == 6)
 519       intel_emit_post_sync_nonzero_flush(intel);
 520
 521    BEGIN_BATCH(2);
 522    OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
 523
 524    /* _NEW_BUFFERS
 525     *
 526     * If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 527     * we have to invert the Y axis in order to match the OpenGL
 528     * pixel coordinate system, and our offset must be matched
 529     * to the window position.  If we're drawing to a FBO
 530     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 531     * system works just fine, and there's no window system to
 532     * worry about.
 533     */
 534    if (brw->intel.ctx.DrawBuffer->Name == 0)
 535       OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31);
 536    else
 537       OUT_BATCH(0);
 538    CACHED_BATCH();
 539 }
 540
 541 const struct brw_tracked_state brw_polygon_stipple_offset = {
 542    .dirty = {
 543       .mesa = (_NEW_BUFFERS |
 544                _NEW_POLYGON),
 545       .brw = BRW_NEW_CONTEXT,
 546       .cache = 0
 547    },
 548    .emit = upload_polygon_stipple_offset
 549 };
 550
 551 /**********************************************************************
 552  * AA Line parameters
 553  */
 554 static void upload_aa_line_parameters(struct brw_context *brw)
 555 {
 556    struct intel_context *intel = &brw->intel;
 557    struct gl_context *ctx = &brw->intel.ctx;
 558
 559    if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
 560       return;
 561
 562    if (intel->gen == 6)
 563       intel_emit_post_sync_nonzero_flush(intel);
 564
 565    OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2));
 566    /* use legacy aa line coverage computation */
 567    OUT_BATCH(0);
 568    OUT_BATCH(0);
 569    CACHED_BATCH();
 570 }
 571
 572 const struct brw_tracked_state brw_aa_line_parameters = {
 573    .dirty = {
 574       .mesa = _NEW_LINE,
 575       .brw = BRW_NEW_CONTEXT,
 576       .cache = 0
 577    },
 578    .emit = upload_aa_line_parameters
 579 };
 580
 581 /***********************************************************************
 582  * Line stipple packet
 583  */
 584
 585 static void upload_line_stipple(struct brw_context *brw)
 586 {
 587    struct intel_context *intel = &brw->intel;
 588    struct gl_context *ctx = &brw->intel.ctx;
 589    GLfloat tmp;
 590    GLint tmpi;
 591
 592    if (!ctx->Line.StippleFlag)
 593       return;
 594
 595    if (intel->gen == 6)
 596       intel_emit_post_sync_nonzero_flush(intel);
 597
 598    BEGIN_BATCH(3);
 599    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
 600    OUT_BATCH(ctx->Line.StipplePattern);
 601    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 602    tmpi = tmp * (1<<13);
 603    OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
 604    CACHED_BATCH();
 605 }
 606
 607 const struct brw_tracked_state brw_line_stipple = {
 608    .dirty = {
 609       .mesa = _NEW_LINE,
 610       .brw = BRW_NEW_CONTEXT,
 611       .cache = 0
 612    },
 613    .emit = upload_line_stipple
 614 };
 615
 616
 617 /***********************************************************************
 618  * Misc invarient state packets
 619  */
 620
 621 static void upload_invarient_state( struct brw_context *brw )
 622 {
 623    struct intel_context *intel = &brw->intel;
 624
 625    /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
 626    if (intel->gen == 6)
 627       intel_emit_post_sync_nonzero_flush(intel);
 628
 629    /* Select the 3D pipeline (as opposed to media) */
 630    BEGIN_BATCH(1);
 631    OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0);
 632    ADVANCE_BATCH();
 633
 634    if (intel->gen < 6) {
 635       /* Disable depth offset clamping. */
 636       BEGIN_BATCH(2);
 637       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
 638       OUT_BATCH_F(0.0);
 639       ADVANCE_BATCH();
 640    }
 641
 642    if (intel->gen >= 6) {
 643       int i;
 644       int len = intel->gen >= 7 ? 4 : 3;
 645
 646       BEGIN_BATCH(len);
 647       OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
 648       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
 649                 MS_NUMSAMPLES_1);
 650       OUT_BATCH(0); /* positions for 4/8-sample */
 651       if (intel->gen >= 7)
 652          OUT_BATCH(0);
 653       ADVANCE_BATCH();
 654
 655       BEGIN_BATCH(2);
 656       OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
 657       OUT_BATCH(1);
 658       ADVANCE_BATCH();
 659
 660       if (intel->gen < 7) {
 661          for (i = 0; i < 4; i++) {
 662             BEGIN_BATCH(4);
 663             OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));
 664             OUT_BATCH(i << SVB_INDEX_SHIFT);
 665             OUT_BATCH(0);
 666             OUT_BATCH(0xffffffff);
 667             ADVANCE_BATCH();
 668          }
 669       }
 670    }
 671
 672    BEGIN_BATCH(2);
 673    OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2));
 674    OUT_BATCH(0);
 675    ADVANCE_BATCH();
 676
 677    BEGIN_BATCH(1);
 678    OUT_BATCH(brw->CMD_VF_STATISTICS << 16 |
 679              (unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0));
 680    ADVANCE_BATCH();
 681 }
 682
 683 const struct brw_tracked_state brw_invarient_state = {
 684    .dirty = {
 685       .mesa = 0,
 686       .brw = BRW_NEW_CONTEXT,
 687       .cache = 0
 688    },
 689    .emit = upload_invarient_state
 690 };
 691
 692 /**
 693  * Define the base addresses which some state is referenced from.
 694  *
 695  * This allows us to avoid having to emit relocations for the objects,
 696  * and is actually required for binding table pointers on gen6.
 697  *
 698  * Surface state base address covers binding table pointers and
 699  * surface state objects, but not the surfaces that the surface state
 700  * objects point to.
 701  */
 702 static void upload_state_base_address( struct brw_context *brw )
 703 {
 704    struct intel_context *intel = &brw->intel;
 705
 706    /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
 707     * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
 708     * programmed prior to STATE_BASE_ADDRESS.
 709     *
 710     * However, given that the instruction SBA (general state base
 711     * address) on this chipset is always set to 0 across X and GL,
 712     * maybe this isn't required for us in particular.
 713     */
 714
 715    if (intel->gen >= 6) {
 716       if (intel->gen == 6)
 717          intel_emit_post_sync_nonzero_flush(intel);
 718
 719        BEGIN_BATCH(10);
 720        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
 721        /* General state base address: stateless DP read/write requests */
 722        OUT_BATCH(1);
 723        /* Surface state base address:
 724         * BINDING_TABLE_STATE
 725         * SURFACE_STATE
 726         */
 727        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
 728         /* Dynamic state base address:
 729          * SAMPLER_STATE
 730          * SAMPLER_BORDER_COLOR_STATE
 731          * CLIP, SF, WM/CC viewport state
 732          * COLOR_CALC_STATE
 733          * DEPTH_STENCIL_STATE
 734          * BLEND_STATE
 735          * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
 736          * Disable is clear, which we rely on)
 737          */
 738        OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER |
 739                                    I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
 740
 741        OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
 742        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 743                  1); /* Instruction base address: shader kernels (incl. SIP) */
 744
 745        OUT_BATCH(1); /* General state upper bound */
 746        OUT_BATCH(1); /* Dynamic state upper bound */
 747        OUT_BATCH(1); /* Indirect object upper bound */
 748        OUT_BATCH(1); /* Instruction access upper bound */
 749        ADVANCE_BATCH();
 750    } else if (intel->gen == 5) {
 751        BEGIN_BATCH(8);
 752        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 753        OUT_BATCH(1); /* General state base address */
 754        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 755                  1); /* Surface state base address */
 756        OUT_BATCH(1); /* Indirect object base address */
 757        OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
 758                  1); /* Instruction base address */
 759        OUT_BATCH(1); /* General state upper bound */
 760        OUT_BATCH(1); /* Indirect object upper bound */
 761        OUT_BATCH(1); /* Instruction access upper bound */
 762        ADVANCE_BATCH();
 763    } else {
 764        BEGIN_BATCH(6);
 765        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 766        OUT_BATCH(1); /* General state base address */
 767        OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
 768                  1); /* Surface state base address */
 769        OUT_BATCH(1); /* Indirect object base address */
 770        OUT_BATCH(1); /* General state upper bound */
 771        OUT_BATCH(1); /* Indirect object upper bound */
 772        ADVANCE_BATCH();
 773    }
 774
 775    /* According to section 3.6.1 of VOL1 of the 965 PRM,
 776     * STATE_BASE_ADDRESS updates require a reissue of:
 777     *
 778     * 3DSTATE_PIPELINE_POINTERS
 779     * 3DSTATE_BINDING_TABLE_POINTERS
 780     * MEDIA_STATE_POINTERS
 781     *
 782     * and this continues through Ironlake.  The Sandy Bridge PRM, vol
 783     * 1 part 1 says that the folowing packets must be reissued:
 784     *
 785     * 3DSTATE_CC_POINTERS
 786     * 3DSTATE_BINDING_TABLE_POINTERS
 787     * 3DSTATE_SAMPLER_STATE_POINTERS
 788     * 3DSTATE_VIEWPORT_STATE_POINTERS
 789     * MEDIA_STATE_POINTERS
 790     *
 791     * Those are always reissued following SBA updates anyway (new
 792     * batch time), except in the case of the program cache BO
 793     * changing.  Having a separate state flag makes the sequence more
 794     * obvious.
 795     */
 796
 797    brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
 798 }
 799
 800 const struct brw_tracked_state brw_state_base_address = {
 801    .dirty = {
 802       .mesa = 0,
 803       .brw = (BRW_NEW_BATCH |
 804               BRW_NEW_PROGRAM_CACHE),
 805       .cache = 0,
 806    },
 807    .emit = upload_state_base_address
 808 };