2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
41 #include "compiler/brw_eu_defines.h"
43 #include "main/framebuffer.h"
44 #include "main/fbobject.h"
45 #include "main/format_utils.h"
46 #include "main/glformats.h"
49 * Upload pointers to the per-stage state.
51 * The state pointers in this packet are all relative to the general state
52 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
55 upload_pipelined_state_pointers(struct brw_context
*brw
)
58 /* Need to flush before changing clip max threads for errata. */
65 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
66 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
67 brw
->vs
.base
.state_offset
);
68 if (brw
->ff_gs
.prog_active
)
69 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
70 brw
->ff_gs
.state_offset
| 1);
73 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
74 brw
->clip
.state_offset
| 1);
75 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
76 brw
->sf
.state_offset
);
77 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
78 brw
->wm
.base
.state_offset
);
79 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
80 brw
->cc
.state_offset
);
83 brw
->ctx
.NewDriverState
|= BRW_NEW_PSP
;
87 upload_psp_urb_cbs(struct brw_context
*brw
)
89 upload_pipelined_state_pointers(brw
);
90 brw_upload_urb_fence(brw
);
91 brw_upload_cs_urb_state(brw
);
94 const struct brw_tracked_state brw_psp_urb_cbs
= {
97 .brw
= BRW_NEW_BATCH
|
99 BRW_NEW_FF_GS_PROG_DATA
|
100 BRW_NEW_GEN4_UNIT_STATE
|
101 BRW_NEW_STATE_BASE_ADDRESS
|
104 .emit
= upload_psp_urb_cbs
,
108 brw_depthbuffer_format(struct brw_context
*brw
)
110 struct gl_context
*ctx
= &brw
->ctx
;
111 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
112 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
113 struct intel_renderbuffer
*srb
;
116 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
117 !srb
->mt
->stencil_mt
&&
118 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
119 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
124 return BRW_DEPTHFORMAT_D32_FLOAT
;
126 return brw_depth_format(brw
, drb
->mt
->format
);
130 * Returns the mask of how many bits of x and y must be handled through the
131 * depthbuffer's draw offset x and y fields.
133 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
134 * between the depth, hiz, and stencil buffers. Because it can be hard to get
135 * all 3 to agree on this value, we want to do as much drawing offset
136 * adjustment as possible by moving the base offset of the 3 buffers, which is
137 * restricted to tile boundaries.
139 * For each buffer, the remainder must be applied through the x/y draw offset.
140 * This returns the worst-case mask of the low bits that have to go into the
141 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
142 * mask, then we're in trouble.
145 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
146 uint32_t depth_level
,
147 uint32_t depth_layer
,
148 struct intel_mipmap_tree
*stencil_mt
,
149 uint32_t *out_tile_mask_x
,
150 uint32_t *out_tile_mask_y
)
152 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
155 intel_get_tile_masks(depth_mt
->tiling
,
157 &tile_mask_x
, &tile_mask_y
);
158 assert(!intel_miptree_level_has_hiz(depth_mt
, depth_level
));
162 if (stencil_mt
->stencil_mt
)
163 stencil_mt
= stencil_mt
->stencil_mt
;
165 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
166 /* Separate stencil buffer uses 64x64 tiles. */
170 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
171 intel_get_tile_masks(stencil_mt
->tiling
,
173 &stencil_tile_mask_x
,
174 &stencil_tile_mask_y
);
176 tile_mask_x
|= stencil_tile_mask_x
;
177 tile_mask_y
|= stencil_tile_mask_y
;
181 *out_tile_mask_x
= tile_mask_x
;
182 *out_tile_mask_y
= tile_mask_y
;
185 static struct intel_mipmap_tree
*
186 get_stencil_miptree(struct intel_renderbuffer
*irb
)
190 if (irb
->mt
->stencil_mt
)
191 return irb
->mt
->stencil_mt
;
196 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
197 GLbitfield clear_mask
)
199 struct gl_context
*ctx
= &brw
->ctx
;
200 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
201 bool rebase_depth
= false;
202 bool rebase_stencil
= false;
203 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
204 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
205 struct intel_mipmap_tree
*depth_mt
= NULL
;
206 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
207 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
208 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
209 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
210 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
213 depth_mt
= depth_irb
->mt
;
215 /* Initialize brw->depthstencil to 'nop' workaround state.
217 brw
->depthstencil
.tile_x
= 0;
218 brw
->depthstencil
.tile_y
= 0;
219 brw
->depthstencil
.depth_offset
= 0;
220 brw
->depthstencil
.stencil_offset
= 0;
221 brw
->depthstencil
.hiz_offset
= 0;
222 brw
->depthstencil
.depth_mt
= NULL
;
223 brw
->depthstencil
.stencil_mt
= NULL
;
225 brw
->depthstencil
.depth_mt
= depth_mt
;
227 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
229 /* Gen6+ doesn't require the workarounds, since we always program the
230 * surface state at the start of the whole surface.
235 /* Check if depth buffer is in depth/stencil format. If so, then it's only
236 * safe to invalidate it if we're also clearing stencil, and both depth_irb
237 * and stencil_irb point to the same miptree.
239 * Note: it's not sufficient to check for the case where
240 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
241 * because this fails to catch depth/stencil buffers on hardware that uses
242 * separate stencil. To catch that case, we check whether
243 * depth_mt->stencil_mt is non-NULL.
245 if (depth_irb
&& invalidate_depth
&&
246 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
247 depth_mt
->stencil_mt
)) {
248 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
249 && depth_irb
->mt
== stencil_irb
->mt
;
252 uint32_t tile_mask_x
, tile_mask_y
;
253 brw_get_depthstencil_tile_masks(depth_mt
,
254 depth_mt
? depth_irb
->mt_level
: 0,
255 depth_mt
? depth_irb
->mt_layer
: 0,
257 &tile_mask_x
, &tile_mask_y
);
260 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
261 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
263 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
264 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
265 * Coordinate Offset X/Y":
267 * "The 3 LSBs of both offsets must be zero to ensure correct
270 if (tile_x
& 7 || tile_y
& 7)
273 /* We didn't even have intra-tile offsets before g45. */
274 if (!brw
->has_surface_tile_offset
) {
275 if (tile_x
|| tile_y
)
280 perf_debug("HW workaround: blitting depth level %d to a temporary "
281 "to fix alignment (depth tile offset %d,%d)\n",
282 depth_irb
->mt_level
, tile_x
, tile_y
);
283 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
284 /* In the case of stencil_irb being the same packed depth/stencil
285 * texture but not the same rb, make it point at our rebased mt, too.
288 stencil_irb
!= depth_irb
&&
289 stencil_irb
->mt
== depth_mt
) {
290 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
291 intel_renderbuffer_set_draw_offset(stencil_irb
);
294 stencil_mt
= get_stencil_miptree(stencil_irb
);
296 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
297 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
301 stencil_mt
= get_stencil_miptree(stencil_irb
);
302 intel_miptree_get_image_offset(stencil_mt
,
303 stencil_irb
->mt_level
,
304 stencil_irb
->mt_layer
,
305 &stencil_draw_x
, &stencil_draw_y
);
306 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
307 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
309 /* If stencil doesn't match depth, then we'll need to rebase stencil
310 * as well. (if we hadn't decided to rebase stencil before, the
311 * post-stencil depth test will also rebase depth to try to match it
314 if (tile_x
!= stencil_tile_x
||
315 tile_y
!= stencil_tile_y
) {
316 rebase_stencil
= true;
321 /* If we have (just) stencil, check it for ignored low bits as well */
323 intel_miptree_get_image_offset(stencil_mt
,
324 stencil_irb
->mt_level
,
325 stencil_irb
->mt_layer
,
326 &stencil_draw_x
, &stencil_draw_y
);
327 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
328 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
330 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
331 rebase_stencil
= true;
333 if (!brw
->has_surface_tile_offset
) {
334 if (stencil_tile_x
|| stencil_tile_y
)
335 rebase_stencil
= true;
339 if (rebase_stencil
) {
340 perf_debug("HW workaround: blitting stencil level %d to a temporary "
341 "to fix alignment (stencil tile offset %d,%d)\n",
342 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
344 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
345 stencil_mt
= get_stencil_miptree(stencil_irb
);
347 intel_miptree_get_image_offset(stencil_mt
,
348 stencil_irb
->mt_level
,
349 stencil_irb
->mt_layer
,
350 &stencil_draw_x
, &stencil_draw_y
);
351 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
352 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
354 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
355 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
356 intel_renderbuffer_set_draw_offset(depth_irb
);
357 } else if (depth_irb
&& !rebase_depth
) {
358 if (tile_x
!= stencil_tile_x
||
359 tile_y
!= stencil_tile_y
) {
360 perf_debug("HW workaround: blitting depth level %d to a temporary "
361 "to match stencil level %d alignment (depth tile offset "
362 "%d,%d, stencil offset %d,%d)\n",
364 stencil_irb
->mt_level
,
366 stencil_tile_x
, stencil_tile_y
);
368 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
370 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
371 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
373 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
374 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
375 intel_renderbuffer_set_draw_offset(stencil_irb
);
378 WARN_ONCE(stencil_tile_x
!= tile_x
||
379 stencil_tile_y
!= tile_y
,
380 "Rebased stencil tile offset (%d,%d) doesn't match depth "
381 "tile offset (%d,%d).\n",
382 stencil_tile_x
, stencil_tile_y
,
389 tile_x
= stencil_tile_x
;
390 tile_y
= stencil_tile_y
;
393 /* While we just tried to get everything aligned, we may have failed to do
394 * so in the case of rendering to array or 3D textures, where nonzero faces
395 * will still have an offset post-rebase. At least give an informative
398 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
399 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
400 "Truncating offset, bad rendering may occur.\n");
404 /* Now, after rebasing, save off the new dephtstencil state so the hardware
405 * packets can just dereference that without re-calculating tile offsets.
407 brw
->depthstencil
.tile_x
= tile_x
;
408 brw
->depthstencil
.tile_y
= tile_y
;
410 depth_mt
= depth_irb
->mt
;
411 brw
->depthstencil
.depth_mt
= depth_mt
;
412 brw
->depthstencil
.depth_offset
=
413 intel_miptree_get_aligned_offset(depth_mt
,
414 depth_irb
->draw_x
& ~tile_mask_x
,
415 depth_irb
->draw_y
& ~tile_mask_y
);
416 if (intel_renderbuffer_has_hiz(depth_irb
)) {
417 brw
->depthstencil
.hiz_offset
=
418 intel_miptree_get_aligned_offset(depth_mt
,
419 depth_irb
->draw_x
& ~tile_mask_x
,
420 (depth_irb
->draw_y
& ~tile_mask_y
) / 2);
424 stencil_mt
= get_stencil_miptree(stencil_irb
);
426 brw
->depthstencil
.stencil_mt
= stencil_mt
;
427 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
428 /* Note: we can't compute the stencil offset using
429 * intel_region_get_aligned_offset(), because stencil_region claims
430 * that the region is untiled even though it's W tiled.
432 brw
->depthstencil
.stencil_offset
=
433 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
434 (stencil_draw_x
& ~tile_mask_x
) * 64;
440 brw_emit_depthbuffer(struct brw_context
*brw
)
442 struct gl_context
*ctx
= &brw
->ctx
;
443 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
445 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
446 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
447 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
448 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
449 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
450 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
451 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
452 bool separate_stencil
= false;
453 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
454 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
455 uint32_t depth_offset
= 0;
456 uint32_t width
= 1, height
= 1;
459 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
461 /* Gen7 supports only separate stencil */
462 assert(separate_stencil
|| brw
->gen
< 7);
465 /* If there's a packed depth/stencil bound to stencil only, we need to
466 * emit the packed depth/stencil buffer packet.
468 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
469 depth_irb
= stencil_irb
;
470 depth_mt
= stencil_mt
;
473 if (depth_irb
&& depth_mt
) {
474 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
475 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
476 * depthstencil format.
478 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
479 * set to the same value. Gens after 7 implicitly always set
480 * Separate_Stencil_Enable; software cannot disable it.
482 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
483 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
486 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
487 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
489 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
490 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
492 depthbuffer_format
= brw_depthbuffer_format(brw
);
493 depth_surface_type
= BRW_SURFACE_2D
;
494 depth_offset
= brw
->depthstencil
.depth_offset
;
495 width
= depth_irb
->Base
.Base
.Width
;
496 height
= depth_irb
->Base
.Base
.Height
;
497 } else if (separate_stencil
) {
499 * There exists a separate stencil buffer but no depth buffer.
501 * The stencil buffer inherits most of its fields from
502 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
505 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
506 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
507 * [DevGT+]: This field must be set to TRUE.
509 assert(brw
->has_separate_stencil
);
511 depth_surface_type
= BRW_SURFACE_2D
;
512 width
= stencil_irb
->Base
.Base
.Width
;
513 height
= stencil_irb
->Base
.Base
.Height
;
517 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
519 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
521 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
522 depthbuffer_format
, depth_surface_type
,
523 stencil_mt
, hiz
, separate_stencil
,
524 width
, height
, tile_x
, tile_y
);
528 brw_convert_depth_value(mesa_format format
, float value
)
531 case MESA_FORMAT_Z_FLOAT32
:
532 return float_as_int(value
);
533 case MESA_FORMAT_Z_UNORM16
:
534 return value
* ((1u << 16) - 1);
535 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
536 return value
* ((1u << 24) - 1);
538 unreachable("Invalid depth format");
543 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
544 struct intel_mipmap_tree
*depth_mt
,
545 uint32_t depth_offset
, uint32_t depthbuffer_format
,
546 uint32_t depth_surface_type
,
547 struct intel_mipmap_tree
*stencil_mt
,
548 bool hiz
, bool separate_stencil
,
549 uint32_t width
, uint32_t height
,
550 uint32_t tile_x
, uint32_t tile_y
)
552 /* Enable the hiz bit if we're doing separate stencil, because it and the
553 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
554 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
555 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
556 * Enable must also be enabled.
558 * [DevGT]: This field must be set to the same value (enabled or
559 * disabled) as Hierarchical Depth Buffer Enable
561 bool enable_hiz_ss
= hiz
|| separate_stencil
;
564 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
565 * non-pipelined state that will need the PIPE_CONTROL workaround.
568 brw_emit_depth_stall_flushes(brw
);
574 else if (brw
->is_g4x
|| brw
->gen
== 5)
580 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
581 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
582 (depthbuffer_format
<< 18) |
583 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
584 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
585 (BRW_TILEWALK_YMAJOR
<< 26) |
586 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
588 (depth_surface_type
<< 29));
591 OUT_RELOC(depth_mt
->bo
,
592 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
598 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
599 ((height
+ tile_y
- 1) << 19));
602 if (brw
->is_g4x
|| brw
->gen
>= 5)
603 OUT_BATCH(tile_x
| (tile_y
<< 16));
605 assert(tile_x
== 0 && tile_y
== 0);
612 if (hiz
|| separate_stencil
) {
614 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
615 * stencil enable' and 'hiz enable' bits were set. Therefore we must
616 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
617 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
618 * failure to do so causes hangs on gen5 and a stall on gen6.
621 /* Emit hiz buffer. */
625 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
626 OUT_BATCH(depth_mt
->hiz_buf
->aux_base
.pitch
- 1);
627 OUT_RELOC(depth_mt
->hiz_buf
->aux_base
.bo
,
628 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
629 brw
->depthstencil
.hiz_offset
);
633 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
639 /* Emit stencil buffer. */
640 if (separate_stencil
) {
642 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
643 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
644 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
645 * The pitch must be set to 2x the value computed based on width, as
646 * the stencil buffer is stored with two rows interleaved.
648 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
649 OUT_RELOC(stencil_mt
->bo
,
650 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
651 brw
->depthstencil
.stencil_offset
);
655 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
663 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
664 * params must be emitted.
666 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
667 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
668 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
670 if (brw
->gen
>= 6 || hiz
) {
672 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
673 GEN5_DEPTH_CLEAR_VALID
|
676 OUT_BATCH(brw_convert_depth_value(depth_mt
->format
,
677 depth_mt
->fast_clear_color
.f32
[0]));
685 const struct brw_tracked_state brw_depthbuffer
= {
687 .mesa
= _NEW_BUFFERS
,
688 .brw
= BRW_NEW_BATCH
|
691 .emit
= brw_emit_depthbuffer
,
695 brw_emit_select_pipeline(struct brw_context
*brw
, enum brw_pipeline pipeline
)
697 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
698 const uint32_t _3DSTATE_PIPELINE_SELECT
=
699 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
701 if (brw
->gen
>= 8 && brw
->gen
< 10) {
702 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
704 * Software must clear the COLOR_CALC_STATE Valid field in
705 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
706 * with Pipeline Select set to GPGPU.
708 * The internal hardware docs recommend the same workaround for Gen9
711 if (pipeline
== BRW_COMPUTE_PIPELINE
) {
713 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
717 brw
->ctx
.NewDriverState
|= BRW_NEW_CC_STATE
;
722 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
723 * PIPELINE_SELECT [DevBWR+]":
727 * Software must ensure all the write caches are flushed through a
728 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
729 * command to invalidate read only caches prior to programming
730 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
732 const unsigned dc_flush
=
733 brw
->gen
>= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH
: 0;
735 brw_emit_pipe_control_flush(brw
,
736 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
737 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
739 PIPE_CONTROL_NO_WRITE
|
740 PIPE_CONTROL_CS_STALL
);
742 brw_emit_pipe_control_flush(brw
,
743 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
744 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
745 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
746 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
747 PIPE_CONTROL_NO_WRITE
);
750 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
751 * PIPELINE_SELECT [DevBWR+]":
753 * Project: PRE-DEVSNB
755 * Software must ensure the current pipeline is flushed via an
756 * MI_FLUSH or PIPE_CONTROL prior to the execution of PIPELINE_SELECT.
763 /* Select the pipeline */
765 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 |
766 (brw
->gen
>= 9 ? (3 << 8) : 0) |
767 (pipeline
== BRW_COMPUTE_PIPELINE
? 2 : 0));
770 if (brw
->gen
== 7 && !brw
->is_haswell
&&
771 pipeline
== BRW_RENDER_PIPELINE
) {
772 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
773 * PIPELINE_SELECT [DevBWR+]":
775 * Project: DEVIVB, DEVHSW:GT3:A0
777 * Software must send a pipe_control with a CS stall and a post sync
778 * operation and then a dummy DRAW after every MI_SET_CONTEXT and
779 * after any PIPELINE_SELECT that is enabling 3D mode.
781 gen7_emit_cs_stall_flush(brw
);
784 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2));
785 OUT_BATCH(_3DPRIM_POINTLIST
);
796 * Misc invariant state packets
799 brw_upload_invariant_state(struct brw_context
*brw
)
801 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
803 brw_emit_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
804 brw
->last_pipeline
= BRW_RENDER_PIPELINE
;
808 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
814 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
819 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
822 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
823 /* use legacy aa line coverage computation */
829 const uint32_t _3DSTATE_VF_STATISTICS
=
830 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
832 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 | 1);
836 const struct brw_tracked_state brw_invariant_state
= {
839 .brw
= BRW_NEW_BLORP
|
842 .emit
= brw_upload_invariant_state
846 * Define the base addresses which some state is referenced from.
848 * This allows us to avoid having to emit relocations for the objects,
849 * and is actually required for binding table pointers on gen6.
851 * Surface state base address covers binding table pointers and
852 * surface state objects, but not the surfaces that the surface state
856 brw_upload_state_base_address(struct brw_context
*brw
)
858 if (brw
->batch
.state_base_address_emitted
)
861 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
862 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
863 * programmed prior to STATE_BASE_ADDRESS.
865 * However, given that the instruction SBA (general state base
866 * address) on this chipset is always set to 0 across X and GL,
867 * maybe this isn't required for us in particular.
871 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
872 int pkt_len
= brw
->gen
>= 9 ? 19 : 16;
874 BEGIN_BATCH(pkt_len
);
875 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (pkt_len
- 2));
876 /* General state base address: stateless DP read/write requests */
877 OUT_BATCH(mocs_wb
<< 4 | 1);
879 OUT_BATCH(mocs_wb
<< 16);
880 /* Surface state base address: */
881 OUT_RELOC64(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
883 /* Dynamic state base address: */
884 OUT_RELOC64(brw
->batch
.bo
,
885 I915_GEM_DOMAIN_RENDER
| I915_GEM_DOMAIN_INSTRUCTION
, 0,
887 /* Indirect object base address: MEDIA_OBJECT data */
888 OUT_BATCH(mocs_wb
<< 4 | 1);
890 /* Instruction base address: shader kernels (incl. SIP) */
891 OUT_RELOC64(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
894 /* General state buffer size */
895 OUT_BATCH(0xfffff001);
896 /* Dynamic state buffer size */
897 OUT_BATCH(ALIGN(brw
->batch
.bo
->size
, 4096) | 1);
898 /* Indirect object upper bound */
899 OUT_BATCH(0xfffff001);
900 /* Instruction access upper bound */
901 OUT_BATCH(ALIGN(brw
->cache
.bo
->size
, 4096) | 1);
908 } else if (brw
->gen
>= 6) {
909 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
912 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
913 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
914 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
915 1); /* General State Base Address Modify Enable */
916 /* Surface state base address:
917 * BINDING_TABLE_STATE
920 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
921 /* Dynamic state base address:
923 * SAMPLER_BORDER_COLOR_STATE
924 * CLIP, SF, WM/CC viewport state
926 * DEPTH_STENCIL_STATE
928 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
929 * Disable is clear, which we rely on)
931 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
932 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
934 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
935 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
936 1); /* Instruction base address: shader kernels (incl. SIP) */
938 OUT_BATCH(1); /* General state upper bound */
939 /* Dynamic state upper bound. Although the documentation says that
940 * programming it to zero will cause it to be ignored, that is a lie.
941 * If this isn't programmed to a real bound, the sampler border color
942 * pointer is rejected, causing border color to mysteriously fail.
944 OUT_BATCH(0xfffff001);
945 OUT_BATCH(1); /* Indirect object upper bound */
946 OUT_BATCH(1); /* Instruction access upper bound */
948 } else if (brw
->gen
== 5) {
950 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
951 OUT_BATCH(1); /* General state base address */
952 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
953 1); /* Surface state base address */
954 OUT_BATCH(1); /* Indirect object base address */
955 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
956 1); /* Instruction base address */
957 OUT_BATCH(0xfffff001); /* General state upper bound */
958 OUT_BATCH(1); /* Indirect object upper bound */
959 OUT_BATCH(1); /* Instruction access upper bound */
963 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
964 OUT_BATCH(1); /* General state base address */
965 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
966 1); /* Surface state base address */
967 OUT_BATCH(1); /* Indirect object base address */
968 OUT_BATCH(1); /* General state upper bound */
969 OUT_BATCH(1); /* Indirect object upper bound */
973 /* According to section 3.6.1 of VOL1 of the 965 PRM,
974 * STATE_BASE_ADDRESS updates require a reissue of:
976 * 3DSTATE_PIPELINE_POINTERS
977 * 3DSTATE_BINDING_TABLE_POINTERS
978 * MEDIA_STATE_POINTERS
980 * and this continues through Ironlake. The Sandy Bridge PRM, vol
981 * 1 part 1 says that the folowing packets must be reissued:
983 * 3DSTATE_CC_POINTERS
984 * 3DSTATE_BINDING_TABLE_POINTERS
985 * 3DSTATE_SAMPLER_STATE_POINTERS
986 * 3DSTATE_VIEWPORT_STATE_POINTERS
987 * MEDIA_STATE_POINTERS
989 * Those are always reissued following SBA updates anyway (new
990 * batch time), except in the case of the program cache BO
991 * changing. Having a separate state flag makes the sequence more
995 brw
->ctx
.NewDriverState
|= BRW_NEW_STATE_BASE_ADDRESS
;
996 brw
->batch
.state_base_address_emitted
= true;