2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
37 #include "intel_regions.h"
39 #include "brw_context.h"
40 #include "brw_state.h"
41 #include "brw_defines.h"
43 #include "main/fbobject.h"
44 #include "main/glformats.h"
46 /* Constant single cliprect for framebuffer object or DRI2 drawing */
47 static void upload_drawing_rect(struct brw_context
*brw
)
49 struct gl_context
*ctx
= &brw
->ctx
;
52 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
53 OUT_BATCH(0); /* xmin, ymin */
54 OUT_BATCH(((ctx
->DrawBuffer
->Width
- 1) & 0xffff) |
55 ((ctx
->DrawBuffer
->Height
- 1) << 16));
60 const struct brw_tracked_state brw_drawing_rect
= {
63 .brw
= BRW_NEW_CONTEXT
,
66 .emit
= upload_drawing_rect
70 * Upload pointers to the per-stage state.
72 * The state pointers in this packet are all relative to the general state
73 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
75 static void upload_pipelined_state_pointers(struct brw_context
*brw
)
78 /* Need to flush before changing clip max threads for errata. */
85 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
86 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
87 brw
->vs
.base
.state_offset
);
88 if (brw
->ff_gs
.prog_active
)
89 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
90 brw
->ff_gs
.state_offset
| 1);
93 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
94 brw
->clip
.state_offset
| 1);
95 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
96 brw
->sf
.state_offset
);
97 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
98 brw
->wm
.base
.state_offset
);
99 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
100 brw
->cc
.state_offset
);
103 brw
->state
.dirty
.brw
|= BRW_NEW_PSP
;
106 static void upload_psp_urb_cbs(struct brw_context
*brw
)
108 upload_pipelined_state_pointers(brw
);
109 brw_upload_urb_fence(brw
);
110 brw_upload_cs_urb_state(brw
);
113 const struct brw_tracked_state brw_psp_urb_cbs
= {
116 .brw
= (BRW_NEW_URB_FENCE
|
118 BRW_NEW_STATE_BASE_ADDRESS
),
119 .cache
= (CACHE_NEW_VS_UNIT
|
120 CACHE_NEW_FF_GS_UNIT
|
121 CACHE_NEW_FF_GS_PROG
|
122 CACHE_NEW_CLIP_UNIT
|
127 .emit
= upload_psp_urb_cbs
,
131 brw_depthbuffer_format(struct brw_context
*brw
)
133 struct gl_context
*ctx
= &brw
->ctx
;
134 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
135 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
136 struct intel_renderbuffer
*srb
;
139 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
140 !srb
->mt
->stencil_mt
&&
141 (intel_rb_format(srb
) == MESA_FORMAT_S8_Z24
||
142 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_X24S8
)) {
147 return BRW_DEPTHFORMAT_D32_FLOAT
;
149 switch (drb
->mt
->format
) {
150 case MESA_FORMAT_Z16
:
151 return BRW_DEPTHFORMAT_D16_UNORM
;
152 case MESA_FORMAT_Z32_FLOAT
:
153 return BRW_DEPTHFORMAT_D32_FLOAT
;
154 case MESA_FORMAT_X8_Z24
:
156 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT
;
158 /* Use D24_UNORM_S8, not D24_UNORM_X8.
160 * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
161 * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
162 * 3DSTATE_DEPTH_BUFFER.Surface_Format).
164 * However, on Gen5, D24_UNORM_X8 may be used only if separate
165 * stencil is enabled, and we never enable it. From the Ironlake PRM,
166 * same section as above, Bit 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Buffer_Enable:
167 * If this field is disabled, the Surface Format of the depth
168 * buffer cannot be D24_UNORM_X8_UINT.
170 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
172 case MESA_FORMAT_S8_Z24
:
173 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT
;
174 case MESA_FORMAT_Z32_FLOAT_X24S8
:
175 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT
;
177 _mesa_problem(ctx
, "Unexpected depth format %s\n",
178 _mesa_get_format_name(intel_rb_format(drb
)));
179 return BRW_DEPTHFORMAT_D16_UNORM
;
184 * Returns the mask of how many bits of x and y must be handled through the
185 * depthbuffer's draw offset x and y fields.
187 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
188 * between the depth, hiz, and stencil buffers. Because it can be hard to get
189 * all 3 to agree on this value, we want to do as much drawing offset
190 * adjustment as possible by moving the base offset of the 3 buffers, which is
191 * restricted to tile boundaries.
193 * For each buffer, the remainder must be applied through the x/y draw offset.
194 * This returns the worst-case mask of the low bits that have to go into the
195 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
196 * mask, then we're in trouble.
199 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
200 uint32_t depth_level
,
201 uint32_t depth_layer
,
202 struct intel_mipmap_tree
*stencil_mt
,
203 uint32_t *out_tile_mask_x
,
204 uint32_t *out_tile_mask_y
)
206 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
209 intel_region_get_tile_masks(depth_mt
->region
,
210 &tile_mask_x
, &tile_mask_y
, false);
212 if (intel_miptree_slice_has_hiz(depth_mt
, depth_level
, depth_layer
)) {
213 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
214 intel_region_get_tile_masks(depth_mt
->hiz_mt
->region
,
215 &hiz_tile_mask_x
, &hiz_tile_mask_y
, false);
217 /* Each HiZ row represents 2 rows of pixels */
218 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
220 tile_mask_x
|= hiz_tile_mask_x
;
221 tile_mask_y
|= hiz_tile_mask_y
;
226 if (stencil_mt
->stencil_mt
)
227 stencil_mt
= stencil_mt
->stencil_mt
;
229 if (stencil_mt
->format
== MESA_FORMAT_S8
) {
230 /* Separate stencil buffer uses 64x64 tiles. */
234 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
235 intel_region_get_tile_masks(stencil_mt
->region
,
236 &stencil_tile_mask_x
,
237 &stencil_tile_mask_y
, false);
239 tile_mask_x
|= stencil_tile_mask_x
;
240 tile_mask_y
|= stencil_tile_mask_y
;
244 *out_tile_mask_x
= tile_mask_x
;
245 *out_tile_mask_y
= tile_mask_y
;
248 static struct intel_mipmap_tree
*
249 get_stencil_miptree(struct intel_renderbuffer
*irb
)
253 if (irb
->mt
->stencil_mt
)
254 return irb
->mt
->stencil_mt
;
259 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
260 GLbitfield clear_mask
)
262 struct gl_context
*ctx
= &brw
->ctx
;
263 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
264 bool rebase_depth
= false;
265 bool rebase_stencil
= false;
266 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
267 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
268 struct intel_mipmap_tree
*depth_mt
= NULL
;
269 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
270 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
271 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
272 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
273 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
276 depth_mt
= depth_irb
->mt
;
278 /* Initialize brw->depthstencil to 'nop' workaround state.
280 brw
->depthstencil
.tile_x
= 0;
281 brw
->depthstencil
.tile_y
= 0;
282 brw
->depthstencil
.depth_offset
= 0;
283 brw
->depthstencil
.stencil_offset
= 0;
284 brw
->depthstencil
.hiz_offset
= 0;
285 brw
->depthstencil
.depth_mt
= NULL
;
286 brw
->depthstencil
.stencil_mt
= NULL
;
288 brw
->depthstencil
.depth_mt
= depth_mt
;
290 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
292 /* Gen7+ doesn't require the workarounds, since we always program the
293 * surface state at the start of the whole surface.
298 /* Check if depth buffer is in depth/stencil format. If so, then it's only
299 * safe to invalidate it if we're also clearing stencil, and both depth_irb
300 * and stencil_irb point to the same miptree.
302 * Note: it's not sufficient to check for the case where
303 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
304 * because this fails to catch depth/stencil buffers on hardware that uses
305 * separate stencil. To catch that case, we check whether
306 * depth_mt->stencil_mt is non-NULL.
308 if (depth_irb
&& invalidate_depth
&&
309 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
310 depth_mt
->stencil_mt
)) {
311 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
312 && depth_irb
->mt
== stencil_irb
->mt
;
315 uint32_t tile_mask_x
, tile_mask_y
;
316 brw_get_depthstencil_tile_masks(depth_mt
,
317 depth_mt
? depth_irb
->mt_level
: 0,
318 depth_mt
? depth_irb
->mt_layer
: 0,
320 &tile_mask_x
, &tile_mask_y
);
323 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
324 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
326 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
327 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
328 * Coordinate Offset X/Y":
330 * "The 3 LSBs of both offsets must be zero to ensure correct
333 if (tile_x
& 7 || tile_y
& 7)
336 /* We didn't even have intra-tile offsets before g45. */
337 if (brw
->gen
== 4 && !brw
->is_g4x
) {
338 if (tile_x
|| tile_y
)
343 perf_debug("HW workaround: blitting depth level %d to a temporary "
344 "to fix alignment (depth tile offset %d,%d)\n",
345 depth_irb
->mt_level
, tile_x
, tile_y
);
346 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
347 /* In the case of stencil_irb being the same packed depth/stencil
348 * texture but not the same rb, make it point at our rebased mt, too.
351 stencil_irb
!= depth_irb
&&
352 stencil_irb
->mt
== depth_mt
) {
353 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
354 intel_renderbuffer_set_draw_offset(stencil_irb
);
357 stencil_mt
= get_stencil_miptree(stencil_irb
);
359 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
360 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
364 stencil_mt
= get_stencil_miptree(stencil_irb
);
365 intel_miptree_get_image_offset(stencil_mt
,
366 stencil_irb
->mt_level
,
367 stencil_irb
->mt_layer
,
368 &stencil_draw_x
, &stencil_draw_y
);
369 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
370 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
372 /* If stencil doesn't match depth, then we'll need to rebase stencil
373 * as well. (if we hadn't decided to rebase stencil before, the
374 * post-stencil depth test will also rebase depth to try to match it
377 if (tile_x
!= stencil_tile_x
||
378 tile_y
!= stencil_tile_y
) {
379 rebase_stencil
= true;
384 /* If we have (just) stencil, check it for ignored low bits as well */
386 intel_miptree_get_image_offset(stencil_mt
,
387 stencil_irb
->mt_level
,
388 stencil_irb
->mt_layer
,
389 &stencil_draw_x
, &stencil_draw_y
);
390 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
391 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
393 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
394 rebase_stencil
= true;
396 if (brw
->gen
== 4 && !brw
->is_g4x
) {
397 if (stencil_tile_x
|| stencil_tile_y
)
398 rebase_stencil
= true;
402 if (rebase_stencil
) {
403 perf_debug("HW workaround: blitting stencil level %d to a temporary "
404 "to fix alignment (stencil tile offset %d,%d)\n",
405 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
407 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
408 stencil_mt
= get_stencil_miptree(stencil_irb
);
410 intel_miptree_get_image_offset(stencil_mt
,
411 stencil_irb
->mt_level
,
412 stencil_irb
->mt_layer
,
413 &stencil_draw_x
, &stencil_draw_y
);
414 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
415 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
417 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
418 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
419 intel_renderbuffer_set_draw_offset(depth_irb
);
420 } else if (depth_irb
&& !rebase_depth
) {
421 if (tile_x
!= stencil_tile_x
||
422 tile_y
!= stencil_tile_y
) {
423 perf_debug("HW workaround: blitting depth level %d to a temporary "
424 "to match stencil level %d alignment (depth tile offset "
425 "%d,%d, stencil offset %d,%d)\n",
427 stencil_irb
->mt_level
,
429 stencil_tile_x
, stencil_tile_y
);
431 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
433 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
434 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
436 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
437 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
438 intel_renderbuffer_set_draw_offset(stencil_irb
);
441 WARN_ONCE(stencil_tile_x
!= tile_x
||
442 stencil_tile_y
!= tile_y
,
443 "Rebased stencil tile offset (%d,%d) doesn't match depth "
444 "tile offset (%d,%d).\n",
445 stencil_tile_x
, stencil_tile_y
,
452 tile_x
= stencil_tile_x
;
453 tile_y
= stencil_tile_y
;
456 /* While we just tried to get everything aligned, we may have failed to do
457 * so in the case of rendering to array or 3D textures, where nonzero faces
458 * will still have an offset post-rebase. At least give an informative
461 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
462 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
463 "Truncating offset, bad rendering may occur.\n");
467 /* Now, after rebasing, save off the new dephtstencil state so the hardware
468 * packets can just dereference that without re-calculating tile offsets.
470 brw
->depthstencil
.tile_x
= tile_x
;
471 brw
->depthstencil
.tile_y
= tile_y
;
473 depth_mt
= depth_irb
->mt
;
474 brw
->depthstencil
.depth_mt
= depth_mt
;
475 brw
->depthstencil
.depth_offset
=
476 intel_region_get_aligned_offset(depth_mt
->region
,
477 depth_irb
->draw_x
& ~tile_mask_x
,
478 depth_irb
->draw_y
& ~tile_mask_y
,
480 if (intel_renderbuffer_has_hiz(depth_irb
)) {
481 brw
->depthstencil
.hiz_offset
=
482 intel_region_get_aligned_offset(depth_mt
->region
,
483 depth_irb
->draw_x
& ~tile_mask_x
,
484 (depth_irb
->draw_y
& ~tile_mask_y
) /
490 stencil_mt
= get_stencil_miptree(stencil_irb
);
492 brw
->depthstencil
.stencil_mt
= stencil_mt
;
493 if (stencil_mt
->format
== MESA_FORMAT_S8
) {
494 /* Note: we can't compute the stencil offset using
495 * intel_region_get_aligned_offset(), because stencil_region claims
496 * that the region is untiled even though it's W tiled.
498 brw
->depthstencil
.stencil_offset
=
499 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->region
->pitch
+
500 (stencil_draw_x
& ~tile_mask_x
) * 64;
506 brw_emit_depthbuffer(struct brw_context
*brw
)
508 struct gl_context
*ctx
= &brw
->ctx
;
509 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
511 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
512 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
513 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
514 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
515 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
516 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
517 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
518 bool separate_stencil
= false;
519 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
520 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
521 uint32_t depth_offset
= 0;
522 uint32_t width
= 1, height
= 1;
525 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S8
;
527 /* Gen7 supports only separate stencil */
528 assert(separate_stencil
|| brw
->gen
< 7);
531 /* If there's a packed depth/stencil bound to stencil only, we need to
532 * emit the packed depth/stencil buffer packet.
534 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
535 depth_irb
= stencil_irb
;
536 depth_mt
= stencil_mt
;
539 if (depth_irb
&& depth_mt
) {
540 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
541 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
542 * depthstencil format.
544 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
545 * set to the same value. Gens after 7 implicitly always set
546 * Separate_Stencil_Enable; software cannot disable it.
548 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
549 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
552 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
553 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
555 assert(brw
->gen
< 6 || depth_mt
->region
->tiling
== I915_TILING_Y
);
556 assert(!hiz
|| depth_mt
->region
->tiling
== I915_TILING_Y
);
558 depthbuffer_format
= brw_depthbuffer_format(brw
);
559 depth_surface_type
= BRW_SURFACE_2D
;
560 depth_offset
= brw
->depthstencil
.depth_offset
;
561 width
= depth_irb
->Base
.Base
.Width
;
562 height
= depth_irb
->Base
.Base
.Height
;
563 } else if (separate_stencil
) {
565 * There exists a separate stencil buffer but no depth buffer.
567 * The stencil buffer inherits most of its fields from
568 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
571 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
572 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
573 * [DevGT+]: This field must be set to TRUE.
575 assert(brw
->has_separate_stencil
);
577 depth_surface_type
= BRW_SURFACE_2D
;
578 width
= stencil_irb
->Base
.Base
.Width
;
579 height
= stencil_irb
->Base
.Base
.Height
;
582 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
583 depthbuffer_format
, depth_surface_type
,
584 stencil_mt
, hiz
, separate_stencil
,
585 width
, height
, tile_x
, tile_y
);
589 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
590 struct intel_mipmap_tree
*depth_mt
,
591 uint32_t depth_offset
, uint32_t depthbuffer_format
,
592 uint32_t depth_surface_type
,
593 struct intel_mipmap_tree
*stencil_mt
,
594 bool hiz
, bool separate_stencil
,
595 uint32_t width
, uint32_t height
,
596 uint32_t tile_x
, uint32_t tile_y
)
598 /* Enable the hiz bit if we're doing separate stencil, because it and the
599 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
600 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
601 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
602 * Enable must also be enabled.
604 * [DevGT]: This field must be set to the same value (enabled or
605 * disabled) as Hierarchical Depth Buffer Enable
607 bool enable_hiz_ss
= hiz
|| separate_stencil
;
610 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
611 * non-pipelined state that will need the PIPE_CONTROL workaround.
614 intel_emit_post_sync_nonzero_flush(brw
);
615 intel_emit_depth_stall_flushes(brw
);
621 else if (brw
->is_g4x
|| brw
->gen
== 5)
627 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
628 OUT_BATCH((depth_mt
? depth_mt
->region
->pitch
- 1 : 0) |
629 (depthbuffer_format
<< 18) |
630 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
631 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
632 (BRW_TILEWALK_YMAJOR
<< 26) |
633 ((depth_mt
? depth_mt
->region
->tiling
!= I915_TILING_NONE
: 1)
635 (depth_surface_type
<< 29));
638 OUT_RELOC(depth_mt
->region
->bo
,
639 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
645 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
646 ((height
+ tile_y
- 1) << 19));
649 if (brw
->is_g4x
|| brw
->gen
>= 5)
650 OUT_BATCH(tile_x
| (tile_y
<< 16));
652 assert(tile_x
== 0 && tile_y
== 0);
659 if (hiz
|| separate_stencil
) {
661 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
662 * stencil enable' and 'hiz enable' bits were set. Therefore we must
663 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
664 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
665 * failure to do so causes hangs on gen5 and a stall on gen6.
668 /* Emit hiz buffer. */
670 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_mt
;
672 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
673 OUT_BATCH(hiz_mt
->region
->pitch
- 1);
674 OUT_RELOC(hiz_mt
->region
->bo
,
675 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
676 brw
->depthstencil
.hiz_offset
);
680 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
686 /* Emit stencil buffer. */
687 if (separate_stencil
) {
688 struct intel_region
*region
= stencil_mt
->region
;
691 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
692 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
693 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
694 * The pitch must be set to 2x the value computed based on width, as
695 * the stencil buffer is stored with two rows interleaved.
697 OUT_BATCH(2 * region
->pitch
- 1);
698 OUT_RELOC(region
->bo
,
699 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
700 brw
->depthstencil
.stencil_offset
);
704 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
712 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
713 * params must be emitted.
715 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
716 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
717 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
719 if (brw
->gen
>= 6 || hiz
) {
721 intel_emit_post_sync_nonzero_flush(brw
);
724 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
725 GEN5_DEPTH_CLEAR_VALID
|
727 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
732 const struct brw_tracked_state brw_depthbuffer
= {
734 .mesa
= _NEW_BUFFERS
,
735 .brw
= BRW_NEW_BATCH
,
738 .emit
= brw_emit_depthbuffer
,
743 /***********************************************************************
744 * Polygon stipple packet
747 static void upload_polygon_stipple(struct brw_context
*brw
)
749 struct gl_context
*ctx
= &brw
->ctx
;
753 if (!ctx
->Polygon
.StippleFlag
)
757 intel_emit_post_sync_nonzero_flush(brw
);
760 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
762 /* Polygon stipple is provided in OpenGL order, i.e. bottom
763 * row first. If we're rendering to a window (i.e. the
764 * default frame buffer object, 0), then we need to invert
765 * it to match our pixel layout. But if we're rendering
766 * to a FBO (i.e. any named frame buffer object), we *don't*
767 * need to invert - we already match the layout.
769 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
770 for (i
= 0; i
< 32; i
++)
771 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
774 for (i
= 0; i
< 32; i
++)
775 OUT_BATCH(ctx
->PolygonStipple
[i
]);
780 const struct brw_tracked_state brw_polygon_stipple
= {
782 .mesa
= (_NEW_POLYGONSTIPPLE
|
784 .brw
= BRW_NEW_CONTEXT
,
787 .emit
= upload_polygon_stipple
791 /***********************************************************************
792 * Polygon stipple offset packet
795 static void upload_polygon_stipple_offset(struct brw_context
*brw
)
797 struct gl_context
*ctx
= &brw
->ctx
;
800 if (!ctx
->Polygon
.StippleFlag
)
804 intel_emit_post_sync_nonzero_flush(brw
);
807 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
811 * If we're drawing to a system window we have to invert the Y axis
812 * in order to match the OpenGL pixel coordinate system, and our
813 * offset must be matched to the window position. If we're drawing
814 * to a user-created FBO then our native pixel coordinate system
815 * works just fine, and there's no window system to worry about.
817 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
818 OUT_BATCH((32 - (ctx
->DrawBuffer
->Height
& 31)) & 31);
824 const struct brw_tracked_state brw_polygon_stipple_offset
= {
826 .mesa
= (_NEW_BUFFERS
|
828 .brw
= BRW_NEW_CONTEXT
,
831 .emit
= upload_polygon_stipple_offset
834 /**********************************************************************
837 static void upload_aa_line_parameters(struct brw_context
*brw
)
839 struct gl_context
*ctx
= &brw
->ctx
;
841 if (!ctx
->Line
.SmoothFlag
|| !brw
->has_aa_line_parameters
)
845 intel_emit_post_sync_nonzero_flush(brw
);
847 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
848 /* use legacy aa line coverage computation */
854 const struct brw_tracked_state brw_aa_line_parameters
= {
857 .brw
= BRW_NEW_CONTEXT
,
860 .emit
= upload_aa_line_parameters
863 /***********************************************************************
864 * Line stipple packet
867 static void upload_line_stipple(struct brw_context
*brw
)
869 struct gl_context
*ctx
= &brw
->ctx
;
873 if (!ctx
->Line
.StippleFlag
)
877 intel_emit_post_sync_nonzero_flush(brw
);
880 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
881 OUT_BATCH(ctx
->Line
.StipplePattern
);
885 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
886 tmpi
= tmp
* (1<<16);
887 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
891 tmp
= 1.0 / (GLfloat
) ctx
->Line
.StippleFactor
;
892 tmpi
= tmp
* (1<<13);
893 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
899 const struct brw_tracked_state brw_line_stipple
= {
902 .brw
= BRW_NEW_CONTEXT
,
905 .emit
= upload_line_stipple
909 /***********************************************************************
910 * Misc invariant state packets
914 brw_upload_invariant_state(struct brw_context
*brw
)
916 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */
918 intel_emit_post_sync_nonzero_flush(brw
);
920 /* Select the 3D pipeline (as opposed to media) */
922 OUT_BATCH(brw
->CMD_PIPELINE_SELECT
<< 16 | 0);
926 /* Disable depth offset clamping. */
928 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
934 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
939 OUT_BATCH(brw
->CMD_VF_STATISTICS
<< 16 |
940 (unlikely(INTEL_DEBUG
& DEBUG_STATS
) ? 1 : 0));
944 const struct brw_tracked_state brw_invariant_state
= {
947 .brw
= BRW_NEW_CONTEXT
,
950 .emit
= brw_upload_invariant_state
954 * Define the base addresses which some state is referenced from.
956 * This allows us to avoid having to emit relocations for the objects,
957 * and is actually required for binding table pointers on gen6.
959 * Surface state base address covers binding table pointers and
960 * surface state objects, but not the surfaces that the surface state
963 static void upload_state_base_address( struct brw_context
*brw
)
965 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
966 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
967 * programmed prior to STATE_BASE_ADDRESS.
969 * However, given that the instruction SBA (general state base
970 * address) on this chipset is always set to 0 across X and GL,
971 * maybe this isn't required for us in particular.
975 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
978 intel_emit_post_sync_nonzero_flush(brw
);
981 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
982 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
983 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
984 1); /* General State Base Address Modify Enable */
985 /* Surface state base address:
986 * BINDING_TABLE_STATE
989 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
990 /* Dynamic state base address:
992 * SAMPLER_BORDER_COLOR_STATE
993 * CLIP, SF, WM/CC viewport state
995 * DEPTH_STENCIL_STATE
997 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
998 * Disable is clear, which we rely on)
1000 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
1001 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
1003 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
1004 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1005 1); /* Instruction base address: shader kernels (incl. SIP) */
1007 OUT_BATCH(1); /* General state upper bound */
1008 /* Dynamic state upper bound. Although the documentation says that
1009 * programming it to zero will cause it to be ignored, that is a lie.
1010 * If this isn't programmed to a real bound, the sampler border color
1011 * pointer is rejected, causing border color to mysteriously fail.
1013 OUT_BATCH(0xfffff001);
1014 OUT_BATCH(1); /* Indirect object upper bound */
1015 OUT_BATCH(1); /* Instruction access upper bound */
1017 } else if (brw
->gen
== 5) {
1019 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
1020 OUT_BATCH(1); /* General state base address */
1021 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1022 1); /* Surface state base address */
1023 OUT_BATCH(1); /* Indirect object base address */
1024 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1025 1); /* Instruction base address */
1026 OUT_BATCH(0xfffff001); /* General state upper bound */
1027 OUT_BATCH(1); /* Indirect object upper bound */
1028 OUT_BATCH(1); /* Instruction access upper bound */
1032 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1033 OUT_BATCH(1); /* General state base address */
1034 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1035 1); /* Surface state base address */
1036 OUT_BATCH(1); /* Indirect object base address */
1037 OUT_BATCH(1); /* General state upper bound */
1038 OUT_BATCH(1); /* Indirect object upper bound */
1042 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1043 * STATE_BASE_ADDRESS updates require a reissue of:
1045 * 3DSTATE_PIPELINE_POINTERS
1046 * 3DSTATE_BINDING_TABLE_POINTERS
1047 * MEDIA_STATE_POINTERS
1049 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1050 * 1 part 1 says that the folowing packets must be reissued:
1052 * 3DSTATE_CC_POINTERS
1053 * 3DSTATE_BINDING_TABLE_POINTERS
1054 * 3DSTATE_SAMPLER_STATE_POINTERS
1055 * 3DSTATE_VIEWPORT_STATE_POINTERS
1056 * MEDIA_STATE_POINTERS
1058 * Those are always reissued following SBA updates anyway (new
1059 * batch time), except in the case of the program cache BO
1060 * changing. Having a separate state flag makes the sequence more
1064 brw
->state
.dirty
.brw
|= BRW_NEW_STATE_BASE_ADDRESS
;
1067 const struct brw_tracked_state brw_state_base_address
= {
1070 .brw
= (BRW_NEW_BATCH
|
1071 BRW_NEW_PROGRAM_CACHE
),
1074 .emit
= upload_state_base_address