i965/fs: Lower 32x32 bit multiplication on BXT.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_nir.h"
25 #include "glsl/glsl_parser_extras.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
28
29 static void
30 nir_optimize(nir_shader *nir, bool is_scalar)
31 {
32 bool progress;
33 do {
34 progress = false;
35 nir_lower_vars_to_ssa(nir);
36 nir_validate_shader(nir);
37
38 if (is_scalar) {
39 nir_lower_alu_to_scalar(nir);
40 nir_validate_shader(nir);
41 }
42
43 progress |= nir_copy_prop(nir);
44 nir_validate_shader(nir);
45
46 if (is_scalar) {
47 nir_lower_phis_to_scalar(nir);
48 nir_validate_shader(nir);
49 }
50
51 progress |= nir_copy_prop(nir);
52 nir_validate_shader(nir);
53 progress |= nir_opt_dce(nir);
54 nir_validate_shader(nir);
55 progress |= nir_opt_cse(nir);
56 nir_validate_shader(nir);
57 progress |= nir_opt_peephole_select(nir);
58 nir_validate_shader(nir);
59 progress |= nir_opt_algebraic(nir);
60 nir_validate_shader(nir);
61 progress |= nir_opt_constant_folding(nir);
62 nir_validate_shader(nir);
63 progress |= nir_opt_remove_phis(nir);
64 nir_validate_shader(nir);
65 } while (progress);
66 }
67
68 nir_shader *
69 brw_create_nir(struct brw_context *brw,
70 const struct gl_shader_program *shader_prog,
71 const struct gl_program *prog,
72 gl_shader_stage stage,
73 bool is_scalar)
74 {
75 struct gl_context *ctx = &brw->ctx;
76 const nir_shader_compiler_options *options =
77 ctx->Const.ShaderCompilerOptions[stage].NirOptions;
78 struct gl_shader *shader = shader_prog ? shader_prog->_LinkedShaders[stage] : NULL;
79 bool debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
80 nir_shader *nir;
81
82 /* First, lower the GLSL IR or Mesa IR to NIR */
83 if (shader_prog) {
84 nir = glsl_to_nir(shader, options);
85 } else {
86 nir = prog_to_nir(prog, options);
87 nir_convert_to_ssa(nir); /* turn registers into SSA */
88 }
89 nir_validate_shader(nir);
90
91 nir_lower_global_vars_to_local(nir);
92 nir_validate_shader(nir);
93
94 nir_lower_tex_projector(nir);
95 nir_validate_shader(nir);
96
97 nir_normalize_cubemap_coords(nir);
98 nir_validate_shader(nir);
99
100 nir_split_var_copies(nir);
101 nir_validate_shader(nir);
102
103 nir_optimize(nir, is_scalar);
104
105 /* Lower a bunch of stuff */
106 nir_lower_var_copies(nir);
107 nir_validate_shader(nir);
108
109 /* Get rid of split copies */
110 nir_optimize(nir, is_scalar);
111
112 if (is_scalar) {
113 nir_assign_var_locations_direct_first(nir, &nir->uniforms,
114 &nir->num_direct_uniforms,
115 &nir->num_uniforms,
116 is_scalar);
117 nir_assign_var_locations(&nir->outputs, &nir->num_outputs, is_scalar);
118 } else {
119 nir_assign_var_locations(&nir->uniforms,
120 &nir->num_uniforms,
121 is_scalar);
122
123 foreach_list_typed(nir_variable, var, node, &nir->outputs)
124 var->data.driver_location = var->data.location;
125 }
126 nir_assign_var_locations(&nir->inputs, &nir->num_inputs, is_scalar);
127
128 nir_lower_io(nir, is_scalar);
129
130 nir_validate_shader(nir);
131
132 nir_remove_dead_variables(nir);
133 nir_validate_shader(nir);
134
135 if (shader_prog) {
136 nir_lower_samplers(nir, shader_prog, stage);
137 nir_validate_shader(nir);
138 }
139
140 nir_lower_system_values(nir);
141 nir_validate_shader(nir);
142
143 nir_lower_atomics(nir);
144 nir_validate_shader(nir);
145
146 nir_optimize(nir, is_scalar);
147
148 if (brw->gen >= 6) {
149 /* Try and fuse multiply-adds */
150 nir_opt_peephole_ffma(nir);
151 nir_validate_shader(nir);
152 }
153
154 nir_opt_algebraic_late(nir);
155 nir_validate_shader(nir);
156
157 nir_lower_locals_to_regs(nir);
158 nir_validate_shader(nir);
159
160 nir_lower_to_source_mods(nir);
161 nir_validate_shader(nir);
162 nir_copy_prop(nir);
163 nir_validate_shader(nir);
164 nir_opt_dce(nir);
165 nir_validate_shader(nir);
166
167 if (unlikely(debug_enabled)) {
168 /* Re-index SSA defs so we print more sensible numbers. */
169 nir_foreach_overload(nir, overload) {
170 if (overload->impl)
171 nir_index_ssa_defs(overload->impl);
172 }
173
174 fprintf(stderr, "NIR (SSA form) for %s shader:\n",
175 _mesa_shader_stage_to_string(stage));
176 nir_print_shader(nir, stderr);
177 }
178
179 nir_convert_from_ssa(nir, is_scalar);
180 nir_validate_shader(nir);
181
182 if (!is_scalar) {
183 nir_lower_vec_to_movs(nir);
184 nir_validate_shader(nir);
185 }
186
187 /* This is the last pass we run before we start emitting stuff. It
188 * determines when we need to insert boolean resolves on Gen <= 5. We
189 * run it last because it stashes data in instr->pass_flags and we don't
190 * want that to be squashed by other NIR passes.
191 */
192 if (brw->gen <= 5)
193 brw_nir_analyze_boolean_resolves(nir);
194
195 nir_sweep(nir);
196
197 if (unlikely(debug_enabled)) {
198 fprintf(stderr, "NIR (final form) for %s shader:\n",
199 _mesa_shader_stage_to_string(stage));
200 nir_print_shader(nir, stderr);
201 }
202
203 return nir;
204 }
205
206 enum brw_reg_type
207 brw_type_for_nir_type(nir_alu_type type)
208 {
209 switch (type) {
210 case nir_type_unsigned:
211 return BRW_REGISTER_TYPE_UD;
212 case nir_type_bool:
213 case nir_type_int:
214 return BRW_REGISTER_TYPE_D;
215 case nir_type_float:
216 return BRW_REGISTER_TYPE_F;
217 default:
218 unreachable("unknown type");
219 }
220
221 return BRW_REGISTER_TYPE_F;
222 }
223
224 /* Returns the glsl_base_type corresponding to a nir_alu_type.
225 * This is used by both brw_vec4_nir and brw_fs_nir.
226 */
227 enum glsl_base_type
228 brw_glsl_base_type_for_nir_type(nir_alu_type type)
229 {
230 switch (type) {
231 case nir_type_float:
232 return GLSL_TYPE_FLOAT;
233
234 case nir_type_int:
235 return GLSL_TYPE_INT;
236
237 case nir_type_unsigned:
238 return GLSL_TYPE_UINT;
239
240 default:
241 unreachable("bad type");
242 }
243 }