2 * Copyright © 2014 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "glsl/nir/nir_builder.h"
28 #include "program/prog_to_nir.h"
31 is_input(nir_intrinsic_instr
*intrin
)
33 return intrin
->intrinsic
== nir_intrinsic_load_input
||
34 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
;
38 is_output(nir_intrinsic_instr
*intrin
)
40 return intrin
->intrinsic
== nir_intrinsic_load_output
||
41 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
42 intrin
->intrinsic
== nir_intrinsic_store_output
||
43 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
47 * In many cases, we just add the base and offset together, so there's no
48 * reason to keep them separate. Sometimes, combining them is essential:
49 * if a shader only accesses part of a compound variable (such as a matrix
50 * or array), the variable's base may not actually exist in the VUE map.
52 * This pass adds constant offsets to instr->const_index[0], and resets
53 * the offset source to 0. Non-constant offsets remain unchanged - since
54 * we don't know what part of a compound variable is accessed, we allocate
55 * storage for the entire thing.
57 struct add_const_offset_to_base_params
{
59 nir_variable_mode mode
;
63 add_const_offset_to_base(nir_block
*block
, void *closure
)
65 struct add_const_offset_to_base_params
*params
= closure
;
66 nir_builder
*b
= ¶ms
->b
;
68 nir_foreach_instr_safe(block
, instr
) {
69 if (instr
->type
!= nir_instr_type_intrinsic
)
72 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
74 if ((params
->mode
== nir_var_shader_in
&& is_input(intrin
)) ||
75 (params
->mode
== nir_var_shader_out
&& is_output(intrin
))) {
76 nir_src
*offset
= nir_get_io_offset_src(intrin
);
77 nir_const_value
*const_offset
= nir_src_as_const_value(*offset
);
80 intrin
->const_index
[0] += const_offset
->u
[0];
81 b
->cursor
= nir_before_instr(&intrin
->instr
);
82 nir_instr_rewrite_src(&intrin
->instr
, offset
,
83 nir_src_for_ssa(nir_imm_int(b
, 0)));
92 remap_vs_attrs(nir_block
*block
, void *closure
)
94 GLbitfield64 inputs_read
= *((GLbitfield64
*) closure
);
96 nir_foreach_instr(block
, instr
) {
97 if (instr
->type
!= nir_instr_type_intrinsic
)
100 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
102 if (intrin
->intrinsic
== nir_intrinsic_load_input
) {
103 /* Attributes come in a contiguous block, ordered by their
104 * gl_vert_attrib value. That means we can compute the slot
105 * number for an attribute by masking out the enabled attributes
106 * before it and counting the bits.
108 int attr
= intrin
->const_index
[0];
109 int slot
= _mesa_bitcount_64(inputs_read
& BITFIELD64_MASK(attr
));
111 intrin
->const_index
[0] = 4 * slot
;
118 brw_nir_lower_inputs(nir_shader
*nir
,
119 const struct brw_device_info
*devinfo
,
122 struct add_const_offset_to_base_params params
= {
123 .mode
= nir_var_shader_in
126 switch (nir
->stage
) {
127 case MESA_SHADER_VERTEX
:
128 /* Start with the location of the variable's base. */
129 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
130 var
->data
.driver_location
= var
->data
.location
;
133 /* Now use nir_lower_io to walk dereference chains. Attribute arrays
134 * are loaded as one vec4 per element (or matrix column), so we use
135 * type_size_vec4 here.
137 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
);
140 /* Finally, translate VERT_ATTRIB_* values into the actual registers.
142 * Note that we can use nir->info.inputs_read instead of
143 * key->inputs_read since the two are identical aside from Gen4-5
144 * edge flag differences.
146 GLbitfield64 inputs_read
= nir
->info
.inputs_read
;
148 /* This pass needs actual constants */
149 nir_opt_constant_folding(nir
);
151 nir_foreach_overload(nir
, overload
) {
152 if (overload
->impl
) {
153 nir_builder_init(¶ms
.b
, overload
->impl
);
154 nir_foreach_block(overload
->impl
, add_const_offset_to_base
, ¶ms
);
155 nir_foreach_block(overload
->impl
, remap_vs_attrs
, &inputs_read
);
160 case MESA_SHADER_GEOMETRY
: {
162 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
163 var
->data
.driver_location
= var
->data
.location
;
166 /* The GLSL linker will have already matched up GS inputs and
167 * the outputs of prior stages. The driver does extend VS outputs
168 * in some cases, but only for legacy OpenGL or Gen4-5 hardware,
169 * neither of which offer geometry shader support. So we can
170 * safely ignore that.
172 * For SSO pipelines, we use a fixed VUE map layout based on variable
173 * locations, so we can rely on rendezvous-by-location to make this
176 * However, we need to ignore VARYING_SLOT_PRIMITIVE_ID, as it's not
177 * written by previous stages and shows up via payload magic.
179 struct brw_vue_map input_vue_map
;
180 GLbitfield64 inputs_read
=
181 nir
->info
.inputs_read
& ~VARYING_BIT_PRIMITIVE_ID
;
182 brw_compute_vue_map(devinfo
, &input_vue_map
, inputs_read
,
183 nir
->info
.separate_shader
);
185 /* Start with the slot for the variable's base. */
186 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
187 assert(input_vue_map
.varying_to_slot
[var
->data
.location
] != -1);
188 var
->data
.driver_location
=
189 input_vue_map
.varying_to_slot
[var
->data
.location
];
192 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
193 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
);
197 case MESA_SHADER_FRAGMENT
:
199 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
,
202 case MESA_SHADER_COMPUTE
:
203 /* Compute shaders have no inputs. */
204 assert(exec_list_is_empty(&nir
->inputs
));
207 unreachable("unsupported shader stage");
212 brw_nir_lower_outputs(nir_shader
*nir
, bool is_scalar
)
214 switch (nir
->stage
) {
215 case MESA_SHADER_VERTEX
:
216 case MESA_SHADER_GEOMETRY
:
218 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
,
219 type_size_vec4_times_4
);
220 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4_times_4
);
222 nir_foreach_variable(var
, &nir
->outputs
)
223 var
->data
.driver_location
= var
->data
.location
;
226 case MESA_SHADER_FRAGMENT
:
227 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
,
230 case MESA_SHADER_COMPUTE
:
231 /* Compute shaders have no outputs. */
232 assert(exec_list_is_empty(&nir
->outputs
));
235 unreachable("unsupported shader stage");
240 type_size_scalar_bytes(const struct glsl_type
*type
)
242 return type_size_scalar(type
) * 4;
246 type_size_vec4_bytes(const struct glsl_type
*type
)
248 return type_size_vec4(type
) * 16;
252 brw_nir_lower_uniforms(nir_shader
*nir
, bool is_scalar
)
255 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
256 type_size_scalar_bytes
);
257 nir_lower_io(nir
, nir_var_uniform
, type_size_scalar_bytes
);
259 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
260 type_size_vec4_bytes
);
261 nir_lower_io(nir
, nir_var_uniform
, type_size_vec4_bytes
);
265 #include "util/debug.h"
270 static int should_clone
= -1;
271 if (should_clone
< 1)
272 should_clone
= env_var_as_boolean("NIR_TEST_CLONE", false);
277 #define _OPT(do_pass) (({ \
278 bool this_progress = true; \
280 nir_validate_shader(nir); \
281 if (should_clone_nir()) { \
282 nir_shader *clone = nir_shader_clone(ralloc_parent(nir), nir); \
289 #define OPT(pass, ...) _OPT( \
290 nir_metadata_set_validation_flag(nir); \
291 this_progress = pass(nir ,##__VA_ARGS__); \
292 if (this_progress) { \
294 nir_metadata_check_validation_flag(nir); \
298 #define OPT_V(pass, ...) _OPT( \
299 pass(nir, ##__VA_ARGS__); \
303 nir_optimize(nir_shader
*nir
, bool is_scalar
)
308 OPT_V(nir_lower_vars_to_ssa
);
311 OPT_V(nir_lower_alu_to_scalar
);
317 OPT_V(nir_lower_phis_to_scalar
);
323 OPT(nir_opt_peephole_select
);
324 OPT(nir_opt_algebraic
);
325 OPT(nir_opt_constant_folding
);
326 OPT(nir_opt_dead_cf
);
327 OPT(nir_opt_remove_phis
);
334 /* Does some simple lowering and runs the standard suite of optimizations
336 * This is intended to be called more-or-less directly after you get the
337 * shader out of GLSL or some other source. While it is geared towards i965,
338 * it is not at all generator-specific except for the is_scalar flag. Even
339 * there, it is safe to call with is_scalar = false for a shader that is
340 * intended for the FS backend as long as nir_optimize is called again with
341 * is_scalar = true to scalarize everything prior to code gen.
344 brw_preprocess_nir(nir_shader
*nir
, bool is_scalar
)
346 bool progress
; /* Written by OPT and OPT_V */
349 if (nir
->stage
== MESA_SHADER_GEOMETRY
)
350 OPT(nir_lower_gs_intrinsics
);
352 static const nir_lower_tex_options tex_options
= {
356 OPT(nir_lower_tex
, &tex_options
);
357 OPT(nir_normalize_cubemap_coords
);
359 OPT(nir_lower_global_vars_to_local
);
361 OPT(nir_split_var_copies
);
363 nir
= nir_optimize(nir
, is_scalar
);
365 /* Lower a bunch of stuff */
366 OPT_V(nir_lower_var_copies
);
368 /* Get rid of split copies */
369 nir
= nir_optimize(nir
, is_scalar
);
371 OPT(nir_remove_dead_variables
);
376 /* Lowers inputs, outputs, uniforms, and samplers for i965
378 * This function does all of the standard lowering prior to post-processing.
379 * The lowering done is highly gen, stage, and backend-specific. The
380 * shader_prog parameter is optional and is used only for lowering sampler
381 * derefs and atomics for GLSL shaders.
384 brw_lower_nir(nir_shader
*nir
,
385 const struct brw_device_info
*devinfo
,
386 const struct gl_shader_program
*shader_prog
,
389 bool progress
; /* Written by OPT and OPT_V */
392 OPT_V(brw_nir_lower_inputs
, devinfo
, is_scalar
);
393 OPT_V(brw_nir_lower_outputs
, is_scalar
);
394 OPT_V(brw_nir_lower_uniforms
, is_scalar
);
395 OPT_V(nir_lower_io
, nir_var_all
, is_scalar
? type_size_scalar
: type_size_vec4
);
398 OPT_V(nir_lower_samplers
, shader_prog
);
401 OPT(nir_lower_system_values
);
404 OPT_V(nir_lower_atomics
, shader_prog
);
407 return nir_optimize(nir
, is_scalar
);
410 /* Prepare the given shader for codegen
412 * This function is intended to be called right before going into the actual
413 * backend and is highly backend-specific. Also, once this function has been
414 * called on a shader, it will no longer be in SSA form so most optimizations
418 brw_postprocess_nir(nir_shader
*nir
,
419 const struct brw_device_info
*devinfo
,
423 (INTEL_DEBUG
& intel_debug_flag_for_shader_stage(nir
->stage
));
425 bool progress
; /* Written by OPT and OPT_V */
428 if (devinfo
->gen
>= 6) {
429 /* Try and fuse multiply-adds */
430 OPT(brw_nir_opt_peephole_ffma
);
433 OPT(nir_opt_algebraic_late
);
435 OPT(nir_lower_locals_to_regs
);
437 OPT_V(nir_lower_to_source_mods
);
441 if (unlikely(debug_enabled
)) {
442 /* Re-index SSA defs so we print more sensible numbers. */
443 nir_foreach_overload(nir
, overload
) {
445 nir_index_ssa_defs(overload
->impl
);
448 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
449 _mesa_shader_stage_to_string(nir
->stage
));
450 nir_print_shader(nir
, stderr
);
453 OPT_V(nir_convert_from_ssa
, true);
456 OPT_V(nir_move_vec_src_uses_to_dest
);
457 OPT(nir_lower_vec_to_movs
);
460 /* This is the last pass we run before we start emitting stuff. It
461 * determines when we need to insert boolean resolves on Gen <= 5. We
462 * run it last because it stashes data in instr->pass_flags and we don't
463 * want that to be squashed by other NIR passes.
465 if (devinfo
->gen
<= 5)
466 brw_nir_analyze_boolean_resolves(nir
);
470 if (unlikely(debug_enabled
)) {
471 fprintf(stderr
, "NIR (final form) for %s shader:\n",
472 _mesa_shader_stage_to_string(nir
->stage
));
473 nir_print_shader(nir
, stderr
);
480 brw_create_nir(struct brw_context
*brw
,
481 const struct gl_shader_program
*shader_prog
,
482 const struct gl_program
*prog
,
483 gl_shader_stage stage
,
486 struct gl_context
*ctx
= &brw
->ctx
;
487 const struct brw_device_info
*devinfo
= brw
->intelScreen
->devinfo
;
488 const nir_shader_compiler_options
*options
=
489 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
493 /* First, lower the GLSL IR or Mesa IR to NIR */
495 nir
= glsl_to_nir(shader_prog
, stage
, options
);
497 nir
= prog_to_nir(prog
, options
);
498 OPT_V(nir_convert_to_ssa
); /* turn registers into SSA */
500 nir_validate_shader(nir
);
504 nir
= brw_preprocess_nir(nir
, is_scalar
);
505 nir
= brw_lower_nir(nir
, devinfo
, shader_prog
, is_scalar
);
511 brw_nir_apply_sampler_key(nir_shader
*nir
,
512 const struct brw_device_info
*devinfo
,
513 const struct brw_sampler_prog_key_data
*key_tex
,
516 nir_lower_tex_options tex_options
= { 0 };
518 /* Iron Lake and prior require lowering of all rectangle textures */
519 if (devinfo
->gen
< 6)
520 tex_options
.lower_rect
= true;
522 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
523 if (devinfo
->gen
< 8) {
524 tex_options
.saturate_s
= key_tex
->gl_clamp_mask
[0];
525 tex_options
.saturate_t
= key_tex
->gl_clamp_mask
[1];
526 tex_options
.saturate_r
= key_tex
->gl_clamp_mask
[2];
529 /* Prior to Haswell, we have to fake texture swizzle */
530 for (unsigned s
= 0; s
< MAX_SAMPLERS
; s
++) {
531 if (key_tex
->swizzles
[s
] == SWIZZLE_NOOP
)
534 tex_options
.swizzle_result
|= (1 << s
);
535 for (unsigned c
= 0; c
< 4; c
++)
536 tex_options
.swizzles
[s
][c
] = GET_SWZ(key_tex
->swizzles
[s
], c
);
539 if (nir_lower_tex(nir
, &tex_options
)) {
540 nir_validate_shader(nir
);
541 nir
= nir_optimize(nir
, is_scalar
);
548 brw_type_for_nir_type(nir_alu_type type
)
552 return BRW_REGISTER_TYPE_UD
;
555 return BRW_REGISTER_TYPE_D
;
557 return BRW_REGISTER_TYPE_F
;
559 unreachable("unknown type");
562 return BRW_REGISTER_TYPE_F
;
565 /* Returns the glsl_base_type corresponding to a nir_alu_type.
566 * This is used by both brw_vec4_nir and brw_fs_nir.
569 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
573 return GLSL_TYPE_FLOAT
;
576 return GLSL_TYPE_INT
;
579 return GLSL_TYPE_UINT
;
582 unreachable("bad type");