src/mesa/drivers/dri/i965/brw_nir.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_nir.h"
  25 #include "brw_shader.h"
  26 #include "compiler/glsl_types.h"
  27 #include "compiler/nir/glsl_to_nir.h"
  28 #include "compiler/nir/nir_builder.h"
  29 #include "program/prog_to_nir.h"
  30 #include "program/prog_parameter.h"
  31
  32 static bool
  33 is_input(nir_intrinsic_instr *intrin)
  34 {
  35    return intrin->intrinsic == nir_intrinsic_load_input ||
  36           intrin->intrinsic == nir_intrinsic_load_per_vertex_input;
  37 }
  38
  39 static bool
  40 is_output(nir_intrinsic_instr *intrin)
  41 {
  42    return intrin->intrinsic == nir_intrinsic_load_output ||
  43           intrin->intrinsic == nir_intrinsic_load_per_vertex_output ||
  44           intrin->intrinsic == nir_intrinsic_store_output ||
  45           intrin->intrinsic == nir_intrinsic_store_per_vertex_output;
  46 }
  47
  48 /**
  49  * In many cases, we just add the base and offset together, so there's no
  50  * reason to keep them separate.  Sometimes, combining them is essential:
  51  * if a shader only accesses part of a compound variable (such as a matrix
  52  * or array), the variable's base may not actually exist in the VUE map.
  53  *
  54  * This pass adds constant offsets to instr->const_index[0], and resets
  55  * the offset source to 0.  Non-constant offsets remain unchanged - since
  56  * we don't know what part of a compound variable is accessed, we allocate
  57  * storage for the entire thing.
  58  */
  59
  60 static bool
  61 add_const_offset_to_base_block(nir_block *block, nir_builder *b,
  62                                nir_variable_mode mode)
  63 {
  64    nir_foreach_instr_safe(instr, block) {
  65       if (instr->type != nir_instr_type_intrinsic)
  66          continue;
  67
  68       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
  69
  70       if ((mode == nir_var_shader_in && is_input(intrin)) ||
  71           (mode == nir_var_shader_out && is_output(intrin))) {
  72          nir_src *offset = nir_get_io_offset_src(intrin);
  73          nir_const_value *const_offset = nir_src_as_const_value(*offset);
  74
  75          if (const_offset) {
  76             intrin->const_index[0] += const_offset->u32[0];
  77             b->cursor = nir_before_instr(&intrin->instr);
  78             nir_instr_rewrite_src(&intrin->instr, offset,
  79                                   nir_src_for_ssa(nir_imm_int(b, 0)));
  80          }
  81       }
  82    }
  83    return true;
  84 }
  85
  86 static void
  87 add_const_offset_to_base(nir_shader *nir, nir_variable_mode mode)
  88 {
  89    nir_foreach_function(f, nir) {
  90       if (f->impl) {
  91          nir_builder b;
  92          nir_builder_init(&b, f->impl);
  93          nir_foreach_block(block, f->impl) {
  94             add_const_offset_to_base_block(block, &b, mode);
  95          }
  96       }
  97    }
  98 }
  99
 100 static bool
 101 remap_vs_attrs(nir_block *block, struct nir_shader_info *nir_info)
 102 {
 103    nir_foreach_instr(instr, block) {
 104       if (instr->type != nir_instr_type_intrinsic)
 105          continue;
 106
 107       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 108
 109       if (intrin->intrinsic == nir_intrinsic_load_input) {
 110          /* Attributes come in a contiguous block, ordered by their
 111           * gl_vert_attrib value.  That means we can compute the slot
 112           * number for an attribute by masking out the enabled attributes
 113           * before it and counting the bits.
 114           */
 115          int attr = intrin->const_index[0];
 116          int slot = _mesa_bitcount_64(nir_info->inputs_read &
 117                                       BITFIELD64_MASK(attr));
 118          int dslot = _mesa_bitcount_64(nir_info->double_inputs_read &
 119                                        BITFIELD64_MASK(attr));
 120          intrin->const_index[0] = 4 * (slot + dslot);
 121       }
 122    }
 123    return true;
 124 }
 125
 126 static bool
 127 remap_inputs_with_vue_map(nir_block *block, const struct brw_vue_map *vue_map)
 128 {
 129    nir_foreach_instr(instr, block) {
 130       if (instr->type != nir_instr_type_intrinsic)
 131          continue;
 132
 133       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 134
 135       if (intrin->intrinsic == nir_intrinsic_load_input ||
 136           intrin->intrinsic == nir_intrinsic_load_per_vertex_input) {
 137          int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
 138          assert(vue_slot != -1);
 139          intrin->const_index[0] = vue_slot;
 140       }
 141    }
 142    return true;
 143 }
 144
 145 static bool
 146 remap_patch_urb_offsets(nir_block *block, nir_builder *b,
 147                         const struct brw_vue_map *vue_map)
 148 {
 149    nir_foreach_instr_safe(instr, block) {
 150       if (instr->type != nir_instr_type_intrinsic)
 151          continue;
 152
 153       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 154
 155       gl_shader_stage stage = b->shader->stage;
 156
 157       if ((stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) ||
 158           (stage == MESA_SHADER_TESS_EVAL && is_input(intrin))) {
 159          int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
 160          assert(vue_slot != -1);
 161          intrin->const_index[0] = vue_slot;
 162
 163          nir_src *vertex = nir_get_io_vertex_index_src(intrin);
 164          if (vertex) {
 165             nir_const_value *const_vertex = nir_src_as_const_value(*vertex);
 166             if (const_vertex) {
 167                intrin->const_index[0] += const_vertex->u32[0] *
 168                                          vue_map->num_per_vertex_slots;
 169             } else {
 170                b->cursor = nir_before_instr(&intrin->instr);
 171
 172                /* Multiply by the number of per-vertex slots. */
 173                nir_ssa_def *vertex_offset =
 174                   nir_imul(b,
 175                            nir_ssa_for_src(b, *vertex, 1),
 176                            nir_imm_int(b,
 177                                        vue_map->num_per_vertex_slots));
 178
 179                /* Add it to the existing offset */
 180                nir_src *offset = nir_get_io_offset_src(intrin);
 181                nir_ssa_def *total_offset =
 182                   nir_iadd(b, vertex_offset,
 183                            nir_ssa_for_src(b, *offset, 1));
 184
 185                nir_instr_rewrite_src(&intrin->instr, offset,
 186                                      nir_src_for_ssa(total_offset));
 187             }
 188          }
 189       }
 190    }
 191    return true;
 192 }
 193
 194 void
 195 brw_nir_lower_vs_inputs(nir_shader *nir,
 196                         const struct brw_device_info *devinfo,
 197                         bool is_scalar,
 198                         bool use_legacy_snorm_formula,
 199                         const uint8_t *vs_attrib_wa_flags)
 200 {
 201    /* Start with the location of the variable's base. */
 202    foreach_list_typed(nir_variable, var, node, &nir->inputs) {
 203       var->data.driver_location = var->data.location;
 204    }
 205
 206    /* Now use nir_lower_io to walk dereference chains.  Attribute arrays are
 207     * loaded as one vec4 or dvec4 per element (or matrix column), depending on
 208     * whether it is a double-precision type or not.
 209     */
 210    nir_lower_io(nir, nir_var_shader_in, type_size_vs_input);
 211
 212    /* This pass needs actual constants */
 213    nir_opt_constant_folding(nir);
 214
 215    add_const_offset_to_base(nir, nir_var_shader_in);
 216
 217    brw_nir_apply_attribute_workarounds(nir, use_legacy_snorm_formula,
 218                                        vs_attrib_wa_flags);
 219
 220    if (is_scalar) {
 221       /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
 222
 223       nir_foreach_function(function, nir) {
 224          if (function->impl) {
 225             nir_foreach_block(block, function->impl) {
 226                remap_vs_attrs(block, &nir->info);
 227             }
 228          }
 229       }
 230    }
 231 }
 232
 233 void
 234 brw_nir_lower_vue_inputs(nir_shader *nir, bool is_scalar,
 235                          const struct brw_vue_map *vue_map)
 236 {
 237    foreach_list_typed(nir_variable, var, node, &nir->inputs) {
 238       var->data.driver_location = var->data.location;
 239    }
 240
 241    /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
 242    nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
 243
 244    if (is_scalar || nir->stage != MESA_SHADER_GEOMETRY) {
 245       /* This pass needs actual constants */
 246       nir_opt_constant_folding(nir);
 247
 248       add_const_offset_to_base(nir, nir_var_shader_in);
 249
 250       nir_foreach_function(function, nir) {
 251          if (function->impl) {
 252             nir_foreach_block(block, function->impl) {
 253                remap_inputs_with_vue_map(block, vue_map);
 254             }
 255          }
 256       }
 257    }
 258 }
 259
 260 void
 261 brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue_map)
 262 {
 263    foreach_list_typed(nir_variable, var, node, &nir->inputs) {
 264       var->data.driver_location = var->data.location;
 265    }
 266
 267    nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
 268
 269    /* This pass needs actual constants */
 270    nir_opt_constant_folding(nir);
 271
 272    add_const_offset_to_base(nir, nir_var_shader_in);
 273
 274    nir_foreach_function(function, nir) {
 275       if (function->impl) {
 276          nir_builder b;
 277          nir_builder_init(&b, function->impl);
 278          nir_foreach_block(block, function->impl) {
 279             remap_patch_urb_offsets(block, &b, vue_map);
 280          }
 281       }
 282    }
 283 }
 284
 285 void
 286 brw_nir_lower_fs_inputs(nir_shader *nir)
 287 {
 288    nir_assign_var_locations(&nir->inputs, &nir->num_inputs, type_size_scalar);
 289    nir_lower_io(nir, nir_var_shader_in, type_size_scalar);
 290 }
 291
 292 void
 293 brw_nir_lower_vue_outputs(nir_shader *nir,
 294                           bool is_scalar)
 295 {
 296    if (is_scalar) {
 297       nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
 298                                type_size_vec4_times_4);
 299       nir_lower_io(nir, nir_var_shader_out, type_size_vec4_times_4);
 300    } else {
 301       nir_foreach_variable(var, &nir->outputs)
 302          var->data.driver_location = var->data.location;
 303       nir_lower_io(nir, nir_var_shader_out, type_size_vec4);
 304    }
 305 }
 306
 307 void
 308 brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue_map)
 309 {
 310    nir_foreach_variable(var, &nir->outputs) {
 311       var->data.driver_location = var->data.location;
 312    }
 313
 314    nir_lower_io(nir, nir_var_shader_out, type_size_vec4);
 315
 316    /* This pass needs actual constants */
 317    nir_opt_constant_folding(nir);
 318
 319    add_const_offset_to_base(nir, nir_var_shader_out);
 320
 321    nir_foreach_function(function, nir) {
 322       if (function->impl) {
 323          nir_builder b;
 324          nir_builder_init(&b, function->impl);
 325          nir_foreach_block(block, function->impl) {
 326             remap_patch_urb_offsets(block, &b, vue_map);
 327          }
 328       }
 329    }
 330 }
 331
 332 void
 333 brw_nir_lower_fs_outputs(nir_shader *nir)
 334 {
 335    nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
 336                             type_size_scalar);
 337    nir_lower_io(nir, nir_var_shader_out, type_size_scalar);
 338 }
 339
 340 static int
 341 type_size_scalar_bytes(const struct glsl_type *type)
 342 {
 343    return type_size_scalar(type) * 4;
 344 }
 345
 346 static int
 347 type_size_vec4_bytes(const struct glsl_type *type)
 348 {
 349    return type_size_vec4(type) * 16;
 350 }
 351
 352 static void
 353 brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
 354 {
 355    if (is_scalar) {
 356       nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
 357                                type_size_scalar_bytes);
 358       nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes);
 359    } else {
 360       nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
 361                                type_size_vec4_bytes);
 362       nir_lower_io(nir, nir_var_uniform, type_size_vec4_bytes);
 363    }
 364 }
 365
 366 void
 367 brw_nir_lower_cs_shared(nir_shader *nir)
 368 {
 369    nir_assign_var_locations(&nir->shared, &nir->num_shared,
 370                             type_size_scalar_bytes);
 371    nir_lower_io(nir, nir_var_shared, type_size_scalar_bytes);
 372 }
 373
 374 #define OPT(pass, ...) ({                                  \
 375    bool this_progress = false;                             \
 376    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 377    if (this_progress)                                      \
 378       progress = true;                                     \
 379    this_progress;                                          \
 380 })
 381
 382 #define OPT_V(pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 383
 384 static nir_shader *
 385 nir_optimize(nir_shader *nir, bool is_scalar)
 386 {
 387    bool progress;
 388    do {
 389       progress = false;
 390       OPT_V(nir_lower_vars_to_ssa);
 391
 392       if (is_scalar) {
 393          OPT_V(nir_lower_alu_to_scalar);
 394       }
 395
 396       OPT(nir_copy_prop);
 397
 398       if (is_scalar) {
 399          OPT_V(nir_lower_phis_to_scalar);
 400       }
 401
 402       OPT(nir_copy_prop);
 403       OPT(nir_opt_dce);
 404       OPT(nir_opt_cse);
 405       OPT(nir_opt_peephole_select);
 406       OPT(nir_opt_algebraic);
 407       OPT(nir_opt_constant_folding);
 408       OPT(nir_opt_dead_cf);
 409       OPT(nir_opt_remove_phis);
 410       OPT(nir_opt_undef);
 411       OPT_V(nir_lower_doubles, nir_lower_drcp |
 412                                nir_lower_dsqrt |
 413                                nir_lower_drsq |
 414                                nir_lower_dtrunc |
 415                                nir_lower_dfloor |
 416                                nir_lower_dceil |
 417                                nir_lower_dfract |
 418                                nir_lower_dround_even |
 419                                nir_lower_dmod);
 420       OPT_V(nir_lower_double_pack);
 421    } while (progress);
 422
 423    return nir;
 424 }
 425
 426 /* Does some simple lowering and runs the standard suite of optimizations
 427  *
 428  * This is intended to be called more-or-less directly after you get the
 429  * shader out of GLSL or some other source.  While it is geared towards i965,
 430  * it is not at all generator-specific except for the is_scalar flag.  Even
 431  * there, it is safe to call with is_scalar = false for a shader that is
 432  * intended for the FS backend as long as nir_optimize is called again with
 433  * is_scalar = true to scalarize everything prior to code gen.
 434  */
 435 nir_shader *
 436 brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
 437 {
 438    bool progress; /* Written by OPT and OPT_V */
 439    (void)progress;
 440
 441    const bool is_scalar = compiler->scalar_stage[nir->stage];
 442
 443    if (nir->stage == MESA_SHADER_GEOMETRY)
 444       OPT(nir_lower_gs_intrinsics);
 445
 446    if (compiler->precise_trig)
 447       OPT(brw_nir_apply_trig_workarounds);
 448
 449    static const nir_lower_tex_options tex_options = {
 450       .lower_txp = ~0,
 451    };
 452
 453    OPT(nir_lower_tex, &tex_options);
 454    OPT(nir_normalize_cubemap_coords);
 455
 456    OPT(nir_lower_global_vars_to_local);
 457
 458    OPT(nir_split_var_copies);
 459
 460    nir = nir_optimize(nir, is_scalar);
 461
 462    if (is_scalar) {
 463       OPT_V(nir_lower_load_const_to_scalar);
 464    }
 465
 466    /* Lower a bunch of stuff */
 467    OPT_V(nir_lower_var_copies);
 468
 469    /* Get rid of split copies */
 470    nir = nir_optimize(nir, is_scalar);
 471
 472    OPT(nir_remove_dead_variables, nir_var_local);
 473
 474    return nir;
 475 }
 476
 477 /* Prepare the given shader for codegen
 478  *
 479  * This function is intended to be called right before going into the actual
 480  * backend and is highly backend-specific.  Also, once this function has been
 481  * called on a shader, it will no longer be in SSA form so most optimizations
 482  * will not work.
 483  */
 484 nir_shader *
 485 brw_postprocess_nir(nir_shader *nir,
 486                     const struct brw_device_info *devinfo,
 487                     bool is_scalar)
 488 {
 489    bool debug_enabled =
 490       (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->stage));
 491
 492    bool progress; /* Written by OPT and OPT_V */
 493    (void)progress;
 494
 495    nir = nir_optimize(nir, is_scalar);
 496
 497    if (devinfo->gen >= 6) {
 498       /* Try and fuse multiply-adds */
 499       OPT(brw_nir_opt_peephole_ffma);
 500    }
 501
 502    OPT(nir_opt_algebraic_late);
 503
 504    OPT(nir_lower_locals_to_regs);
 505
 506    OPT_V(nir_lower_to_source_mods);
 507    OPT(nir_copy_prop);
 508    OPT(nir_opt_dce);
 509
 510    if (unlikely(debug_enabled)) {
 511       /* Re-index SSA defs so we print more sensible numbers. */
 512       nir_foreach_function(function, nir) {
 513          if (function->impl)
 514             nir_index_ssa_defs(function->impl);
 515       }
 516
 517       fprintf(stderr, "NIR (SSA form) for %s shader:\n",
 518               _mesa_shader_stage_to_string(nir->stage));
 519       nir_print_shader(nir, stderr);
 520    }
 521
 522    OPT_V(nir_convert_from_ssa, true);
 523
 524    if (!is_scalar) {
 525       OPT_V(nir_move_vec_src_uses_to_dest);
 526       OPT(nir_lower_vec_to_movs);
 527    }
 528
 529    /* This is the last pass we run before we start emitting stuff.  It
 530     * determines when we need to insert boolean resolves on Gen <= 5.  We
 531     * run it last because it stashes data in instr->pass_flags and we don't
 532     * want that to be squashed by other NIR passes.
 533     */
 534    if (devinfo->gen <= 5)
 535       brw_nir_analyze_boolean_resolves(nir);
 536
 537    nir_sweep(nir);
 538
 539    if (unlikely(debug_enabled)) {
 540       fprintf(stderr, "NIR (final form) for %s shader:\n",
 541               _mesa_shader_stage_to_string(nir->stage));
 542       nir_print_shader(nir, stderr);
 543    }
 544
 545    return nir;
 546 }
 547
 548 nir_shader *
 549 brw_create_nir(struct brw_context *brw,
 550                const struct gl_shader_program *shader_prog,
 551                const struct gl_program *prog,
 552                gl_shader_stage stage,
 553                bool is_scalar)
 554 {
 555    struct gl_context *ctx = &brw->ctx;
 556    const nir_shader_compiler_options *options =
 557       ctx->Const.ShaderCompilerOptions[stage].NirOptions;
 558    bool progress;
 559    nir_shader *nir;
 560
 561    /* First, lower the GLSL IR or Mesa IR to NIR */
 562    if (shader_prog) {
 563       nir = glsl_to_nir(shader_prog, stage, options);
 564       nir_remove_dead_variables(nir, nir_var_shader_in | nir_var_shader_out);
 565       OPT_V(nir_lower_io_to_temporaries,
 566             nir_shader_get_entrypoint(nir),
 567             true, false);
 568    } else {
 569       nir = prog_to_nir(prog, options);
 570       OPT_V(nir_convert_to_ssa); /* turn registers into SSA */
 571    }
 572    nir_validate_shader(nir);
 573
 574    (void)progress;
 575
 576    nir = brw_preprocess_nir(brw->intelScreen->compiler, nir);
 577
 578    if (stage == MESA_SHADER_FRAGMENT) {
 579       static const struct nir_lower_wpos_ytransform_options wpos_options = {
 580          .state_tokens = {STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM, 0, 0, 0},
 581          .fs_coord_pixel_center_integer = 1,
 582          .fs_coord_origin_upper_left = 1,
 583       };
 584       _mesa_add_state_reference(prog->Parameters,
 585                                 (gl_state_index *) wpos_options.state_tokens);
 586
 587       OPT(nir_lower_wpos_ytransform, &wpos_options);
 588    }
 589
 590    OPT(nir_lower_system_values);
 591    OPT_V(brw_nir_lower_uniforms, is_scalar);
 592
 593    if (shader_prog) {
 594       OPT_V(nir_lower_samplers, shader_prog);
 595       OPT_V(nir_lower_atomics, shader_prog);
 596    }
 597
 598    return nir;
 599 }
 600
 601 nir_shader *
 602 brw_nir_apply_sampler_key(nir_shader *nir,
 603                           const struct brw_device_info *devinfo,
 604                           const struct brw_sampler_prog_key_data *key_tex,
 605                           bool is_scalar)
 606 {
 607    nir_lower_tex_options tex_options = { 0 };
 608
 609    /* Iron Lake and prior require lowering of all rectangle textures */
 610    if (devinfo->gen < 6)
 611       tex_options.lower_rect = true;
 612
 613    /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
 614    if (devinfo->gen < 8) {
 615       tex_options.saturate_s = key_tex->gl_clamp_mask[0];
 616       tex_options.saturate_t = key_tex->gl_clamp_mask[1];
 617       tex_options.saturate_r = key_tex->gl_clamp_mask[2];
 618    }
 619
 620    /* Prior to Haswell, we have to fake texture swizzle */
 621    for (unsigned s = 0; s < MAX_SAMPLERS; s++) {
 622       if (key_tex->swizzles[s] == SWIZZLE_NOOP)
 623          continue;
 624
 625       tex_options.swizzle_result |= (1 << s);
 626       for (unsigned c = 0; c < 4; c++)
 627          tex_options.swizzles[s][c] = GET_SWZ(key_tex->swizzles[s], c);
 628    }
 629
 630    if (nir_lower_tex(nir, &tex_options)) {
 631       nir_validate_shader(nir);
 632       nir = nir_optimize(nir, is_scalar);
 633    }
 634
 635    return nir;
 636 }
 637
 638 enum brw_reg_type
 639 brw_type_for_nir_type(nir_alu_type type)
 640 {
 641    switch (type) {
 642    case nir_type_uint:
 643    case nir_type_uint32:
 644       return BRW_REGISTER_TYPE_UD;
 645    case nir_type_bool:
 646    case nir_type_int:
 647    case nir_type_bool32:
 648    case nir_type_int32:
 649       return BRW_REGISTER_TYPE_D;
 650    case nir_type_float:
 651    case nir_type_float32:
 652       return BRW_REGISTER_TYPE_F;
 653    case nir_type_float64:
 654       return BRW_REGISTER_TYPE_DF;
 655    case nir_type_int64:
 656    case nir_type_uint64:
 657       /* TODO we should only see these in moves, so for now it's ok, but when
 658        * we add actual 64-bit integer support we should fix this.
 659        */
 660       return BRW_REGISTER_TYPE_DF;
 661    default:
 662       unreachable("unknown type");
 663    }
 664
 665    return BRW_REGISTER_TYPE_F;
 666 }
 667
 668 /* Returns the glsl_base_type corresponding to a nir_alu_type.
 669  * This is used by both brw_vec4_nir and brw_fs_nir.
 670  */
 671 enum glsl_base_type
 672 brw_glsl_base_type_for_nir_type(nir_alu_type type)
 673 {
 674    switch (type) {
 675    case nir_type_float:
 676    case nir_type_float32:
 677       return GLSL_TYPE_FLOAT;
 678
 679    case nir_type_float64:
 680       return GLSL_TYPE_DOUBLE;
 681
 682    case nir_type_int:
 683    case nir_type_int32:
 684       return GLSL_TYPE_INT;
 685
 686    case nir_type_uint:
 687    case nir_type_uint32:
 688       return GLSL_TYPE_UINT;
 689
 690    default:
 691       unreachable("bad type");
 692    }
 693 }