2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "compiler/glsl_types.h"
27 #include "compiler/nir/nir_builder.h"
30 is_input(nir_intrinsic_instr
*intrin
)
32 return intrin
->intrinsic
== nir_intrinsic_load_input
||
33 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
||
34 intrin
->intrinsic
== nir_intrinsic_load_interpolated_input
;
38 is_output(nir_intrinsic_instr
*intrin
)
40 return intrin
->intrinsic
== nir_intrinsic_load_output
||
41 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
42 intrin
->intrinsic
== nir_intrinsic_store_output
||
43 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
47 * In many cases, we just add the base and offset together, so there's no
48 * reason to keep them separate. Sometimes, combining them is essential:
49 * if a shader only accesses part of a compound variable (such as a matrix
50 * or array), the variable's base may not actually exist in the VUE map.
52 * This pass adds constant offsets to instr->const_index[0], and resets
53 * the offset source to 0. Non-constant offsets remain unchanged - since
54 * we don't know what part of a compound variable is accessed, we allocate
55 * storage for the entire thing.
59 add_const_offset_to_base_block(nir_block
*block
, nir_builder
*b
,
60 nir_variable_mode mode
)
62 nir_foreach_instr_safe(instr
, block
) {
63 if (instr
->type
!= nir_instr_type_intrinsic
)
66 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
68 if ((mode
== nir_var_shader_in
&& is_input(intrin
)) ||
69 (mode
== nir_var_shader_out
&& is_output(intrin
))) {
70 nir_src
*offset
= nir_get_io_offset_src(intrin
);
71 nir_const_value
*const_offset
= nir_src_as_const_value(*offset
);
74 intrin
->const_index
[0] += const_offset
->u32
[0];
75 b
->cursor
= nir_before_instr(&intrin
->instr
);
76 nir_instr_rewrite_src(&intrin
->instr
, offset
,
77 nir_src_for_ssa(nir_imm_int(b
, 0)));
85 add_const_offset_to_base(nir_shader
*nir
, nir_variable_mode mode
)
87 nir_foreach_function(f
, nir
) {
90 nir_builder_init(&b
, f
->impl
);
91 nir_foreach_block(block
, f
->impl
) {
92 add_const_offset_to_base_block(block
, &b
, mode
);
99 remap_vs_attrs(nir_block
*block
, struct nir_shader_info
*nir_info
)
101 nir_foreach_instr(instr
, block
) {
102 if (instr
->type
!= nir_instr_type_intrinsic
)
105 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
107 if (intrin
->intrinsic
== nir_intrinsic_load_input
) {
108 /* Attributes come in a contiguous block, ordered by their
109 * gl_vert_attrib value. That means we can compute the slot
110 * number for an attribute by masking out the enabled attributes
111 * before it and counting the bits.
113 int attr
= intrin
->const_index
[0];
114 int slot
= _mesa_bitcount_64(nir_info
->inputs_read
&
115 BITFIELD64_MASK(attr
));
116 int dslot
= _mesa_bitcount_64(nir_info
->double_inputs_read
&
117 BITFIELD64_MASK(attr
));
118 intrin
->const_index
[0] = 4 * (slot
+ dslot
);
125 remap_inputs_with_vue_map(nir_block
*block
, const struct brw_vue_map
*vue_map
)
127 nir_foreach_instr(instr
, block
) {
128 if (instr
->type
!= nir_instr_type_intrinsic
)
131 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
133 if (intrin
->intrinsic
== nir_intrinsic_load_input
||
134 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
) {
135 int vue_slot
= vue_map
->varying_to_slot
[intrin
->const_index
[0]];
136 assert(vue_slot
!= -1);
137 intrin
->const_index
[0] = vue_slot
;
144 remap_patch_urb_offsets(nir_block
*block
, nir_builder
*b
,
145 const struct brw_vue_map
*vue_map
)
147 nir_foreach_instr_safe(instr
, block
) {
148 if (instr
->type
!= nir_instr_type_intrinsic
)
151 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
153 gl_shader_stage stage
= b
->shader
->stage
;
155 if ((stage
== MESA_SHADER_TESS_CTRL
&& is_output(intrin
)) ||
156 (stage
== MESA_SHADER_TESS_EVAL
&& is_input(intrin
))) {
157 int vue_slot
= vue_map
->varying_to_slot
[intrin
->const_index
[0]];
158 assert(vue_slot
!= -1);
159 intrin
->const_index
[0] = vue_slot
;
161 nir_src
*vertex
= nir_get_io_vertex_index_src(intrin
);
163 nir_const_value
*const_vertex
= nir_src_as_const_value(*vertex
);
165 intrin
->const_index
[0] += const_vertex
->u32
[0] *
166 vue_map
->num_per_vertex_slots
;
168 b
->cursor
= nir_before_instr(&intrin
->instr
);
170 /* Multiply by the number of per-vertex slots. */
171 nir_ssa_def
*vertex_offset
=
173 nir_ssa_for_src(b
, *vertex
, 1),
175 vue_map
->num_per_vertex_slots
));
177 /* Add it to the existing offset */
178 nir_src
*offset
= nir_get_io_offset_src(intrin
);
179 nir_ssa_def
*total_offset
=
180 nir_iadd(b
, vertex_offset
,
181 nir_ssa_for_src(b
, *offset
, 1));
183 nir_instr_rewrite_src(&intrin
->instr
, offset
,
184 nir_src_for_ssa(total_offset
));
193 brw_nir_lower_vs_inputs(nir_shader
*nir
,
194 const struct gen_device_info
*devinfo
,
196 bool use_legacy_snorm_formula
,
197 const uint8_t *vs_attrib_wa_flags
)
199 /* Start with the location of the variable's base. */
200 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
201 var
->data
.driver_location
= var
->data
.location
;
204 /* Now use nir_lower_io to walk dereference chains. Attribute arrays are
205 * loaded as one vec4 or dvec4 per element (or matrix column), depending on
206 * whether it is a double-precision type or not.
208 nir_lower_io(nir
, nir_var_shader_in
, type_size_vs_input
, 0);
210 /* This pass needs actual constants */
211 nir_opt_constant_folding(nir
);
213 add_const_offset_to_base(nir
, nir_var_shader_in
);
215 brw_nir_apply_attribute_workarounds(nir
, use_legacy_snorm_formula
,
219 /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
221 nir_foreach_function(function
, nir
) {
222 if (function
->impl
) {
223 nir_foreach_block(block
, function
->impl
) {
224 remap_vs_attrs(block
, &nir
->info
);
232 brw_nir_lower_vue_inputs(nir_shader
*nir
, bool is_scalar
,
233 const struct brw_vue_map
*vue_map
)
235 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
236 var
->data
.driver_location
= var
->data
.location
;
239 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
240 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
242 if (is_scalar
|| nir
->stage
!= MESA_SHADER_GEOMETRY
) {
243 /* This pass needs actual constants */
244 nir_opt_constant_folding(nir
);
246 add_const_offset_to_base(nir
, nir_var_shader_in
);
248 nir_foreach_function(function
, nir
) {
249 if (function
->impl
) {
250 nir_foreach_block(block
, function
->impl
) {
251 remap_inputs_with_vue_map(block
, vue_map
);
259 brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
261 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
262 var
->data
.driver_location
= var
->data
.location
;
265 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
267 /* This pass needs actual constants */
268 nir_opt_constant_folding(nir
);
270 add_const_offset_to_base(nir
, nir_var_shader_in
);
272 nir_foreach_function(function
, nir
) {
273 if (function
->impl
) {
275 nir_builder_init(&b
, function
->impl
);
276 nir_foreach_block(block
, function
->impl
) {
277 remap_patch_urb_offsets(block
, &b
, vue_map
);
284 brw_nir_lower_fs_inputs(nir_shader
*nir
,
285 const struct gen_device_info
*devinfo
,
286 const struct brw_wm_prog_key
*key
)
288 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
289 var
->data
.driver_location
= var
->data
.location
;
291 /* Apply default interpolation mode.
293 * Everything defaults to smooth except for the legacy GL color
294 * built-in variables, which might be flat depending on API state.
296 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
297 const bool flat
= key
->flat_shade
&&
298 (var
->data
.location
== VARYING_SLOT_COL0
||
299 var
->data
.location
== VARYING_SLOT_COL1
);
301 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
302 : INTERP_MODE_SMOOTH
;
305 /* On Ironlake and below, there is only one interpolation mode.
306 * Centroid interpolation doesn't mean anything on this hardware --
307 * there is no multisampling.
309 if (devinfo
->gen
< 6) {
310 var
->data
.centroid
= false;
311 var
->data
.sample
= false;
315 nir_lower_io_options lower_io_options
= 0;
316 if (key
->persample_interp
)
317 lower_io_options
|= nir_lower_io_force_sample_interpolation
;
319 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, lower_io_options
);
321 /* This pass needs actual constants */
322 nir_opt_constant_folding(nir
);
324 add_const_offset_to_base(nir
, nir_var_shader_in
);
328 brw_nir_lower_vue_outputs(nir_shader
*nir
,
332 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
,
334 type_size_vec4_times_4
);
335 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4_times_4
, 0);
337 nir_foreach_variable(var
, &nir
->outputs
)
338 var
->data
.driver_location
= var
->data
.location
;
339 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
344 brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
346 nir_foreach_variable(var
, &nir
->outputs
) {
347 var
->data
.driver_location
= var
->data
.location
;
350 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
352 /* This pass needs actual constants */
353 nir_opt_constant_folding(nir
);
355 add_const_offset_to_base(nir
, nir_var_shader_out
);
357 nir_foreach_function(function
, nir
) {
358 if (function
->impl
) {
360 nir_builder_init(&b
, function
->impl
);
361 nir_foreach_block(block
, function
->impl
) {
362 remap_patch_urb_offsets(block
, &b
, vue_map
);
369 brw_nir_lower_fs_outputs(nir_shader
*nir
)
371 nir_foreach_variable(var
, &nir
->outputs
) {
372 var
->data
.driver_location
=
373 SET_FIELD(var
->data
.index
, BRW_NIR_FRAG_OUTPUT_INDEX
) |
374 SET_FIELD(var
->data
.location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
377 nir_lower_io(nir
, nir_var_shader_out
, type_size_dvec4
, 0);
381 brw_nir_lower_cs_shared(nir_shader
*nir
)
383 nir_assign_var_locations(&nir
->shared
, &nir
->num_shared
, 0,
384 type_size_scalar_bytes
);
385 nir_lower_io(nir
, nir_var_shared
, type_size_scalar_bytes
, 0);
388 #define OPT(pass, ...) ({ \
389 bool this_progress = false; \
390 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
396 #define OPT_V(pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
399 nir_optimize(nir_shader
*nir
, bool is_scalar
)
404 OPT_V(nir_lower_vars_to_ssa
);
407 OPT(nir_lower_alu_to_scalar
);
413 OPT(nir_lower_phis_to_scalar
);
419 OPT(nir_opt_peephole_select
);
420 OPT(nir_opt_algebraic
);
421 OPT(nir_opt_constant_folding
);
422 OPT(nir_opt_dead_cf
);
423 OPT(nir_opt_remove_phis
);
425 OPT_V(nir_lower_doubles
, nir_lower_drcp
|
432 nir_lower_dround_even
|
434 OPT_V(nir_lower_double_pack
);
440 /* Does some simple lowering and runs the standard suite of optimizations
442 * This is intended to be called more-or-less directly after you get the
443 * shader out of GLSL or some other source. While it is geared towards i965,
444 * it is not at all generator-specific except for the is_scalar flag. Even
445 * there, it is safe to call with is_scalar = false for a shader that is
446 * intended for the FS backend as long as nir_optimize is called again with
447 * is_scalar = true to scalarize everything prior to code gen.
450 brw_preprocess_nir(const struct brw_compiler
*compiler
, nir_shader
*nir
)
452 bool progress
; /* Written by OPT and OPT_V */
455 const bool is_scalar
= compiler
->scalar_stage
[nir
->stage
];
457 if (nir
->stage
== MESA_SHADER_GEOMETRY
)
458 OPT(nir_lower_gs_intrinsics
);
460 if (compiler
->precise_trig
)
461 OPT(brw_nir_apply_trig_workarounds
);
463 static const nir_lower_tex_options tex_options
= {
465 .lower_txf_offset
= true,
466 .lower_rect_offset
= true,
469 OPT(nir_lower_tex
, &tex_options
);
470 OPT(nir_normalize_cubemap_coords
);
472 OPT(nir_lower_global_vars_to_local
);
474 OPT(nir_split_var_copies
);
476 nir
= nir_optimize(nir
, is_scalar
);
479 OPT_V(nir_lower_load_const_to_scalar
);
482 /* Lower a bunch of stuff */
483 OPT_V(nir_lower_var_copies
);
485 /* Get rid of split copies */
486 nir
= nir_optimize(nir
, is_scalar
);
488 OPT(nir_remove_dead_variables
, nir_var_local
);
493 /* Prepare the given shader for codegen
495 * This function is intended to be called right before going into the actual
496 * backend and is highly backend-specific. Also, once this function has been
497 * called on a shader, it will no longer be in SSA form so most optimizations
501 brw_postprocess_nir(nir_shader
*nir
,
502 const struct gen_device_info
*devinfo
,
506 (INTEL_DEBUG
& intel_debug_flag_for_shader_stage(nir
->stage
));
508 bool progress
; /* Written by OPT and OPT_V */
511 nir
= nir_optimize(nir
, is_scalar
);
513 if (devinfo
->gen
>= 6) {
514 /* Try and fuse multiply-adds */
515 OPT(brw_nir_opt_peephole_ffma
);
518 OPT(nir_opt_algebraic_late
);
520 OPT(nir_lower_locals_to_regs
);
522 OPT_V(nir_lower_to_source_mods
);
526 if (unlikely(debug_enabled
)) {
527 /* Re-index SSA defs so we print more sensible numbers. */
528 nir_foreach_function(function
, nir
) {
530 nir_index_ssa_defs(function
->impl
);
533 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
534 _mesa_shader_stage_to_string(nir
->stage
));
535 nir_print_shader(nir
, stderr
);
538 OPT_V(nir_convert_from_ssa
, true);
541 OPT_V(nir_move_vec_src_uses_to_dest
);
542 OPT(nir_lower_vec_to_movs
);
545 /* This is the last pass we run before we start emitting stuff. It
546 * determines when we need to insert boolean resolves on Gen <= 5. We
547 * run it last because it stashes data in instr->pass_flags and we don't
548 * want that to be squashed by other NIR passes.
550 if (devinfo
->gen
<= 5)
551 brw_nir_analyze_boolean_resolves(nir
);
555 if (unlikely(debug_enabled
)) {
556 fprintf(stderr
, "NIR (final form) for %s shader:\n",
557 _mesa_shader_stage_to_string(nir
->stage
));
558 nir_print_shader(nir
, stderr
);
565 brw_nir_apply_sampler_key(nir_shader
*nir
,
566 const struct gen_device_info
*devinfo
,
567 const struct brw_sampler_prog_key_data
*key_tex
,
570 nir_lower_tex_options tex_options
= { 0 };
572 /* Iron Lake and prior require lowering of all rectangle textures */
573 if (devinfo
->gen
< 6)
574 tex_options
.lower_rect
= true;
576 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
577 if (devinfo
->gen
< 8) {
578 tex_options
.saturate_s
= key_tex
->gl_clamp_mask
[0];
579 tex_options
.saturate_t
= key_tex
->gl_clamp_mask
[1];
580 tex_options
.saturate_r
= key_tex
->gl_clamp_mask
[2];
583 /* Prior to Haswell, we have to fake texture swizzle */
584 for (unsigned s
= 0; s
< MAX_SAMPLERS
; s
++) {
585 if (key_tex
->swizzles
[s
] == SWIZZLE_NOOP
)
588 tex_options
.swizzle_result
|= (1 << s
);
589 for (unsigned c
= 0; c
< 4; c
++)
590 tex_options
.swizzles
[s
][c
] = GET_SWZ(key_tex
->swizzles
[s
], c
);
593 tex_options
.lower_y_uv_external
= key_tex
->y_uv_image_mask
;
594 tex_options
.lower_y_u_v_external
= key_tex
->y_u_v_image_mask
;
595 tex_options
.lower_yx_xuxv_external
= key_tex
->yx_xuxv_image_mask
;
597 if (nir_lower_tex(nir
, &tex_options
)) {
598 nir_validate_shader(nir
);
599 nir
= nir_optimize(nir
, is_scalar
);
606 brw_type_for_nir_type(nir_alu_type type
)
610 case nir_type_uint32
:
611 return BRW_REGISTER_TYPE_UD
;
614 case nir_type_bool32
:
616 return BRW_REGISTER_TYPE_D
;
618 case nir_type_float32
:
619 return BRW_REGISTER_TYPE_F
;
620 case nir_type_float64
:
621 return BRW_REGISTER_TYPE_DF
;
623 case nir_type_uint64
:
624 /* TODO we should only see these in moves, so for now it's ok, but when
625 * we add actual 64-bit integer support we should fix this.
627 return BRW_REGISTER_TYPE_DF
;
629 unreachable("unknown type");
632 return BRW_REGISTER_TYPE_F
;
635 /* Returns the glsl_base_type corresponding to a nir_alu_type.
636 * This is used by both brw_vec4_nir and brw_fs_nir.
639 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
643 case nir_type_float32
:
644 return GLSL_TYPE_FLOAT
;
646 case nir_type_float64
:
647 return GLSL_TYPE_DOUBLE
;
651 return GLSL_TYPE_INT
;
654 case nir_type_uint32
:
655 return GLSL_TYPE_UINT
;
658 unreachable("bad type");