i965/fs: Rework uniform handling
[mesa.git] / src / mesa / drivers / dri / i965 / brw_nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_nir.h"
25 #include "brw_shader.h"
26 #include "glsl/glsl_parser_extras.h"
27 #include "glsl/nir/glsl_to_nir.h"
28 #include "program/prog_to_nir.h"
29
30 static void
31 nir_optimize(nir_shader *nir, bool is_scalar)
32 {
33 bool progress;
34 do {
35 progress = false;
36 nir_lower_vars_to_ssa(nir);
37 nir_validate_shader(nir);
38
39 if (is_scalar) {
40 nir_lower_alu_to_scalar(nir);
41 nir_validate_shader(nir);
42 }
43
44 progress |= nir_copy_prop(nir);
45 nir_validate_shader(nir);
46
47 if (is_scalar) {
48 nir_lower_phis_to_scalar(nir);
49 nir_validate_shader(nir);
50 }
51
52 progress |= nir_copy_prop(nir);
53 nir_validate_shader(nir);
54 progress |= nir_opt_dce(nir);
55 nir_validate_shader(nir);
56 progress |= nir_opt_cse(nir);
57 nir_validate_shader(nir);
58 progress |= nir_opt_peephole_select(nir);
59 nir_validate_shader(nir);
60 progress |= nir_opt_algebraic(nir);
61 nir_validate_shader(nir);
62 progress |= nir_opt_constant_folding(nir);
63 nir_validate_shader(nir);
64 progress |= nir_opt_remove_phis(nir);
65 nir_validate_shader(nir);
66 } while (progress);
67 }
68
69 nir_shader *
70 brw_create_nir(struct brw_context *brw,
71 const struct gl_shader_program *shader_prog,
72 const struct gl_program *prog,
73 gl_shader_stage stage,
74 bool is_scalar)
75 {
76 struct gl_context *ctx = &brw->ctx;
77 const nir_shader_compiler_options *options =
78 ctx->Const.ShaderCompilerOptions[stage].NirOptions;
79 struct gl_shader *shader = shader_prog ? shader_prog->_LinkedShaders[stage] : NULL;
80 bool debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
81 nir_shader *nir;
82
83 /* First, lower the GLSL IR or Mesa IR to NIR */
84 if (shader_prog) {
85 nir = glsl_to_nir(shader, options);
86 } else {
87 nir = prog_to_nir(prog, options);
88 nir_convert_to_ssa(nir); /* turn registers into SSA */
89 }
90 nir_validate_shader(nir);
91
92 nir_lower_global_vars_to_local(nir);
93 nir_validate_shader(nir);
94
95 nir_lower_tex_projector(nir);
96 nir_validate_shader(nir);
97
98 nir_normalize_cubemap_coords(nir);
99 nir_validate_shader(nir);
100
101 nir_split_var_copies(nir);
102 nir_validate_shader(nir);
103
104 nir_optimize(nir, is_scalar);
105
106 /* Lower a bunch of stuff */
107 nir_lower_var_copies(nir);
108 nir_validate_shader(nir);
109
110 /* Get rid of split copies */
111 nir_optimize(nir, is_scalar);
112
113 if (is_scalar) {
114 nir_assign_var_locations(&nir->uniforms,
115 &nir->num_uniforms,
116 type_size_scalar);
117 nir_assign_var_locations(&nir->inputs, &nir->num_inputs, type_size_scalar);
118 nir_assign_var_locations(&nir->outputs, &nir->num_outputs, type_size_scalar);
119 nir_lower_io(nir, type_size_scalar);
120 } else {
121 nir_assign_var_locations(&nir->uniforms,
122 &nir->num_uniforms,
123 type_size_vec4);
124
125 nir_assign_var_locations(&nir->inputs, &nir->num_inputs, type_size_vec4);
126
127 foreach_list_typed(nir_variable, var, node, &nir->outputs)
128 var->data.driver_location = var->data.location;
129
130 nir_lower_io(nir, type_size_vec4);
131 }
132
133 nir_validate_shader(nir);
134
135 nir_remove_dead_variables(nir);
136 nir_validate_shader(nir);
137
138 if (shader_prog) {
139 nir_lower_samplers(nir, shader_prog, stage);
140 nir_validate_shader(nir);
141 }
142
143 nir_lower_system_values(nir);
144 nir_validate_shader(nir);
145
146 nir_lower_atomics(nir);
147 nir_validate_shader(nir);
148
149 nir_optimize(nir, is_scalar);
150
151 if (brw->gen >= 6) {
152 /* Try and fuse multiply-adds */
153 nir_opt_peephole_ffma(nir);
154 nir_validate_shader(nir);
155 }
156
157 nir_opt_algebraic_late(nir);
158 nir_validate_shader(nir);
159
160 nir_lower_locals_to_regs(nir);
161 nir_validate_shader(nir);
162
163 nir_lower_to_source_mods(nir);
164 nir_validate_shader(nir);
165 nir_copy_prop(nir);
166 nir_validate_shader(nir);
167 nir_opt_dce(nir);
168 nir_validate_shader(nir);
169
170 if (unlikely(debug_enabled)) {
171 /* Re-index SSA defs so we print more sensible numbers. */
172 nir_foreach_overload(nir, overload) {
173 if (overload->impl)
174 nir_index_ssa_defs(overload->impl);
175 }
176
177 fprintf(stderr, "NIR (SSA form) for %s shader:\n",
178 _mesa_shader_stage_to_string(stage));
179 nir_print_shader(nir, stderr);
180 }
181
182 nir_convert_from_ssa(nir, is_scalar);
183 nir_validate_shader(nir);
184
185 if (!is_scalar) {
186 nir_lower_vec_to_movs(nir);
187 nir_validate_shader(nir);
188 }
189
190 /* This is the last pass we run before we start emitting stuff. It
191 * determines when we need to insert boolean resolves on Gen <= 5. We
192 * run it last because it stashes data in instr->pass_flags and we don't
193 * want that to be squashed by other NIR passes.
194 */
195 if (brw->gen <= 5)
196 brw_nir_analyze_boolean_resolves(nir);
197
198 nir_sweep(nir);
199
200 if (unlikely(debug_enabled)) {
201 fprintf(stderr, "NIR (final form) for %s shader:\n",
202 _mesa_shader_stage_to_string(stage));
203 nir_print_shader(nir, stderr);
204 }
205
206 return nir;
207 }
208
209 enum brw_reg_type
210 brw_type_for_nir_type(nir_alu_type type)
211 {
212 switch (type) {
213 case nir_type_unsigned:
214 return BRW_REGISTER_TYPE_UD;
215 case nir_type_bool:
216 case nir_type_int:
217 return BRW_REGISTER_TYPE_D;
218 case nir_type_float:
219 return BRW_REGISTER_TYPE_F;
220 default:
221 unreachable("unknown type");
222 }
223
224 return BRW_REGISTER_TYPE_F;
225 }
226
227 /* Returns the glsl_base_type corresponding to a nir_alu_type.
228 * This is used by both brw_vec4_nir and brw_fs_nir.
229 */
230 enum glsl_base_type
231 brw_glsl_base_type_for_nir_type(nir_alu_type type)
232 {
233 switch (type) {
234 case nir_type_float:
235 return GLSL_TYPE_FLOAT;
236
237 case nir_type_int:
238 return GLSL_TYPE_INT;
239
240 case nir_type_unsigned:
241 return GLSL_TYPE_UINT;
242
243 default:
244 unreachable("bad type");
245 }
246 }