src/mesa/drivers/dri/i965/brw_nir.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_nir.h"
  25 #include "brw_shader.h"
  26 #include "compiler/nir/glsl_to_nir.h"
  27 #include "compiler/nir/nir_builder.h"
  28 #include "program/prog_to_nir.h"
  29
  30 static bool
  31 is_input(nir_intrinsic_instr *intrin)
  32 {
  33    return intrin->intrinsic == nir_intrinsic_load_input ||
  34           intrin->intrinsic == nir_intrinsic_load_per_vertex_input;
  35 }
  36
  37 static bool
  38 is_output(nir_intrinsic_instr *intrin)
  39 {
  40    return intrin->intrinsic == nir_intrinsic_load_output ||
  41           intrin->intrinsic == nir_intrinsic_load_per_vertex_output ||
  42           intrin->intrinsic == nir_intrinsic_store_output ||
  43           intrin->intrinsic == nir_intrinsic_store_per_vertex_output;
  44 }
  45
  46 /**
  47  * In many cases, we just add the base and offset together, so there's no
  48  * reason to keep them separate.  Sometimes, combining them is essential:
  49  * if a shader only accesses part of a compound variable (such as a matrix
  50  * or array), the variable's base may not actually exist in the VUE map.
  51  *
  52  * This pass adds constant offsets to instr->const_index[0], and resets
  53  * the offset source to 0.  Non-constant offsets remain unchanged - since
  54  * we don't know what part of a compound variable is accessed, we allocate
  55  * storage for the entire thing.
  56  */
  57
  58 static bool
  59 add_const_offset_to_base_block(nir_block *block, nir_builder *b,
  60                                nir_variable_mode mode)
  61 {
  62    nir_foreach_instr_safe(instr, block) {
  63       if (instr->type != nir_instr_type_intrinsic)
  64          continue;
  65
  66       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
  67
  68       if ((mode == nir_var_shader_in && is_input(intrin)) ||
  69           (mode == nir_var_shader_out && is_output(intrin))) {
  70          nir_src *offset = nir_get_io_offset_src(intrin);
  71          nir_const_value *const_offset = nir_src_as_const_value(*offset);
  72
  73          if (const_offset) {
  74             intrin->const_index[0] += const_offset->u32[0];
  75             b->cursor = nir_before_instr(&intrin->instr);
  76             nir_instr_rewrite_src(&intrin->instr, offset,
  77                                   nir_src_for_ssa(nir_imm_int(b, 0)));
  78          }
  79       }
  80    }
  81    return true;
  82 }
  83
  84 static void
  85 add_const_offset_to_base(nir_shader *nir, nir_variable_mode mode)
  86 {
  87    nir_foreach_function(f, nir) {
  88       if (f->impl) {
  89          nir_builder b;
  90          nir_builder_init(&b, f->impl);
  91          nir_foreach_block(block, f->impl) {
  92             add_const_offset_to_base_block(block, &b, mode);
  93          }
  94       }
  95    }
  96 }
  97
  98 static bool
  99 remap_vs_attrs(nir_block *block, GLbitfield64 inputs_read)
 100 {
 101    nir_foreach_instr(instr, block) {
 102       if (instr->type != nir_instr_type_intrinsic)
 103          continue;
 104
 105       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 106
 107       if (intrin->intrinsic == nir_intrinsic_load_input) {
 108          /* Attributes come in a contiguous block, ordered by their
 109           * gl_vert_attrib value.  That means we can compute the slot
 110           * number for an attribute by masking out the enabled attributes
 111           * before it and counting the bits.
 112           */
 113          int attr = intrin->const_index[0];
 114          int slot = _mesa_bitcount_64(inputs_read & BITFIELD64_MASK(attr));
 115
 116          intrin->const_index[0] = 4 * slot;
 117       }
 118    }
 119    return true;
 120 }
 121
 122 static bool
 123 remap_inputs_with_vue_map(nir_block *block, const struct brw_vue_map *vue_map)
 124 {
 125    nir_foreach_instr(instr, block) {
 126       if (instr->type != nir_instr_type_intrinsic)
 127          continue;
 128
 129       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 130
 131       if (intrin->intrinsic == nir_intrinsic_load_input ||
 132           intrin->intrinsic == nir_intrinsic_load_per_vertex_input) {
 133          int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
 134          assert(vue_slot != -1);
 135          intrin->const_index[0] = vue_slot;
 136       }
 137    }
 138    return true;
 139 }
 140
 141 static bool
 142 remap_patch_urb_offsets(nir_block *block, nir_builder *b,
 143                         const struct brw_vue_map *vue_map)
 144 {
 145    nir_foreach_instr_safe(instr, block) {
 146       if (instr->type != nir_instr_type_intrinsic)
 147          continue;
 148
 149       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 150
 151       gl_shader_stage stage = b->shader->stage;
 152
 153       if ((stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) ||
 154           (stage == MESA_SHADER_TESS_EVAL && is_input(intrin))) {
 155          int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
 156          assert(vue_slot != -1);
 157          intrin->const_index[0] = vue_slot;
 158
 159          nir_src *vertex = nir_get_io_vertex_index_src(intrin);
 160          if (vertex) {
 161             nir_const_value *const_vertex = nir_src_as_const_value(*vertex);
 162             if (const_vertex) {
 163                intrin->const_index[0] += const_vertex->u32[0] *
 164                                          vue_map->num_per_vertex_slots;
 165             } else {
 166                b->cursor = nir_before_instr(&intrin->instr);
 167
 168                /* Multiply by the number of per-vertex slots. */
 169                nir_ssa_def *vertex_offset =
 170                   nir_imul(b,
 171                            nir_ssa_for_src(b, *vertex, 1),
 172                            nir_imm_int(b,
 173                                        vue_map->num_per_vertex_slots));
 174
 175                /* Add it to the existing offset */
 176                nir_src *offset = nir_get_io_offset_src(intrin);
 177                nir_ssa_def *total_offset =
 178                   nir_iadd(b, vertex_offset,
 179                            nir_ssa_for_src(b, *offset, 1));
 180
 181                nir_instr_rewrite_src(&intrin->instr, offset,
 182                                      nir_src_for_ssa(total_offset));
 183             }
 184          }
 185       }
 186    }
 187    return true;
 188 }
 189
 190 void
 191 brw_nir_lower_vs_inputs(nir_shader *nir,
 192                         const struct brw_device_info *devinfo,
 193                         bool is_scalar,
 194                         bool use_legacy_snorm_formula,
 195                         const uint8_t *vs_attrib_wa_flags)
 196 {
 197    /* Start with the location of the variable's base. */
 198    foreach_list_typed(nir_variable, var, node, &nir->inputs) {
 199       var->data.driver_location = var->data.location;
 200    }
 201
 202    /* Now use nir_lower_io to walk dereference chains.  Attribute arrays
 203     * are loaded as one vec4 per element (or matrix column), so we use
 204     * type_size_vec4 here.
 205     */
 206    nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
 207
 208    /* This pass needs actual constants */
 209    nir_opt_constant_folding(nir);
 210
 211    add_const_offset_to_base(nir, nir_var_shader_in);
 212
 213    brw_nir_apply_attribute_workarounds(nir, use_legacy_snorm_formula,
 214                                        vs_attrib_wa_flags);
 215
 216    if (is_scalar) {
 217       /* Finally, translate VERT_ATTRIB_* values into the actual registers.
 218        *
 219        * Note that we can use nir->info.inputs_read instead of
 220        * key->inputs_read since the two are identical aside from Gen4-5
 221        * edge flag differences.
 222        */
 223       GLbitfield64 inputs_read = nir->info.inputs_read;
 224
 225       nir_foreach_function(function, nir) {
 226          if (function->impl) {
 227             nir_foreach_block(block, function->impl) {
 228                remap_vs_attrs(block, inputs_read);
 229             }
 230          }
 231       }
 232    }
 233 }
 234
 235 void
 236 brw_nir_lower_vue_inputs(nir_shader *nir, bool is_scalar,
 237                          const struct brw_vue_map *vue_map)
 238 {
 239    foreach_list_typed(nir_variable, var, node, &nir->inputs) {
 240       var->data.driver_location = var->data.location;
 241    }
 242
 243    /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
 244    nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
 245
 246    if (is_scalar || nir->stage != MESA_SHADER_GEOMETRY) {
 247       /* This pass needs actual constants */
 248       nir_opt_constant_folding(nir);
 249
 250       add_const_offset_to_base(nir, nir_var_shader_in);
 251
 252       nir_foreach_function(function, nir) {
 253          if (function->impl) {
 254             nir_foreach_block(block, function->impl) {
 255                remap_inputs_with_vue_map(block, vue_map);
 256             }
 257          }
 258       }
 259    }
 260 }
 261
 262 void
 263 brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue_map)
 264 {
 265    foreach_list_typed(nir_variable, var, node, &nir->inputs) {
 266       var->data.driver_location = var->data.location;
 267    }
 268
 269    nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
 270
 271    /* This pass needs actual constants */
 272    nir_opt_constant_folding(nir);
 273
 274    add_const_offset_to_base(nir, nir_var_shader_in);
 275
 276    nir_foreach_function(function, nir) {
 277       if (function->impl) {
 278          nir_builder b;
 279          nir_builder_init(&b, function->impl);
 280          nir_foreach_block(block, function->impl) {
 281             remap_patch_urb_offsets(block, &b, vue_map);
 282          }
 283       }
 284    }
 285 }
 286
 287 void
 288 brw_nir_lower_fs_inputs(nir_shader *nir)
 289 {
 290    nir_assign_var_locations(&nir->inputs, &nir->num_inputs, type_size_scalar);
 291    nir_lower_io(nir, nir_var_shader_in, type_size_scalar);
 292 }
 293
 294 void
 295 brw_nir_lower_vue_outputs(nir_shader *nir,
 296                           bool is_scalar)
 297 {
 298    if (is_scalar) {
 299       nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
 300                                type_size_vec4_times_4);
 301       nir_lower_io(nir, nir_var_shader_out, type_size_vec4_times_4);
 302    } else {
 303       nir_foreach_variable(var, &nir->outputs)
 304          var->data.driver_location = var->data.location;
 305       nir_lower_io(nir, nir_var_shader_out, type_size_vec4);
 306    }
 307 }
 308
 309 void
 310 brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue_map)
 311 {
 312    nir_foreach_variable(var, &nir->outputs) {
 313       var->data.driver_location = var->data.location;
 314    }
 315
 316    nir_lower_io(nir, nir_var_shader_out, type_size_vec4);
 317
 318    /* This pass needs actual constants */
 319    nir_opt_constant_folding(nir);
 320
 321    add_const_offset_to_base(nir, nir_var_shader_out);
 322
 323    nir_foreach_function(function, nir) {
 324       if (function->impl) {
 325          nir_builder b;
 326          nir_builder_init(&b, function->impl);
 327          nir_foreach_block(block, function->impl) {
 328             remap_patch_urb_offsets(block, &b, vue_map);
 329          }
 330       }
 331    }
 332 }
 333
 334 void
 335 brw_nir_lower_fs_outputs(nir_shader *nir)
 336 {
 337    nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
 338                             type_size_scalar);
 339    nir_lower_io(nir, nir_var_shader_out, type_size_scalar);
 340 }
 341
 342 static int
 343 type_size_scalar_bytes(const struct glsl_type *type)
 344 {
 345    return type_size_scalar(type) * 4;
 346 }
 347
 348 static int
 349 type_size_vec4_bytes(const struct glsl_type *type)
 350 {
 351    return type_size_vec4(type) * 16;
 352 }
 353
 354 static void
 355 brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
 356 {
 357    if (is_scalar) {
 358       nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
 359                                type_size_scalar_bytes);
 360       nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes);
 361    } else {
 362       nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
 363                                type_size_vec4_bytes);
 364       nir_lower_io(nir, nir_var_uniform, type_size_vec4_bytes);
 365    }
 366 }
 367
 368 void
 369 brw_nir_lower_cs_shared(nir_shader *nir)
 370 {
 371    nir_assign_var_locations(&nir->shared, &nir->num_shared,
 372                             type_size_scalar_bytes);
 373    nir_lower_io(nir, nir_var_shared, type_size_scalar_bytes);
 374 }
 375
 376 #define OPT(pass, ...) ({                                  \
 377    bool this_progress = false;                             \
 378    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 379    if (this_progress)                                      \
 380       progress = true;                                     \
 381    this_progress;                                          \
 382 })
 383
 384 #define OPT_V(pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 385
 386 static nir_shader *
 387 nir_optimize(nir_shader *nir, bool is_scalar)
 388 {
 389    bool progress;
 390    do {
 391       progress = false;
 392       OPT_V(nir_lower_vars_to_ssa);
 393
 394       if (is_scalar) {
 395          OPT_V(nir_lower_alu_to_scalar);
 396       }
 397
 398       OPT(nir_copy_prop);
 399
 400       if (is_scalar) {
 401          OPT_V(nir_lower_phis_to_scalar);
 402       }
 403
 404       OPT(nir_copy_prop);
 405       OPT(nir_opt_dce);
 406       OPT(nir_opt_cse);
 407       OPT(nir_opt_peephole_select);
 408       OPT(nir_opt_algebraic);
 409       OPT(nir_opt_constant_folding);
 410       OPT(nir_opt_dead_cf);
 411       OPT(nir_opt_remove_phis);
 412       OPT(nir_opt_undef);
 413       OPT_V(nir_lower_doubles, nir_lower_drcp |
 414                                nir_lower_dsqrt |
 415                                nir_lower_drsq |
 416                                nir_lower_dtrunc |
 417                                nir_lower_dfloor |
 418                                nir_lower_dceil |
 419                                nir_lower_dfract |
 420                                nir_lower_dround_even |
 421                                nir_lower_dmod);
 422       OPT_V(nir_lower_double_pack);
 423    } while (progress);
 424
 425    return nir;
 426 }
 427
 428 /* Does some simple lowering and runs the standard suite of optimizations
 429  *
 430  * This is intended to be called more-or-less directly after you get the
 431  * shader out of GLSL or some other source.  While it is geared towards i965,
 432  * it is not at all generator-specific except for the is_scalar flag.  Even
 433  * there, it is safe to call with is_scalar = false for a shader that is
 434  * intended for the FS backend as long as nir_optimize is called again with
 435  * is_scalar = true to scalarize everything prior to code gen.
 436  */
 437 nir_shader *
 438 brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
 439 {
 440    bool progress; /* Written by OPT and OPT_V */
 441    (void)progress;
 442
 443    const bool is_scalar = compiler->scalar_stage[nir->stage];
 444
 445    if (nir->stage == MESA_SHADER_GEOMETRY)
 446       OPT(nir_lower_gs_intrinsics);
 447
 448    if (compiler->precise_trig)
 449       OPT(brw_nir_apply_trig_workarounds);
 450
 451    static const nir_lower_tex_options tex_options = {
 452       .lower_txp = ~0,
 453    };
 454
 455    OPT(nir_lower_tex, &tex_options);
 456    OPT(nir_normalize_cubemap_coords);
 457
 458    OPT(nir_lower_global_vars_to_local);
 459
 460    OPT(nir_split_var_copies);
 461
 462    nir = nir_optimize(nir, is_scalar);
 463
 464    if (is_scalar) {
 465       OPT_V(nir_lower_load_const_to_scalar);
 466    }
 467
 468    /* Lower a bunch of stuff */
 469    OPT_V(nir_lower_var_copies);
 470
 471    /* Get rid of split copies */
 472    nir = nir_optimize(nir, is_scalar);
 473
 474    OPT(nir_remove_dead_variables, nir_var_local);
 475
 476    return nir;
 477 }
 478
 479 /* Prepare the given shader for codegen
 480  *
 481  * This function is intended to be called right before going into the actual
 482  * backend and is highly backend-specific.  Also, once this function has been
 483  * called on a shader, it will no longer be in SSA form so most optimizations
 484  * will not work.
 485  */
 486 nir_shader *
 487 brw_postprocess_nir(nir_shader *nir,
 488                     const struct brw_device_info *devinfo,
 489                     bool is_scalar)
 490 {
 491    bool debug_enabled =
 492       (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->stage));
 493
 494    bool progress; /* Written by OPT and OPT_V */
 495    (void)progress;
 496
 497    nir = nir_optimize(nir, is_scalar);
 498
 499    if (devinfo->gen >= 6) {
 500       /* Try and fuse multiply-adds */
 501       OPT(brw_nir_opt_peephole_ffma);
 502    }
 503
 504    OPT(nir_opt_algebraic_late);
 505
 506    OPT(nir_lower_locals_to_regs);
 507
 508    OPT_V(nir_lower_to_source_mods);
 509    OPT(nir_copy_prop);
 510    OPT(nir_opt_dce);
 511
 512    if (unlikely(debug_enabled)) {
 513       /* Re-index SSA defs so we print more sensible numbers. */
 514       nir_foreach_function(function, nir) {
 515          if (function->impl)
 516             nir_index_ssa_defs(function->impl);
 517       }
 518
 519       fprintf(stderr, "NIR (SSA form) for %s shader:\n",
 520               _mesa_shader_stage_to_string(nir->stage));
 521       nir_print_shader(nir, stderr);
 522    }
 523
 524    OPT_V(nir_convert_from_ssa, true);
 525
 526    if (!is_scalar) {
 527       OPT_V(nir_move_vec_src_uses_to_dest);
 528       OPT(nir_lower_vec_to_movs);
 529    }
 530
 531    /* This is the last pass we run before we start emitting stuff.  It
 532     * determines when we need to insert boolean resolves on Gen <= 5.  We
 533     * run it last because it stashes data in instr->pass_flags and we don't
 534     * want that to be squashed by other NIR passes.
 535     */
 536    if (devinfo->gen <= 5)
 537       brw_nir_analyze_boolean_resolves(nir);
 538
 539    nir_sweep(nir);
 540
 541    if (unlikely(debug_enabled)) {
 542       fprintf(stderr, "NIR (final form) for %s shader:\n",
 543               _mesa_shader_stage_to_string(nir->stage));
 544       nir_print_shader(nir, stderr);
 545    }
 546
 547    return nir;
 548 }
 549
 550 nir_shader *
 551 brw_create_nir(struct brw_context *brw,
 552                const struct gl_shader_program *shader_prog,
 553                const struct gl_program *prog,
 554                gl_shader_stage stage,
 555                bool is_scalar)
 556 {
 557    struct gl_context *ctx = &brw->ctx;
 558    const nir_shader_compiler_options *options =
 559       ctx->Const.ShaderCompilerOptions[stage].NirOptions;
 560    bool progress;
 561    nir_shader *nir;
 562
 563    /* First, lower the GLSL IR or Mesa IR to NIR */
 564    if (shader_prog) {
 565       nir = glsl_to_nir(shader_prog, stage, options);
 566    } else {
 567       nir = prog_to_nir(prog, options);
 568       OPT_V(nir_convert_to_ssa); /* turn registers into SSA */
 569    }
 570    nir_validate_shader(nir);
 571
 572    (void)progress;
 573
 574    nir = brw_preprocess_nir(brw->intelScreen->compiler, nir);
 575
 576    OPT(nir_lower_system_values);
 577    OPT_V(brw_nir_lower_uniforms, is_scalar);
 578
 579    if (shader_prog) {
 580       OPT_V(nir_lower_samplers, shader_prog);
 581       OPT_V(nir_lower_atomics, shader_prog);
 582    }
 583
 584    return nir;
 585 }
 586
 587 nir_shader *
 588 brw_nir_apply_sampler_key(nir_shader *nir,
 589                           const struct brw_device_info *devinfo,
 590                           const struct brw_sampler_prog_key_data *key_tex,
 591                           bool is_scalar)
 592 {
 593    nir_lower_tex_options tex_options = { 0 };
 594
 595    /* Iron Lake and prior require lowering of all rectangle textures */
 596    if (devinfo->gen < 6)
 597       tex_options.lower_rect = true;
 598
 599    /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
 600    if (devinfo->gen < 8) {
 601       tex_options.saturate_s = key_tex->gl_clamp_mask[0];
 602       tex_options.saturate_t = key_tex->gl_clamp_mask[1];
 603       tex_options.saturate_r = key_tex->gl_clamp_mask[2];
 604    }
 605
 606    /* Prior to Haswell, we have to fake texture swizzle */
 607    for (unsigned s = 0; s < MAX_SAMPLERS; s++) {
 608       if (key_tex->swizzles[s] == SWIZZLE_NOOP)
 609          continue;
 610
 611       tex_options.swizzle_result |= (1 << s);
 612       for (unsigned c = 0; c < 4; c++)
 613          tex_options.swizzles[s][c] = GET_SWZ(key_tex->swizzles[s], c);
 614    }
 615
 616    if (nir_lower_tex(nir, &tex_options)) {
 617       nir_validate_shader(nir);
 618       nir = nir_optimize(nir, is_scalar);
 619    }
 620
 621    return nir;
 622 }
 623
 624 enum brw_reg_type
 625 brw_type_for_nir_type(nir_alu_type type)
 626 {
 627    switch (type) {
 628    case nir_type_uint:
 629    case nir_type_uint32:
 630       return BRW_REGISTER_TYPE_UD;
 631    case nir_type_bool:
 632    case nir_type_int:
 633    case nir_type_bool32:
 634    case nir_type_int32:
 635       return BRW_REGISTER_TYPE_D;
 636    case nir_type_float:
 637    case nir_type_float32:
 638       return BRW_REGISTER_TYPE_F;
 639    case nir_type_float64:
 640       return BRW_REGISTER_TYPE_DF;
 641    case nir_type_int64:
 642    case nir_type_uint64:
 643       /* TODO we should only see these in moves, so for now it's ok, but when
 644        * we add actual 64-bit integer support we should fix this.
 645        */
 646       return BRW_REGISTER_TYPE_DF;
 647    default:
 648       unreachable("unknown type");
 649    }
 650
 651    return BRW_REGISTER_TYPE_F;
 652 }
 653
 654 /* Returns the glsl_base_type corresponding to a nir_alu_type.
 655  * This is used by both brw_vec4_nir and brw_fs_nir.
 656  */
 657 enum glsl_base_type
 658 brw_glsl_base_type_for_nir_type(nir_alu_type type)
 659 {
 660    switch (type) {
 661    case nir_type_float:
 662    case nir_type_float32:
 663       return GLSL_TYPE_FLOAT;
 664
 665    case nir_type_float64:
 666       return GLSL_TYPE_DOUBLE;
 667
 668    case nir_type_int:
 669    case nir_type_int32:
 670       return GLSL_TYPE_INT;
 671
 672    case nir_type_uint:
 673    case nir_type_uint32:
 674       return GLSL_TYPE_UINT;
 675
 676    default:
 677       unreachable("bad type");
 678    }
 679 }