src/mesa/drivers/dri/i965/brw_nir.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_nir.h"
  25 #include "brw_shader.h"
  26 #include "compiler/glsl_types.h"
  27 #include "compiler/nir/nir_builder.h"
  28
  29 static bool
  30 is_input(nir_intrinsic_instr *intrin)
  31 {
  32    return intrin->intrinsic == nir_intrinsic_load_input ||
  33           intrin->intrinsic == nir_intrinsic_load_per_vertex_input;
  34 }
  35
  36 static bool
  37 is_output(nir_intrinsic_instr *intrin)
  38 {
  39    return intrin->intrinsic == nir_intrinsic_load_output ||
  40           intrin->intrinsic == nir_intrinsic_load_per_vertex_output ||
  41           intrin->intrinsic == nir_intrinsic_store_output ||
  42           intrin->intrinsic == nir_intrinsic_store_per_vertex_output;
  43 }
  44
  45 /**
  46  * In many cases, we just add the base and offset together, so there's no
  47  * reason to keep them separate.  Sometimes, combining them is essential:
  48  * if a shader only accesses part of a compound variable (such as a matrix
  49  * or array), the variable's base may not actually exist in the VUE map.
  50  *
  51  * This pass adds constant offsets to instr->const_index[0], and resets
  52  * the offset source to 0.  Non-constant offsets remain unchanged - since
  53  * we don't know what part of a compound variable is accessed, we allocate
  54  * storage for the entire thing.
  55  */
  56
  57 static bool
  58 add_const_offset_to_base_block(nir_block *block, nir_builder *b,
  59                                nir_variable_mode mode)
  60 {
  61    nir_foreach_instr_safe(instr, block) {
  62       if (instr->type != nir_instr_type_intrinsic)
  63          continue;
  64
  65       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
  66
  67       if ((mode == nir_var_shader_in && is_input(intrin)) ||
  68           (mode == nir_var_shader_out && is_output(intrin))) {
  69          nir_src *offset = nir_get_io_offset_src(intrin);
  70          nir_const_value *const_offset = nir_src_as_const_value(*offset);
  71
  72          if (const_offset) {
  73             intrin->const_index[0] += const_offset->u32[0];
  74             b->cursor = nir_before_instr(&intrin->instr);
  75             nir_instr_rewrite_src(&intrin->instr, offset,
  76                                   nir_src_for_ssa(nir_imm_int(b, 0)));
  77          }
  78       }
  79    }
  80    return true;
  81 }
  82
  83 static void
  84 add_const_offset_to_base(nir_shader *nir, nir_variable_mode mode)
  85 {
  86    nir_foreach_function(f, nir) {
  87       if (f->impl) {
  88          nir_builder b;
  89          nir_builder_init(&b, f->impl);
  90          nir_foreach_block(block, f->impl) {
  91             add_const_offset_to_base_block(block, &b, mode);
  92          }
  93       }
  94    }
  95 }
  96
  97 static bool
  98 remap_vs_attrs(nir_block *block, struct nir_shader_info *nir_info)
  99 {
 100    nir_foreach_instr(instr, block) {
 101       if (instr->type != nir_instr_type_intrinsic)
 102          continue;
 103
 104       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 105
 106       if (intrin->intrinsic == nir_intrinsic_load_input) {
 107          /* Attributes come in a contiguous block, ordered by their
 108           * gl_vert_attrib value.  That means we can compute the slot
 109           * number for an attribute by masking out the enabled attributes
 110           * before it and counting the bits.
 111           */
 112          int attr = intrin->const_index[0];
 113          int slot = _mesa_bitcount_64(nir_info->inputs_read &
 114                                       BITFIELD64_MASK(attr));
 115          int dslot = _mesa_bitcount_64(nir_info->double_inputs_read &
 116                                        BITFIELD64_MASK(attr));
 117          intrin->const_index[0] = 4 * (slot + dslot);
 118       }
 119    }
 120    return true;
 121 }
 122
 123 static bool
 124 remap_inputs_with_vue_map(nir_block *block, const struct brw_vue_map *vue_map)
 125 {
 126    nir_foreach_instr(instr, block) {
 127       if (instr->type != nir_instr_type_intrinsic)
 128          continue;
 129
 130       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 131
 132       if (intrin->intrinsic == nir_intrinsic_load_input ||
 133           intrin->intrinsic == nir_intrinsic_load_per_vertex_input) {
 134          int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
 135          assert(vue_slot != -1);
 136          intrin->const_index[0] = vue_slot;
 137       }
 138    }
 139    return true;
 140 }
 141
 142 static bool
 143 remap_patch_urb_offsets(nir_block *block, nir_builder *b,
 144                         const struct brw_vue_map *vue_map)
 145 {
 146    nir_foreach_instr_safe(instr, block) {
 147       if (instr->type != nir_instr_type_intrinsic)
 148          continue;
 149
 150       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 151
 152       gl_shader_stage stage = b->shader->stage;
 153
 154       if ((stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) ||
 155           (stage == MESA_SHADER_TESS_EVAL && is_input(intrin))) {
 156          int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
 157          assert(vue_slot != -1);
 158          intrin->const_index[0] = vue_slot;
 159
 160          nir_src *vertex = nir_get_io_vertex_index_src(intrin);
 161          if (vertex) {
 162             nir_const_value *const_vertex = nir_src_as_const_value(*vertex);
 163             if (const_vertex) {
 164                intrin->const_index[0] += const_vertex->u32[0] *
 165                                          vue_map->num_per_vertex_slots;
 166             } else {
 167                b->cursor = nir_before_instr(&intrin->instr);
 168
 169                /* Multiply by the number of per-vertex slots. */
 170                nir_ssa_def *vertex_offset =
 171                   nir_imul(b,
 172                            nir_ssa_for_src(b, *vertex, 1),
 173                            nir_imm_int(b,
 174                                        vue_map->num_per_vertex_slots));
 175
 176                /* Add it to the existing offset */
 177                nir_src *offset = nir_get_io_offset_src(intrin);
 178                nir_ssa_def *total_offset =
 179                   nir_iadd(b, vertex_offset,
 180                            nir_ssa_for_src(b, *offset, 1));
 181
 182                nir_instr_rewrite_src(&intrin->instr, offset,
 183                                      nir_src_for_ssa(total_offset));
 184             }
 185          }
 186       }
 187    }
 188    return true;
 189 }
 190
 191 void
 192 brw_nir_lower_vs_inputs(nir_shader *nir,
 193                         const struct brw_device_info *devinfo,
 194                         bool is_scalar,
 195                         bool use_legacy_snorm_formula,
 196                         const uint8_t *vs_attrib_wa_flags)
 197 {
 198    /* Start with the location of the variable's base. */
 199    foreach_list_typed(nir_variable, var, node, &nir->inputs) {
 200       var->data.driver_location = var->data.location;
 201    }
 202
 203    /* Now use nir_lower_io to walk dereference chains.  Attribute arrays are
 204     * loaded as one vec4 or dvec4 per element (or matrix column), depending on
 205     * whether it is a double-precision type or not.
 206     */
 207    nir_lower_io(nir, nir_var_shader_in, type_size_vs_input);
 208
 209    /* This pass needs actual constants */
 210    nir_opt_constant_folding(nir);
 211
 212    add_const_offset_to_base(nir, nir_var_shader_in);
 213
 214    brw_nir_apply_attribute_workarounds(nir, use_legacy_snorm_formula,
 215                                        vs_attrib_wa_flags);
 216
 217    if (is_scalar) {
 218       /* Finally, translate VERT_ATTRIB_* values into the actual registers. */
 219
 220       nir_foreach_function(function, nir) {
 221          if (function->impl) {
 222             nir_foreach_block(block, function->impl) {
 223                remap_vs_attrs(block, &nir->info);
 224             }
 225          }
 226       }
 227    }
 228 }
 229
 230 void
 231 brw_nir_lower_vue_inputs(nir_shader *nir, bool is_scalar,
 232                          const struct brw_vue_map *vue_map)
 233 {
 234    foreach_list_typed(nir_variable, var, node, &nir->inputs) {
 235       var->data.driver_location = var->data.location;
 236    }
 237
 238    /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
 239    nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
 240
 241    if (is_scalar || nir->stage != MESA_SHADER_GEOMETRY) {
 242       /* This pass needs actual constants */
 243       nir_opt_constant_folding(nir);
 244
 245       add_const_offset_to_base(nir, nir_var_shader_in);
 246
 247       nir_foreach_function(function, nir) {
 248          if (function->impl) {
 249             nir_foreach_block(block, function->impl) {
 250                remap_inputs_with_vue_map(block, vue_map);
 251             }
 252          }
 253       }
 254    }
 255 }
 256
 257 void
 258 brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue_map)
 259 {
 260    foreach_list_typed(nir_variable, var, node, &nir->inputs) {
 261       var->data.driver_location = var->data.location;
 262    }
 263
 264    nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
 265
 266    /* This pass needs actual constants */
 267    nir_opt_constant_folding(nir);
 268
 269    add_const_offset_to_base(nir, nir_var_shader_in);
 270
 271    nir_foreach_function(function, nir) {
 272       if (function->impl) {
 273          nir_builder b;
 274          nir_builder_init(&b, function->impl);
 275          nir_foreach_block(block, function->impl) {
 276             remap_patch_urb_offsets(block, &b, vue_map);
 277          }
 278       }
 279    }
 280 }
 281
 282 void
 283 brw_nir_lower_fs_inputs(nir_shader *nir)
 284 {
 285    nir_assign_var_locations(&nir->inputs, &nir->num_inputs, type_size_scalar);
 286    nir_lower_io(nir, nir_var_shader_in, type_size_scalar);
 287 }
 288
 289 void
 290 brw_nir_lower_vue_outputs(nir_shader *nir,
 291                           bool is_scalar)
 292 {
 293    if (is_scalar) {
 294       nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
 295                                type_size_vec4_times_4);
 296       nir_lower_io(nir, nir_var_shader_out, type_size_vec4_times_4);
 297    } else {
 298       nir_foreach_variable(var, &nir->outputs)
 299          var->data.driver_location = var->data.location;
 300       nir_lower_io(nir, nir_var_shader_out, type_size_vec4);
 301    }
 302 }
 303
 304 void
 305 brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue_map)
 306 {
 307    nir_foreach_variable(var, &nir->outputs) {
 308       var->data.driver_location = var->data.location;
 309    }
 310
 311    nir_lower_io(nir, nir_var_shader_out, type_size_vec4);
 312
 313    /* This pass needs actual constants */
 314    nir_opt_constant_folding(nir);
 315
 316    add_const_offset_to_base(nir, nir_var_shader_out);
 317
 318    nir_foreach_function(function, nir) {
 319       if (function->impl) {
 320          nir_builder b;
 321          nir_builder_init(&b, function->impl);
 322          nir_foreach_block(block, function->impl) {
 323             remap_patch_urb_offsets(block, &b, vue_map);
 324          }
 325       }
 326    }
 327 }
 328
 329 void
 330 brw_nir_lower_fs_outputs(nir_shader *nir)
 331 {
 332    nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
 333                             type_size_scalar);
 334    nir_lower_io(nir, nir_var_shader_out, type_size_scalar);
 335 }
 336
 337 void
 338 brw_nir_lower_cs_shared(nir_shader *nir)
 339 {
 340    nir_assign_var_locations(&nir->shared, &nir->num_shared,
 341                             type_size_scalar_bytes);
 342    nir_lower_io(nir, nir_var_shared, type_size_scalar_bytes);
 343 }
 344
 345 #define OPT(pass, ...) ({                                  \
 346    bool this_progress = false;                             \
 347    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 348    if (this_progress)                                      \
 349       progress = true;                                     \
 350    this_progress;                                          \
 351 })
 352
 353 #define OPT_V(pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 354
 355 static nir_shader *
 356 nir_optimize(nir_shader *nir, bool is_scalar)
 357 {
 358    bool progress;
 359    do {
 360       progress = false;
 361       OPT_V(nir_lower_vars_to_ssa);
 362
 363       if (is_scalar) {
 364          OPT_V(nir_lower_alu_to_scalar);
 365       }
 366
 367       OPT(nir_copy_prop);
 368
 369       if (is_scalar) {
 370          OPT_V(nir_lower_phis_to_scalar);
 371       }
 372
 373       OPT(nir_copy_prop);
 374       OPT(nir_opt_dce);
 375       OPT(nir_opt_cse);
 376       OPT(nir_opt_peephole_select);
 377       OPT(nir_opt_algebraic);
 378       OPT(nir_opt_constant_folding);
 379       OPT(nir_opt_dead_cf);
 380       OPT(nir_opt_remove_phis);
 381       OPT(nir_opt_undef);
 382       OPT_V(nir_lower_doubles, nir_lower_drcp |
 383                                nir_lower_dsqrt |
 384                                nir_lower_drsq |
 385                                nir_lower_dtrunc |
 386                                nir_lower_dfloor |
 387                                nir_lower_dceil |
 388                                nir_lower_dfract |
 389                                nir_lower_dround_even |
 390                                nir_lower_dmod);
 391       OPT_V(nir_lower_double_pack);
 392    } while (progress);
 393
 394    return nir;
 395 }
 396
 397 /* Does some simple lowering and runs the standard suite of optimizations
 398  *
 399  * This is intended to be called more-or-less directly after you get the
 400  * shader out of GLSL or some other source.  While it is geared towards i965,
 401  * it is not at all generator-specific except for the is_scalar flag.  Even
 402  * there, it is safe to call with is_scalar = false for a shader that is
 403  * intended for the FS backend as long as nir_optimize is called again with
 404  * is_scalar = true to scalarize everything prior to code gen.
 405  */
 406 nir_shader *
 407 brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
 408 {
 409    bool progress; /* Written by OPT and OPT_V */
 410    (void)progress;
 411
 412    const bool is_scalar = compiler->scalar_stage[nir->stage];
 413
 414    if (nir->stage == MESA_SHADER_GEOMETRY)
 415       OPT(nir_lower_gs_intrinsics);
 416
 417    if (compiler->precise_trig)
 418       OPT(brw_nir_apply_trig_workarounds);
 419
 420    static const nir_lower_tex_options tex_options = {
 421       .lower_txp = ~0,
 422    };
 423
 424    OPT(nir_lower_tex, &tex_options);
 425    OPT(nir_normalize_cubemap_coords);
 426
 427    OPT(nir_lower_global_vars_to_local);
 428
 429    OPT(nir_split_var_copies);
 430
 431    nir = nir_optimize(nir, is_scalar);
 432
 433    if (is_scalar) {
 434       OPT_V(nir_lower_load_const_to_scalar);
 435    }
 436
 437    /* Lower a bunch of stuff */
 438    OPT_V(nir_lower_var_copies);
 439
 440    /* Get rid of split copies */
 441    nir = nir_optimize(nir, is_scalar);
 442
 443    OPT(nir_remove_dead_variables, nir_var_local);
 444
 445    return nir;
 446 }
 447
 448 /* Prepare the given shader for codegen
 449  *
 450  * This function is intended to be called right before going into the actual
 451  * backend and is highly backend-specific.  Also, once this function has been
 452  * called on a shader, it will no longer be in SSA form so most optimizations
 453  * will not work.
 454  */
 455 nir_shader *
 456 brw_postprocess_nir(nir_shader *nir,
 457                     const struct brw_device_info *devinfo,
 458                     bool is_scalar)
 459 {
 460    bool debug_enabled =
 461       (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->stage));
 462
 463    bool progress; /* Written by OPT and OPT_V */
 464    (void)progress;
 465
 466    nir = nir_optimize(nir, is_scalar);
 467
 468    if (devinfo->gen >= 6) {
 469       /* Try and fuse multiply-adds */
 470       OPT(brw_nir_opt_peephole_ffma);
 471    }
 472
 473    OPT(nir_opt_algebraic_late);
 474
 475    OPT(nir_lower_locals_to_regs);
 476
 477    OPT_V(nir_lower_to_source_mods);
 478    OPT(nir_copy_prop);
 479    OPT(nir_opt_dce);
 480
 481    if (unlikely(debug_enabled)) {
 482       /* Re-index SSA defs so we print more sensible numbers. */
 483       nir_foreach_function(function, nir) {
 484          if (function->impl)
 485             nir_index_ssa_defs(function->impl);
 486       }
 487
 488       fprintf(stderr, "NIR (SSA form) for %s shader:\n",
 489               _mesa_shader_stage_to_string(nir->stage));
 490       nir_print_shader(nir, stderr);
 491    }
 492
 493    OPT_V(nir_convert_from_ssa, true);
 494
 495    if (!is_scalar) {
 496       OPT_V(nir_move_vec_src_uses_to_dest);
 497       OPT(nir_lower_vec_to_movs);
 498    }
 499
 500    /* This is the last pass we run before we start emitting stuff.  It
 501     * determines when we need to insert boolean resolves on Gen <= 5.  We
 502     * run it last because it stashes data in instr->pass_flags and we don't
 503     * want that to be squashed by other NIR passes.
 504     */
 505    if (devinfo->gen <= 5)
 506       brw_nir_analyze_boolean_resolves(nir);
 507
 508    nir_sweep(nir);
 509
 510    if (unlikely(debug_enabled)) {
 511       fprintf(stderr, "NIR (final form) for %s shader:\n",
 512               _mesa_shader_stage_to_string(nir->stage));
 513       nir_print_shader(nir, stderr);
 514    }
 515
 516    return nir;
 517 }
 518
 519 nir_shader *
 520 brw_nir_apply_sampler_key(nir_shader *nir,
 521                           const struct brw_device_info *devinfo,
 522                           const struct brw_sampler_prog_key_data *key_tex,
 523                           bool is_scalar)
 524 {
 525    nir_lower_tex_options tex_options = { 0 };
 526
 527    /* Iron Lake and prior require lowering of all rectangle textures */
 528    if (devinfo->gen < 6)
 529       tex_options.lower_rect = true;
 530
 531    /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
 532    if (devinfo->gen < 8) {
 533       tex_options.saturate_s = key_tex->gl_clamp_mask[0];
 534       tex_options.saturate_t = key_tex->gl_clamp_mask[1];
 535       tex_options.saturate_r = key_tex->gl_clamp_mask[2];
 536    }
 537
 538    /* Prior to Haswell, we have to fake texture swizzle */
 539    for (unsigned s = 0; s < MAX_SAMPLERS; s++) {
 540       if (key_tex->swizzles[s] == SWIZZLE_NOOP)
 541          continue;
 542
 543       tex_options.swizzle_result |= (1 << s);
 544       for (unsigned c = 0; c < 4; c++)
 545          tex_options.swizzles[s][c] = GET_SWZ(key_tex->swizzles[s], c);
 546    }
 547
 548    tex_options.lower_y_uv_external = key_tex->y_uv_image_mask;
 549    tex_options.lower_y_u_v_external = key_tex->y_u_v_image_mask;
 550    tex_options.lower_yx_xuxv_external = key_tex->yx_xuxv_image_mask;
 551
 552    if (nir_lower_tex(nir, &tex_options)) {
 553       nir_validate_shader(nir);
 554       nir = nir_optimize(nir, is_scalar);
 555    }
 556
 557    return nir;
 558 }
 559
 560 enum brw_reg_type
 561 brw_type_for_nir_type(nir_alu_type type)
 562 {
 563    switch (type) {
 564    case nir_type_uint:
 565    case nir_type_uint32:
 566       return BRW_REGISTER_TYPE_UD;
 567    case nir_type_bool:
 568    case nir_type_int:
 569    case nir_type_bool32:
 570    case nir_type_int32:
 571       return BRW_REGISTER_TYPE_D;
 572    case nir_type_float:
 573    case nir_type_float32:
 574       return BRW_REGISTER_TYPE_F;
 575    case nir_type_float64:
 576       return BRW_REGISTER_TYPE_DF;
 577    case nir_type_int64:
 578    case nir_type_uint64:
 579       /* TODO we should only see these in moves, so for now it's ok, but when
 580        * we add actual 64-bit integer support we should fix this.
 581        */
 582       return BRW_REGISTER_TYPE_DF;
 583    default:
 584       unreachable("unknown type");
 585    }
 586
 587    return BRW_REGISTER_TYPE_F;
 588 }
 589
 590 /* Returns the glsl_base_type corresponding to a nir_alu_type.
 591  * This is used by both brw_vec4_nir and brw_fs_nir.
 592  */
 593 enum glsl_base_type
 594 brw_glsl_base_type_for_nir_type(nir_alu_type type)
 595 {
 596    switch (type) {
 597    case nir_type_float:
 598    case nir_type_float32:
 599       return GLSL_TYPE_FLOAT;
 600
 601    case nir_type_float64:
 602       return GLSL_TYPE_DOUBLE;
 603
 604    case nir_type_int:
 605    case nir_type_int32:
 606       return GLSL_TYPE_INT;
 607
 608    case nir_type_uint:
 609    case nir_type_uint32:
 610       return GLSL_TYPE_UINT;
 611
 612    default:
 613       unreachable("bad type");
 614    }
 615 }