2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "compiler/nir/glsl_to_nir.h"
27 #include "compiler/nir/nir_builder.h"
28 #include "program/prog_to_nir.h"
31 is_input(nir_intrinsic_instr
*intrin
)
33 return intrin
->intrinsic
== nir_intrinsic_load_input
||
34 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
;
38 is_output(nir_intrinsic_instr
*intrin
)
40 return intrin
->intrinsic
== nir_intrinsic_load_output
||
41 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
42 intrin
->intrinsic
== nir_intrinsic_store_output
||
43 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
47 * In many cases, we just add the base and offset together, so there's no
48 * reason to keep them separate. Sometimes, combining them is essential:
49 * if a shader only accesses part of a compound variable (such as a matrix
50 * or array), the variable's base may not actually exist in the VUE map.
52 * This pass adds constant offsets to instr->const_index[0], and resets
53 * the offset source to 0. Non-constant offsets remain unchanged - since
54 * we don't know what part of a compound variable is accessed, we allocate
55 * storage for the entire thing.
57 struct add_const_offset_to_base_params
{
59 nir_variable_mode mode
;
63 add_const_offset_to_base_block(nir_block
*block
, void *closure
)
65 struct add_const_offset_to_base_params
*params
= closure
;
66 nir_builder
*b
= ¶ms
->b
;
68 nir_foreach_instr_safe(block
, instr
) {
69 if (instr
->type
!= nir_instr_type_intrinsic
)
72 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
74 if ((params
->mode
== nir_var_shader_in
&& is_input(intrin
)) ||
75 (params
->mode
== nir_var_shader_out
&& is_output(intrin
))) {
76 nir_src
*offset
= nir_get_io_offset_src(intrin
);
77 nir_const_value
*const_offset
= nir_src_as_const_value(*offset
);
80 intrin
->const_index
[0] += const_offset
->u32
[0];
81 b
->cursor
= nir_before_instr(&intrin
->instr
);
82 nir_instr_rewrite_src(&intrin
->instr
, offset
,
83 nir_src_for_ssa(nir_imm_int(b
, 0)));
91 add_const_offset_to_base(nir_shader
*nir
, nir_variable_mode mode
)
93 struct add_const_offset_to_base_params params
= { .mode
= mode
};
95 nir_foreach_function(nir
, f
) {
97 nir_builder_init(¶ms
.b
, f
->impl
);
98 nir_foreach_block_call(f
->impl
, add_const_offset_to_base_block
, ¶ms
);
104 remap_vs_attrs(nir_block
*block
, void *closure
)
106 GLbitfield64 inputs_read
= *((GLbitfield64
*) closure
);
108 nir_foreach_instr(block
, instr
) {
109 if (instr
->type
!= nir_instr_type_intrinsic
)
112 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
114 if (intrin
->intrinsic
== nir_intrinsic_load_input
) {
115 /* Attributes come in a contiguous block, ordered by their
116 * gl_vert_attrib value. That means we can compute the slot
117 * number for an attribute by masking out the enabled attributes
118 * before it and counting the bits.
120 int attr
= intrin
->const_index
[0];
121 int slot
= _mesa_bitcount_64(inputs_read
& BITFIELD64_MASK(attr
));
123 intrin
->const_index
[0] = 4 * slot
;
130 remap_inputs_with_vue_map(nir_block
*block
, void *closure
)
132 const struct brw_vue_map
*vue_map
= closure
;
134 nir_foreach_instr(block
, instr
) {
135 if (instr
->type
!= nir_instr_type_intrinsic
)
138 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
140 if (intrin
->intrinsic
== nir_intrinsic_load_input
||
141 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
) {
142 int vue_slot
= vue_map
->varying_to_slot
[intrin
->const_index
[0]];
143 assert(vue_slot
!= -1);
144 intrin
->const_index
[0] = vue_slot
;
150 struct remap_patch_urb_offsets_state
{
152 const struct brw_vue_map
*vue_map
;
156 remap_patch_urb_offsets(nir_block
*block
, void *closure
)
158 struct remap_patch_urb_offsets_state
*state
= closure
;
160 nir_foreach_instr_safe(block
, instr
) {
161 if (instr
->type
!= nir_instr_type_intrinsic
)
164 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
166 gl_shader_stage stage
= state
->b
.shader
->stage
;
168 if ((stage
== MESA_SHADER_TESS_CTRL
&& is_output(intrin
)) ||
169 (stage
== MESA_SHADER_TESS_EVAL
&& is_input(intrin
))) {
170 int vue_slot
= state
->vue_map
->varying_to_slot
[intrin
->const_index
[0]];
171 assert(vue_slot
!= -1);
172 intrin
->const_index
[0] = vue_slot
;
174 nir_src
*vertex
= nir_get_io_vertex_index_src(intrin
);
176 nir_const_value
*const_vertex
= nir_src_as_const_value(*vertex
);
178 intrin
->const_index
[0] += const_vertex
->u32
[0] *
179 state
->vue_map
->num_per_vertex_slots
;
181 state
->b
.cursor
= nir_before_instr(&intrin
->instr
);
183 /* Multiply by the number of per-vertex slots. */
184 nir_ssa_def
*vertex_offset
=
186 nir_ssa_for_src(&state
->b
, *vertex
, 1),
187 nir_imm_int(&state
->b
,
188 state
->vue_map
->num_per_vertex_slots
));
190 /* Add it to the existing offset */
191 nir_src
*offset
= nir_get_io_offset_src(intrin
);
192 nir_ssa_def
*total_offset
=
193 nir_iadd(&state
->b
, vertex_offset
,
194 nir_ssa_for_src(&state
->b
, *offset
, 1));
196 nir_instr_rewrite_src(&intrin
->instr
, offset
,
197 nir_src_for_ssa(total_offset
));
206 brw_nir_lower_vs_inputs(nir_shader
*nir
,
207 const struct brw_device_info
*devinfo
,
209 bool use_legacy_snorm_formula
,
210 const uint8_t *vs_attrib_wa_flags
)
212 /* Start with the location of the variable's base. */
213 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
214 var
->data
.driver_location
= var
->data
.location
;
217 /* Now use nir_lower_io to walk dereference chains. Attribute arrays
218 * are loaded as one vec4 per element (or matrix column), so we use
219 * type_size_vec4 here.
221 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
);
223 /* This pass needs actual constants */
224 nir_opt_constant_folding(nir
);
226 add_const_offset_to_base(nir
, nir_var_shader_in
);
228 brw_nir_apply_attribute_workarounds(nir
, use_legacy_snorm_formula
,
232 /* Finally, translate VERT_ATTRIB_* values into the actual registers.
234 * Note that we can use nir->info.inputs_read instead of
235 * key->inputs_read since the two are identical aside from Gen4-5
236 * edge flag differences.
238 GLbitfield64 inputs_read
= nir
->info
.inputs_read
;
240 nir_foreach_function(nir
, function
) {
241 if (function
->impl
) {
242 nir_foreach_block_call(function
->impl
, remap_vs_attrs
, &inputs_read
);
249 brw_nir_lower_vue_inputs(nir_shader
*nir
, bool is_scalar
,
250 const struct brw_vue_map
*vue_map
)
252 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
253 var
->data
.driver_location
= var
->data
.location
;
256 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
257 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
);
259 if (is_scalar
|| nir
->stage
!= MESA_SHADER_GEOMETRY
) {
260 /* This pass needs actual constants */
261 nir_opt_constant_folding(nir
);
263 add_const_offset_to_base(nir
, nir_var_shader_in
);
265 nir_foreach_function(nir
, function
) {
266 if (function
->impl
) {
267 nir_foreach_block_call(function
->impl
, remap_inputs_with_vue_map
,
275 brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
277 struct remap_patch_urb_offsets_state state
;
278 state
.vue_map
= vue_map
;
280 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
281 var
->data
.driver_location
= var
->data
.location
;
284 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
);
286 /* This pass needs actual constants */
287 nir_opt_constant_folding(nir
);
289 add_const_offset_to_base(nir
, nir_var_shader_in
);
291 nir_foreach_function(nir
, function
) {
292 if (function
->impl
) {
293 nir_builder_init(&state
.b
, function
->impl
);
294 nir_foreach_block_call(function
->impl
, remap_patch_urb_offsets
, &state
);
300 brw_nir_lower_fs_inputs(nir_shader
*nir
)
302 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, type_size_scalar
);
303 nir_lower_io(nir
, nir_var_shader_in
, type_size_scalar
);
307 brw_nir_lower_vue_outputs(nir_shader
*nir
,
311 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
,
312 type_size_vec4_times_4
);
313 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4_times_4
);
315 nir_foreach_variable(var
, &nir
->outputs
)
316 var
->data
.driver_location
= var
->data
.location
;
317 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
);
322 brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
324 struct remap_patch_urb_offsets_state state
;
325 state
.vue_map
= vue_map
;
327 nir_foreach_variable(var
, &nir
->outputs
) {
328 var
->data
.driver_location
= var
->data
.location
;
331 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
);
333 /* This pass needs actual constants */
334 nir_opt_constant_folding(nir
);
336 add_const_offset_to_base(nir
, nir_var_shader_out
);
338 nir_foreach_function(nir
, function
) {
339 if (function
->impl
) {
340 nir_builder_init(&state
.b
, function
->impl
);
341 nir_foreach_block_call(function
->impl
, remap_patch_urb_offsets
, &state
);
347 brw_nir_lower_fs_outputs(nir_shader
*nir
)
349 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
,
351 nir_lower_io(nir
, nir_var_shader_out
, type_size_scalar
);
355 type_size_scalar_bytes(const struct glsl_type
*type
)
357 return type_size_scalar(type
) * 4;
361 type_size_vec4_bytes(const struct glsl_type
*type
)
363 return type_size_vec4(type
) * 16;
367 brw_nir_lower_uniforms(nir_shader
*nir
, bool is_scalar
)
370 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
371 type_size_scalar_bytes
);
372 nir_lower_io(nir
, nir_var_uniform
, type_size_scalar_bytes
);
374 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
375 type_size_vec4_bytes
);
376 nir_lower_io(nir
, nir_var_uniform
, type_size_vec4_bytes
);
381 brw_nir_lower_cs_shared(nir_shader
*nir
)
383 nir_assign_var_locations(&nir
->shared
, &nir
->num_shared
,
384 type_size_scalar_bytes
);
385 nir_lower_io(nir
, nir_var_shared
, type_size_scalar_bytes
);
388 #define OPT(pass, ...) ({ \
389 bool this_progress = false; \
390 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
396 #define OPT_V(pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
399 nir_optimize(nir_shader
*nir
, bool is_scalar
)
404 OPT_V(nir_lower_vars_to_ssa
);
407 OPT_V(nir_lower_alu_to_scalar
);
413 OPT_V(nir_lower_phis_to_scalar
);
419 OPT(nir_opt_peephole_select
);
420 OPT(nir_opt_algebraic
);
421 OPT(nir_opt_constant_folding
);
422 OPT(nir_opt_dead_cf
);
423 OPT(nir_opt_remove_phis
);
430 /* Does some simple lowering and runs the standard suite of optimizations
432 * This is intended to be called more-or-less directly after you get the
433 * shader out of GLSL or some other source. While it is geared towards i965,
434 * it is not at all generator-specific except for the is_scalar flag. Even
435 * there, it is safe to call with is_scalar = false for a shader that is
436 * intended for the FS backend as long as nir_optimize is called again with
437 * is_scalar = true to scalarize everything prior to code gen.
440 brw_preprocess_nir(const struct brw_compiler
*compiler
, nir_shader
*nir
)
442 bool progress
; /* Written by OPT and OPT_V */
445 const bool is_scalar
= compiler
->scalar_stage
[nir
->stage
];
447 if (nir
->stage
== MESA_SHADER_GEOMETRY
)
448 OPT(nir_lower_gs_intrinsics
);
450 if (compiler
->precise_trig
)
451 OPT(brw_nir_apply_trig_workarounds
);
453 static const nir_lower_tex_options tex_options
= {
457 OPT(nir_lower_tex
, &tex_options
);
458 OPT(nir_normalize_cubemap_coords
);
460 OPT(nir_lower_global_vars_to_local
);
462 OPT(nir_split_var_copies
);
464 nir
= nir_optimize(nir
, is_scalar
);
467 OPT_V(nir_lower_load_const_to_scalar
);
470 /* Lower a bunch of stuff */
471 OPT_V(nir_lower_var_copies
);
473 /* Get rid of split copies */
474 nir
= nir_optimize(nir
, is_scalar
);
476 OPT(nir_remove_dead_variables
, nir_var_local
);
481 /* Prepare the given shader for codegen
483 * This function is intended to be called right before going into the actual
484 * backend and is highly backend-specific. Also, once this function has been
485 * called on a shader, it will no longer be in SSA form so most optimizations
489 brw_postprocess_nir(nir_shader
*nir
,
490 const struct brw_device_info
*devinfo
,
494 (INTEL_DEBUG
& intel_debug_flag_for_shader_stage(nir
->stage
));
496 bool progress
; /* Written by OPT and OPT_V */
499 nir
= nir_optimize(nir
, is_scalar
);
501 if (devinfo
->gen
>= 6) {
502 /* Try and fuse multiply-adds */
503 OPT(brw_nir_opt_peephole_ffma
);
506 OPT(nir_opt_algebraic_late
);
508 OPT(nir_lower_locals_to_regs
);
510 OPT_V(nir_lower_to_source_mods
);
514 if (unlikely(debug_enabled
)) {
515 /* Re-index SSA defs so we print more sensible numbers. */
516 nir_foreach_function(nir
, function
) {
518 nir_index_ssa_defs(function
->impl
);
521 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
522 _mesa_shader_stage_to_string(nir
->stage
));
523 nir_print_shader(nir
, stderr
);
526 OPT_V(nir_convert_from_ssa
, true);
529 OPT_V(nir_move_vec_src_uses_to_dest
);
530 OPT(nir_lower_vec_to_movs
);
533 /* This is the last pass we run before we start emitting stuff. It
534 * determines when we need to insert boolean resolves on Gen <= 5. We
535 * run it last because it stashes data in instr->pass_flags and we don't
536 * want that to be squashed by other NIR passes.
538 if (devinfo
->gen
<= 5)
539 brw_nir_analyze_boolean_resolves(nir
);
543 if (unlikely(debug_enabled
)) {
544 fprintf(stderr
, "NIR (final form) for %s shader:\n",
545 _mesa_shader_stage_to_string(nir
->stage
));
546 nir_print_shader(nir
, stderr
);
553 brw_create_nir(struct brw_context
*brw
,
554 const struct gl_shader_program
*shader_prog
,
555 const struct gl_program
*prog
,
556 gl_shader_stage stage
,
559 struct gl_context
*ctx
= &brw
->ctx
;
560 const nir_shader_compiler_options
*options
=
561 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
565 /* First, lower the GLSL IR or Mesa IR to NIR */
567 nir
= glsl_to_nir(shader_prog
, stage
, options
);
569 nir
= prog_to_nir(prog
, options
);
570 OPT_V(nir_convert_to_ssa
); /* turn registers into SSA */
572 nir_validate_shader(nir
);
576 nir
= brw_preprocess_nir(brw
->intelScreen
->compiler
, nir
);
578 OPT(nir_lower_system_values
);
579 OPT_V(brw_nir_lower_uniforms
, is_scalar
);
582 OPT_V(nir_lower_samplers
, shader_prog
);
583 OPT_V(nir_lower_atomics
, shader_prog
);
590 brw_nir_apply_sampler_key(nir_shader
*nir
,
591 const struct brw_device_info
*devinfo
,
592 const struct brw_sampler_prog_key_data
*key_tex
,
595 nir_lower_tex_options tex_options
= { 0 };
597 /* Iron Lake and prior require lowering of all rectangle textures */
598 if (devinfo
->gen
< 6)
599 tex_options
.lower_rect
= true;
601 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
602 if (devinfo
->gen
< 8) {
603 tex_options
.saturate_s
= key_tex
->gl_clamp_mask
[0];
604 tex_options
.saturate_t
= key_tex
->gl_clamp_mask
[1];
605 tex_options
.saturate_r
= key_tex
->gl_clamp_mask
[2];
608 /* Prior to Haswell, we have to fake texture swizzle */
609 for (unsigned s
= 0; s
< MAX_SAMPLERS
; s
++) {
610 if (key_tex
->swizzles
[s
] == SWIZZLE_NOOP
)
613 tex_options
.swizzle_result
|= (1 << s
);
614 for (unsigned c
= 0; c
< 4; c
++)
615 tex_options
.swizzles
[s
][c
] = GET_SWZ(key_tex
->swizzles
[s
], c
);
618 if (nir_lower_tex(nir
, &tex_options
)) {
619 nir_validate_shader(nir
);
620 nir
= nir_optimize(nir
, is_scalar
);
627 brw_type_for_nir_type(nir_alu_type type
)
631 case nir_type_uint32
:
632 return BRW_REGISTER_TYPE_UD
;
635 case nir_type_bool32
:
637 return BRW_REGISTER_TYPE_D
;
639 case nir_type_float32
:
640 return BRW_REGISTER_TYPE_F
;
641 case nir_type_float64
:
642 return BRW_REGISTER_TYPE_DF
;
644 case nir_type_uint64
:
645 /* TODO we should only see these in moves, so for now it's ok, but when
646 * we add actual 64-bit integer support we should fix this.
648 return BRW_REGISTER_TYPE_DF
;
650 unreachable("unknown type");
653 return BRW_REGISTER_TYPE_F
;
656 /* Returns the glsl_base_type corresponding to a nir_alu_type.
657 * This is used by both brw_vec4_nir and brw_fs_nir.
660 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
664 case nir_type_float32
:
665 return GLSL_TYPE_FLOAT
;
667 case nir_type_float64
:
668 return GLSL_TYPE_DOUBLE
;
672 return GLSL_TYPE_INT
;
675 case nir_type_uint32
:
676 return GLSL_TYPE_UINT
;
679 unreachable("bad type");