src/mesa/drivers/dri/i965/brw_nir.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_nir.h"
  25 #include "brw_shader.h"
  26 #include "glsl/glsl_parser_extras.h"
  27 #include "glsl/nir/glsl_to_nir.h"
  28 #include "program/prog_to_nir.h"
  29
  30 static bool
  31 remap_vs_attrs(nir_block *block, void *closure)
  32 {
  33    GLbitfield64 inputs_read = *((GLbitfield64 *) closure);
  34
  35    nir_foreach_instr(block, instr) {
  36       if (instr->type != nir_instr_type_intrinsic)
  37          continue;
  38
  39       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
  40
  41       /* We set EmitNoIndirect for VS inputs, so there are no indirects. */
  42       assert(intrin->intrinsic != nir_intrinsic_load_input_indirect);
  43
  44       if (intrin->intrinsic == nir_intrinsic_load_input) {
  45          /* Attributes come in a contiguous block, ordered by their
  46           * gl_vert_attrib value.  That means we can compute the slot
  47           * number for an attribute by masking out the enabled attributes
  48           * before it and counting the bits.
  49           */
  50          int attr = intrin->const_index[0];
  51          int slot = _mesa_bitcount_64(inputs_read & BITFIELD64_MASK(attr));
  52          intrin->const_index[0] = 4 * slot;
  53       }
  54    }
  55    return true;
  56 }
  57
  58 static void
  59 brw_nir_lower_inputs(nir_shader *nir, bool is_scalar)
  60 {
  61    switch (nir->stage) {
  62    case MESA_SHADER_VERTEX:
  63       /* For now, leave the vec4 backend doing the old method. */
  64       if (!is_scalar) {
  65          nir_assign_var_locations(&nir->inputs, &nir->num_inputs,
  66                                   type_size_vec4);
  67          break;
  68       }
  69
  70       /* Start with the location of the variable's base. */
  71       foreach_list_typed(nir_variable, var, node, &nir->inputs) {
  72          var->data.driver_location = var->data.location;
  73       }
  74
  75       /* Now use nir_lower_io to walk dereference chains.  Attribute arrays
  76        * are loaded as one vec4 per element (or matrix column), so we use
  77        * type_size_vec4 here.
  78        */
  79       nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
  80
  81       /* Finally, translate VERT_ATTRIB_* values into the actual registers.
  82        *
  83        * Note that we can use nir->info.inputs_read instead of key->inputs_read
  84        * since the two are identical aside from Gen4-5 edge flag differences.
  85        */
  86       GLbitfield64 inputs_read = nir->info.inputs_read;
  87       nir_foreach_overload(nir, overload) {
  88          if (overload->impl) {
  89             nir_foreach_block(overload->impl, remap_vs_attrs, &inputs_read);
  90          }
  91       }
  92       break;
  93    case MESA_SHADER_GEOMETRY:
  94       foreach_list_typed(nir_variable, var, node, &nir->inputs) {
  95          var->data.driver_location = var->data.location;
  96       }
  97       break;
  98    case MESA_SHADER_FRAGMENT:
  99       nir_assign_var_locations(&nir->inputs, &nir->num_inputs,
 100                                is_scalar ? type_size_scalar : type_size_vec4);
 101       break;
 102    default:
 103       unreachable("unsupported shader stage");
 104    }
 105 }
 106
 107 static void
 108 brw_nir_lower_outputs(nir_shader *nir, bool is_scalar)
 109 {
 110    if (is_scalar) {
 111       nir_assign_var_locations(&nir->outputs, &nir->num_outputs, type_size_scalar);
 112    } else {
 113       nir_foreach_variable(var, &nir->outputs)
 114          var->data.driver_location = var->data.location;
 115    }
 116 }
 117
 118 static void
 119 nir_optimize(nir_shader *nir, bool is_scalar)
 120 {
 121    bool progress;
 122    do {
 123       progress = false;
 124       nir_lower_vars_to_ssa(nir);
 125       nir_validate_shader(nir);
 126
 127       if (is_scalar) {
 128          nir_lower_alu_to_scalar(nir);
 129          nir_validate_shader(nir);
 130       }
 131
 132       progress |= nir_copy_prop(nir);
 133       nir_validate_shader(nir);
 134
 135       if (is_scalar) {
 136          nir_lower_phis_to_scalar(nir);
 137          nir_validate_shader(nir);
 138       }
 139
 140       progress |= nir_copy_prop(nir);
 141       nir_validate_shader(nir);
 142       progress |= nir_opt_dce(nir);
 143       nir_validate_shader(nir);
 144       progress |= nir_opt_cse(nir);
 145       nir_validate_shader(nir);
 146       progress |= nir_opt_peephole_select(nir);
 147       nir_validate_shader(nir);
 148       progress |= nir_opt_algebraic(nir);
 149       nir_validate_shader(nir);
 150       progress |= nir_opt_constant_folding(nir);
 151       nir_validate_shader(nir);
 152       progress |= nir_opt_dead_cf(nir);
 153       nir_validate_shader(nir);
 154       progress |= nir_opt_remove_phis(nir);
 155       nir_validate_shader(nir);
 156       progress |= nir_opt_undef(nir);
 157       nir_validate_shader(nir);
 158    } while (progress);
 159 }
 160
 161 nir_shader *
 162 brw_create_nir(struct brw_context *brw,
 163                const struct gl_shader_program *shader_prog,
 164                const struct gl_program *prog,
 165                gl_shader_stage stage,
 166                bool is_scalar)
 167 {
 168    struct gl_context *ctx = &brw->ctx;
 169    const nir_shader_compiler_options *options =
 170       ctx->Const.ShaderCompilerOptions[stage].NirOptions;
 171    static const nir_lower_tex_options tex_options = {
 172       .lower_txp = ~0,
 173    };
 174    bool debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 175    nir_shader *nir;
 176
 177    /* First, lower the GLSL IR or Mesa IR to NIR */
 178    if (shader_prog) {
 179       nir = glsl_to_nir(shader_prog, stage, options);
 180    } else {
 181       nir = prog_to_nir(prog, options);
 182       nir_convert_to_ssa(nir); /* turn registers into SSA */
 183    }
 184    nir_validate_shader(nir);
 185
 186    if (stage == MESA_SHADER_GEOMETRY) {
 187       nir_lower_gs_intrinsics(nir);
 188       nir_validate_shader(nir);
 189    }
 190
 191    nir_lower_global_vars_to_local(nir);
 192    nir_validate_shader(nir);
 193
 194    nir_lower_tex(nir, &tex_options);
 195    nir_validate_shader(nir);
 196
 197    nir_normalize_cubemap_coords(nir);
 198    nir_validate_shader(nir);
 199
 200    nir_split_var_copies(nir);
 201    nir_validate_shader(nir);
 202
 203    nir_optimize(nir, is_scalar);
 204
 205    /* Lower a bunch of stuff */
 206    nir_lower_var_copies(nir);
 207    nir_validate_shader(nir);
 208
 209    /* Get rid of split copies */
 210    nir_optimize(nir, is_scalar);
 211
 212    brw_nir_lower_inputs(nir, is_scalar);
 213    brw_nir_lower_outputs(nir, is_scalar);
 214    nir_assign_var_locations(&nir->uniforms,
 215                             &nir->num_uniforms,
 216                             is_scalar ? type_size_scalar : type_size_vec4);
 217    nir_lower_io(nir, -1, is_scalar ? type_size_scalar : type_size_vec4);
 218    nir_validate_shader(nir);
 219
 220    nir_remove_dead_variables(nir);
 221    nir_validate_shader(nir);
 222
 223    if (shader_prog) {
 224       nir_lower_samplers(nir, shader_prog);
 225       nir_validate_shader(nir);
 226    }
 227
 228    nir_lower_system_values(nir);
 229    nir_validate_shader(nir);
 230
 231    nir_lower_atomics(nir);
 232    nir_validate_shader(nir);
 233
 234    nir_optimize(nir, is_scalar);
 235
 236    if (brw->gen >= 6) {
 237       /* Try and fuse multiply-adds */
 238       nir_opt_peephole_ffma(nir);
 239       nir_validate_shader(nir);
 240    }
 241
 242    nir_opt_algebraic_late(nir);
 243    nir_validate_shader(nir);
 244
 245    nir_lower_locals_to_regs(nir);
 246    nir_validate_shader(nir);
 247
 248    nir_lower_to_source_mods(nir);
 249    nir_validate_shader(nir);
 250    nir_copy_prop(nir);
 251    nir_validate_shader(nir);
 252    nir_opt_dce(nir);
 253    nir_validate_shader(nir);
 254
 255    if (unlikely(debug_enabled)) {
 256       /* Re-index SSA defs so we print more sensible numbers. */
 257       nir_foreach_overload(nir, overload) {
 258          if (overload->impl)
 259             nir_index_ssa_defs(overload->impl);
 260       }
 261
 262       fprintf(stderr, "NIR (SSA form) for %s shader:\n",
 263               _mesa_shader_stage_to_string(stage));
 264       nir_print_shader(nir, stderr);
 265    }
 266
 267    nir_convert_from_ssa(nir, true);
 268    nir_validate_shader(nir);
 269
 270    if (!is_scalar) {
 271       nir_move_vec_src_uses_to_dest(nir);
 272       nir_validate_shader(nir);
 273
 274       nir_lower_vec_to_movs(nir);
 275       nir_validate_shader(nir);
 276    }
 277
 278    /* This is the last pass we run before we start emitting stuff.  It
 279     * determines when we need to insert boolean resolves on Gen <= 5.  We
 280     * run it last because it stashes data in instr->pass_flags and we don't
 281     * want that to be squashed by other NIR passes.
 282     */
 283    if (brw->gen <= 5)
 284       brw_nir_analyze_boolean_resolves(nir);
 285
 286    nir_sweep(nir);
 287
 288    if (unlikely(debug_enabled)) {
 289       fprintf(stderr, "NIR (final form) for %s shader:\n",
 290               _mesa_shader_stage_to_string(stage));
 291       nir_print_shader(nir, stderr);
 292    }
 293
 294    return nir;
 295 }
 296
 297 enum brw_reg_type
 298 brw_type_for_nir_type(nir_alu_type type)
 299 {
 300    switch (type) {
 301    case nir_type_unsigned:
 302       return BRW_REGISTER_TYPE_UD;
 303    case nir_type_bool:
 304    case nir_type_int:
 305       return BRW_REGISTER_TYPE_D;
 306    case nir_type_float:
 307       return BRW_REGISTER_TYPE_F;
 308    default:
 309       unreachable("unknown type");
 310    }
 311
 312    return BRW_REGISTER_TYPE_F;
 313 }
 314
 315 /* Returns the glsl_base_type corresponding to a nir_alu_type.
 316  * This is used by both brw_vec4_nir and brw_fs_nir.
 317  */
 318 enum glsl_base_type
 319 brw_glsl_base_type_for_nir_type(nir_alu_type type)
 320 {
 321    switch (type) {
 322    case nir_type_float:
 323       return GLSL_TYPE_FLOAT;
 324
 325    case nir_type_int:
 326       return GLSL_TYPE_INT;
 327
 328    case nir_type_unsigned:
 329       return GLSL_TYPE_UINT;
 330
 331    default:
 332       unreachable("bad type");
 333    }
 334 }